HK1165114A

HK1165114A - A portable computing device

Info

Publication number: HK1165114A
Application number: HK12105285.9A
Authority: HK
Inventors: 罗弗戈兰阿玛德雷兹; 达拉比胡曼
Original assignee: 美国博通公司
Priority date: 2010-06-03
Filing date: 2012-05-30
Publication date: 2012-09-28

Description

Portable computing device

Technical Field

The present invention relates to the field of wireless communications, and more particularly, to radio transceivers.

Background

Communication systems are known that support wireless and wired communication between wirelessly and/or wired connected communication devices. These communication systems range from national and/or international cellular telephone systems to the internet and even to point-to-point in-home wireless networks. Various types of communication systems may be separately created and operate in accordance with one or more communication standards. For example, a wireless communication system may operate in accordance with one or more standards including, but not limited to, IEEE802.11, bluetooth, Advanced Mobile Phone Service (AMPS), digital AMPS, global system for mobile communications (GSM), Code Division Multiple Access (CDMA), Local Multipoint Distribution System (LMDS), multi-channel multipoint distribution system (MMDS), Radio Frequency Identification (RFID), enhanced packet radio service (EDGE), General Packet Radio Service (GPRS), WCDMA, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), and/or variations thereof.

Depending on the type of wireless communication system, wireless communication devices (e.g., cellular phones, two-way radios, Personal Digital Assistants (PDAs), Personal Computers (PCs), handheld computers, home entertainment equipment, RFID readers, RFID tags, etc.) communicate directly or indirectly with other wireless communication devices. For direct communication (also known as point-to-point communication), the participating wireless communication devices tune their receivers and transmitters to the same frequency channel (e.g., one or some system-specific radio frequency of the multiple radio frequency carriers of the wireless communication system) and communicate over that frequency channel. For indirect wireless communication, each wireless communication device communicates directly with an associated base station (e.g., for cellular service) and/or with an associated access point (e.g., for an in-home or in-building wireless network) over an assigned frequency channel. To complete the communication link between the wireless communication devices, the associated base stations and/or associated access points communicate directly with each other through the system controller, through the public switched telephone network, through the internet, and/or through some other wide area network.

For each wireless communication device participating in wireless communication, it includes a built-in radio transceiver (i.e., receiver and transmitter) or is connected to an associated radio transceiver (e.g., a base station, RF modem, etc. for a home and/or in-building wireless communication network). The known receiver is connected to an antenna and comprises a low noise amplifier, one or more intermediate frequency stages (stages), a filtering stage and a data recovery stage. The low noise amplifier receives the inbound RF signal through the antenna and then amplifies it. The one or more intermediate frequency stages mix the amplified RF signal with one or more local oscillations, thereby converting the amplified RF signal to a baseband signal or an intermediate frequency signal. The filtering stage filters the baseband signal or the intermediate frequency signal to attenuate unwanted out-of-band signals to generate a filtered signal. The data recovery stage recovers data in the filtered signal in accordance with a particular wireless communication standard.

The known transmitter comprises a data modulation stage, one or more intermediate frequency stages and a power amplifier. The data modulation stage converts the data to baseband signals according to a particular wireless communication standard. One or more intermediate frequency stages mix the baseband signal with one or more local oscillations to produce an RF signal. The power amplifier amplifies the RF signal and then transmits it through the antenna.

To implement a radio transceiver, a wireless communication device includes a plurality of integrated circuits and a plurality of discrete components. Fig. 1 illustrates an example of a wireless communication device that supports 2G and 3G cellular telephone protocols. As shown, the wireless communication device includes a baseband processing IC, a power management IC, a radio transceiver IC, a transmit/receive (T/R) switch, an antenna, and a number of discrete components. The discrete components include Surface Acoustic Wave (SAW) filters, power amplifiers, duplexers, inductors, and capacitors. These discrete components add to the material cost of the wireless communication device, but they are not necessary to achieve the precise performance requirements of the 2G and 3G protocols.

With the development of integrated circuit process technology, wireless communication device manufacturers desire wireless transceiver IC manufacturers to upgrade their ICs in accordance with advances in the IC manufacturing process. For example, due to a change in the manufacturing process (e.g., using a smaller transistor model), the wireless transceiver IC is redesigned for the updated manufacturing process. As most digital circuits shrink with the IC manufacturing process, redesigning the digital portion of the IC is a relatively simple process. However, since most analog circuits (e.g., inductors, capacitors, etc.) do not scale down with the IC process, redesigning the analog portion is not a straightforward task. Therefore, wireless transceiver IC manufacturers have invested great efforts in producing ICs using newer IC manufacturing processes.

Disclosure of Invention

The present invention provides an apparatus and method of operation, and further description is provided in the following brief description of the drawings and detailed description, and in the claims.

According to an aspect of the present invention, there is provided a portable computing device (computing device) comprising:

a front end module for connecting to the antenna section and for separating one or more outbound radio frequency signals from one or more inbound radio frequency signals;

a surface-acoustic-wave (less-SAW) -free receiver for:

converting the one or more inbound radio frequency signals to one or more inbound intermediate frequency signals by:

frequency converting the baseband filter response to at least one of an intermediate frequency filter response and a radio frequency filter response;

filtering the one or more inbound RF signals according to the RF filter response when the baseband filter response is transduced to the RF filter response; and

filtering the one or more inbound intermediate frequency signals according to the intermediate frequency filter response when the baseband filter response is converted to the intermediate frequency filter response; and

converting the one or more inbound intermediate frequency signals to one or more inbound symbol streams;

a saw-less transmitter for converting one or more outbound symbol streams into the one or more outbound radio frequency signals; and

a baseband processing unit to:

converting outbound data into the one or more outbound symbol streams; and

converting the one or more inbound symbol streams to inbound data.

Preferably, the portable computing device further comprises:

the front-end module is further configured to separate one or more second outbound radio frequency signals from one or more second inbound radio frequency signals, wherein the one or more inbound and outbound radio frequency signals are located in a first frequency band and the one or more second inbound radio frequency signals are located in a second frequency band;

the saw-less receiver is further configured to:

converting the one or more second inbound radio frequency signals to one or more second inbound intermediate frequency signals, wherein:

frequency converting the second baseband filter response to at least one of a second intermediate frequency filter response and a second radio frequency filter response;

filtering the one or more second inbound RF signals according to the second RF filter response when the second baseband filter response is frequency converted to the second RF filter response; and

filtering the one or more second inbound intermediate frequency signals according to the second intermediate frequency filter response when the second baseband filter response is converted to the second intermediate frequency filter response; and

converting the one or more second inbound intermediate frequency signals to one or more second inbound symbol streams;

the saw-less transmitter is further configured to convert one or more second outbound symbol streams into the one or more second outbound radio frequency signals; and

the baseband processing unit is further configured to:

converting second outbound data into the one or more second outbound symbol streams; and

converting the one or more second inbound symbol streams to second inbound data.

Preferably, the front end module includes:

an antenna tuning unit connected with the antenna part and tuned to provide an impedance matching the impedance of the antenna part;

one or more power amplifiers for amplifying the one or more outbound radio frequency signals to produce one or more amplified outbound radio frequency signals;

a splitting module coupled to the SAW-less receiver, the antenna tuning unit, and the one or more power amplifiers, the splitting module configured to:

outputting the one or more amplified outbound radio frequency signals to the antenna tuning unit; and

attenuating the one or more amplified outbound radio frequency signals in connection of the separation module with the surfaceless receiver to separate the one or more inbound radio frequency signals from the one or more outbound radio frequency signals.

Preferably, the baseband processing unit is further configured to generate at least one of:

an antenna tuning unit control signal for adjusting an impedance of the antenna tuning unit according to a change in the impedance of the antenna part;

a separation control signal for adjusting attenuation of the one or more outbound RF signals; and

a power amplifier control signal to adjust one or more parameters of the one or more power amplifiers.

Preferably, the surface wave-less launcher comprises:

an up-conversion mixing module for converting the one or more outbound symbol streams into one or more up-converted signals;

a transmit variable frequency bandpass filter for:

frequency converting the second baseband filter response to a second radio frequency band pass filter response; and

filtering the one or more upconverted signals according to the second radio frequency band-pass filter response to produce one or more filtered upconverted signals; and

an output module for conditioning (conditioning) the one or more filtered upconverted signals to produce one or more conditioned upconverted signals; and

a power amplifier driver to amplify the one or more conditioned upconverted signals to generate the one or more outbound radio frequency signals.

Preferably, the baseband processing unit is further configured to:

generating a transmitter control signal for adjusting at least one of: the second baseband filter response, the second radio frequency band pass filter response, and parameters of the power amplifier driver.

Preferably, the surface wave-less receiver comprises:

a radio-intermediate frequency receiver section comprising:

a low noise amplifier for amplifying the one or more inbound radio frequency signals to produce one or more amplified inbound radio frequency signals;

an intermediate frequency down conversion module for converting the one or more amplified inbound RF signals to the one or more inbound intermediate frequency signals; and

a variable frequency bandpass filter having the radio frequency bandpass filter response for filtering the one or more inbound radio frequency signals or filtering the one or more inbound intermediate frequency signals; and

an intermediate frequency-baseband receiver section to convert the one or more inbound intermediate frequency signals into one or more inbound symbol streams.

Preferably, the baseband processing unit is further configured to:

generating a receiver control signal for adjusting at least one of: the baseband filter response, the radio frequency band pass filter response, and parameters of the low noise amplifier.

Preferably, the portable computing device further comprises:

a first integrated circuit to support the baseband processing unit, the surface wave free receiver, and the surface wave free transmitter; and

a second integrated circuit for supporting the front end module.

Preferably, the portable computing device further comprises at least one of:

a processing module to:

executing one or more portable computing device functions to generate the outbound data; and

performing the one or more portable computing device functions to process the input data; and

a power management unit to perform one or more power management functions of the portable computing device.

According to another aspect, a portable computing device is presented, comprising:

a front end module, the front end module comprising:

a plurality of power amplifiers, wherein a power amplifier of the plurality of power amplifiers amplifies a first outbound radio frequency signal of a plurality of outbound radio frequency signals;

a plurality of splitting modules, wherein a splitting module of the plurality of splitting modules splits a first inbound radio frequency signal of a plurality of inbound radio frequency signals from the first outbound radio frequency signal; and

at least one antenna tuning unit for providing an impedance matched to an impedance of an antenna section according to a control signal, wherein the antenna tuning unit receives the first inbound radio frequency signal from the antenna section and outputs the first outbound radio frequency signal to the antenna section;

a saw-less receiver for converting the plurality of inbound RF signals into a plurality of inbound symbol streams;

a saw-less transmitter for converting a plurality of outbound symbol streams into the plurality of outbound radio frequency signals; and

a baseband processing unit to:

generating the control signal according to the impedance change of the antenna part;

converting a plurality of outbound data into the plurality of outbound symbol streams; and

converting the plurality of inbound symbol streams into a plurality of inbound data.

Preferably, the portable computing device further comprises:

a second power amplifier of the plurality of power amplifiers amplifies a second outbound radio frequency signal of a plurality of outbound radio frequency signals, wherein the first outbound radio frequency signal is located in a first frequency band and the second outbound radio frequency signal is located in a second frequency band;

a second splitting module of the plurality of splitting modules splits a second inbound radio frequency signal of a plurality of inbound radio frequency signals from the second outbound radio frequency signal;

a band switcher connected to the antenna part and the at least one antenna tuning unit; and

a second antenna tuning unit of the at least one antenna tuning unit is configured to provide a second impedance matching an impedance of the antenna section according to a second control signal, wherein the second antenna tuning unit receives the second inbound radio frequency signal from the antenna section through the band switcher and outputs the second outbound radio frequency signal to the antenna section through the band switcher.

Preferably, the separation module is further configured to:

outputting the first outbound radio frequency signal to the at least one antenna tuning unit; and

attenuating the first outbound radio frequency signal in connection of the separation module with the surfaceless receiver to separate the first inbound radio frequency signal from the first outbound radio frequency signal.

Preferably, the portable computing device further comprises:

the baseband processing module generates a separation control signal; and

the separation module adjusts the attenuation of the outbound radio frequency signal.

Preferably, the surface wave-less launcher comprises:

a transmit variable frequency bandpass filter for:

Preferably, the baseband processing unit is further configured to:

Preferably, the surface wave-less receiver comprises:

a radio-intermediate frequency receiver section comprising:

a low noise amplifier section for amplifying the plurality of inbound radio frequency signals to produce a plurality of amplified inbound radio frequency signals;

an intermediate frequency down conversion module for converting the plurality of amplified inbound radio frequency signals to a plurality of inbound intermediate frequency signals; and

a variable frequency bandpass filter having the radio frequency bandpass filter response for filtering the plurality of inbound radio frequency signals or filtering the plurality of inbound intermediate frequency signals; and

an intermediate frequency-baseband receiver section to convert the plurality of inbound intermediate frequency signals into a plurality of inbound symbol streams.

Preferably, the baseband processing unit is further configured to:

Preferably, the portable computing device further comprises:

a first integrated circuit to support the first baseband processing unit, the surface wave free receiver, and the surface wave free transmitter; and

a second integrated circuit for supporting the front end module.

Preferably, the portable computing device further comprises at least one of:

a processing module to:

performing the one or more portable computing device functions to process the input; and

Various advantages, aspects and novel features of the invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

Drawings

FIG. 1 is a schematic block diagram of a prior art wireless communication device;

FIG. 2 is a schematic block diagram of a portable computing communication device in accordance with one embodiment of the present invention;

FIG. 3 is a schematic block diagram of a portable computing communication device according to another embodiment of the present invention;

FIG. 4 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 5 is a schematic block diagram of a portable computing communication device according to another embodiment of the present invention;

FIG. 6 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 7 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 8 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 9 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 10 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 11 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 12 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 13 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 14 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention;

FIG. 15 is a schematic block diagram of an RF-IF receiver portion of a SOC according to one embodiment of the invention;

FIG. 16 is a schematic block diagram of an RF-IF receiver portion of an SOC according to another embodiment of the invention;

FIG. 17 is a schematic block diagram of an RF-IF receiver portion of an SOC according to another embodiment of the invention;

FIG. 18 is a schematic block diagram of an RF-IF receiver portion of a SOC according to another embodiment of the invention;

FIG. 19 is a schematic block diagram of an RF-IF receiver portion of an SOC according to another embodiment of the invention;

FIG. 20 is a schematic block diagram of an RF-IF receiver portion of an SOC according to another embodiment of the invention;

FIG. 21 is a schematic block diagram of an RF-IF receiver portion of an SOC according to another embodiment of the invention;

FIG. 22 is a schematic block diagram of an RF-IF receiver portion of a SOC according to another embodiment of the invention;

FIG. 23 is a schematic block diagram of a transmitter portion of a SOC in accordance with one embodiment of the invention;

FIG. 24 is a schematic block diagram of a transmitter portion of a SOC in accordance with one embodiment of the invention;

fig. 25 is a schematic block diagram of a portion of an RF-IF receiver section including an FTBPF (frequency conversion bandpass filter) according to one embodiment of the present invention;

fig. 26 is a schematic block diagram of a clock generator for an RF-IF receiver section according to one embodiment of the present invention;

fig. 27 is a schematic diagram of a frequency response of an RF-IF receiver section according to one embodiment of the present invention;

FIG. 28 is a schematic block diagram of an FTBPF in accordance with one embodiment of the present invention;

FIG. 29 is a schematic diagram of the phase and frequency response of the baseband component of an FTBPF in accordance with one embodiment of the present invention;

FIG. 30 is a schematic diagram of the phase and frequency response of the RF component of an FTBPF in accordance with one embodiment of the present invention;

fig. 31 is a schematic block diagram of a portion of an RF-IF receiver component incorporating an FTBPF (frequency conversion bandpass filter) according to another embodiment of the invention;

FIG. 32 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 33 is a schematic diagram of the frequency response of an RF-IF receiver component according to another embodiment of the invention;

fig. 34 is a schematic block diagram of a portion of an RF-IF receiver section including an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

FIG. 35 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 36 is a schematic diagram of the frequency response of an RF-IF receiver component according to another embodiment of the invention;

fig. 37 is a schematic block diagram of a portion of an RF-IF receiver section incorporating an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 38 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 39 is a schematic diagram of a frequency response of an RF-IF receiver section according to another embodiment of the present invention;

fig. 40 is a schematic block diagram of a portion of an RF-IF receiver section incorporating an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 41 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 42 is a schematic diagram of a frequency response of an RF-IF receiver section according to another embodiment of the present invention;

fig. 43 is a schematic block diagram of a portion of an RF-IF receiver section including an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 44 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 45 is a schematic block diagram of a portion of an RF-IF receiver section including an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 46 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

FIG. 47 is a schematic block diagram of a complex baseband (BB) filter according to one embodiment of the present invention;

FIG. 48 is a schematic diagram of the conversion of a complex BB filter frequency response to a high Q RF filter frequency response, according to one embodiment of the present invention;

fig. 49 is a schematic block diagram of a portion of an RF-IF receiver section including an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 50 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 51 is a schematic diagram of a frequency response of an RF-IF receiver section according to another embodiment of the present invention;

fig. 52 is a schematic block diagram of a portion of an RF-IF receiver section including an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 53 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 54 is a schematic block diagram of a portion of an RF-IF receiver section incorporating an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 55 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

FIG. 56 is a schematic block diagram of a negative resistance, according to one embodiment of the present invention;

fig. 57 is a schematic block diagram of a portion of an RF-IF receiver section incorporating an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 58 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 59 is a schematic block diagram of a portion of an RF-IF receiver section incorporating an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 60 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention;

fig. 61 is a schematic diagram of the frequency response of the first LO of the RF-IF receiver section according to one embodiment of the present invention;

fig. 62 is a schematic diagram of the frequency response of the second LO of the RF-IF receiver section according to one embodiment of the present invention;

fig. 63 is a schematic block diagram of a portion of an RF-IF receiver section incorporating an FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

fig. 64 is a schematic block diagram of a portion of an RF-IF receiver section including a mixer according to another embodiment of the present invention;

fig. 65 is a schematic block diagram of a clock generator of an RF-IF receiver section according to another embodiment of the present invention;

figure 66 is a schematic block diagram of a transimpedance amplifier (TIA) according to one embodiment of the present invention;

FIG. 67 is a schematic block diagram of a Low Noise Amplifier (LNA) including a FTBPF according to one embodiment of the invention;

FIG. 68 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) according to one embodiment of the present invention;

FIG. 69 is a schematic diagram of the frequency response of a 4-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 70 is a schematic block diagram of a 3-phase FTBPF (frequency conversion bandpass filter) according to another embodiment of the present invention;

FIG. 71 is a schematic diagram of the clock signals for a 3-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 72 is a schematic diagram of the frequency response of a 3-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 73 is a schematic block diagram of a 4-phase FTBPF in accordance with another embodiment of the present invention;

FIG. 74 is a schematic block diagram of a 4-phase FTBPF in accordance with another embodiment of the present invention;

FIG. 75 is a schematic block diagram of a 4-phase FTBPF in accordance with another embodiment of the present invention;

FIG. 76 is a schematic block diagram of a 4-phase FTBPF in accordance with another embodiment of the present invention;

FIG. 77 is a schematic block diagram of the complex baseband impedance of an FTBPF in accordance with one embodiment of the present invention;

FIG. 78 is a schematic block diagram of a 4-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 79 is a schematic block diagram of an m-phase FTBPF according to one embodiment of the present invention;

FIG. 80 is a schematic block diagram of an m-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 81 is a schematic block diagram of an m-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 82 is a schematic block diagram of an m-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 83 is a schematic block diagram of an m-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 84 is a graph illustrating the frequency response of an m-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 85 is a schematic block diagram of a clock generator for an m-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 86 is a schematic block diagram of a clock generator for an m-phase FTBPF according to another embodiment of the present invention;

FIG. 87 is a schematic block diagram of a clock generator for an m-phase FTBPF according to another embodiment of the present invention;

FIG. 88 is a schematic block diagram of a clock generator for a 3-phase FTBPF in accordance with one embodiment of the present invention;

FIG. 89 is a schematic block diagram of a clock generator for a 3-phase FTBPF according to another embodiment of the present invention;

FIG. 90 is a schematic block diagram of a portion of each of a Front End Module (FEM) and SOC in accordance with one embodiment of the invention;

FIG. 91 is a schematic block diagram of a portion of each of a Front End Module (FEM) and a SOC according to another embodiment of the invention;

FIG. 92 is a schematic block diagram of a portion of each of a Front End Module (FEM) and a SOC in accordance with another embodiment of the invention;

FIG. 93 is a schematic block diagram of a portion of each of a Front End Module (FEM) and SOC in a 2G TX mode, in accordance with one embodiment of the present invention;

FIG. 94 is a schematic block diagram of a portion of each of a Front End Module (FEM) and SOC in a 2G TX mode, in accordance with one embodiment of the present invention;

FIG. 95 is a schematic block diagram of a small signal balancing network in accordance with one embodiment of the present invention;

FIG. 96 is a schematic block diagram of a large signal balancing network according to one embodiment of the present invention;

FIG. 97 is a schematic block diagram of a portion of each of a Front End Module (FEM) and SOC in accordance with another embodiment of the invention;

FIG. 98 is a schematic block diagram of a portion of each of a Front End Module (FEM) and SOC in accordance with another embodiment of the invention;

FIG. 99 is a schematic block diagram of a portion of each of a Front End Module (FEM) and a SOC according to another embodiment of the invention;

FIG. 100 is a schematic block diagram of a portion of each of a Front End Module (FEM) and an LNA in accordance with another embodiment of the invention;

FIG. 101 is a schematic block diagram of an equivalent circuit of a portion of each of a Front End Module (FEM) and an LNA in accordance with one embodiment of the invention;

FIG. 102 is a schematic block diagram of a portion of each of a Front End Module (FEM) and an LNA in accordance with another embodiment of the invention;

FIG. 103 is a schematic block diagram of a transformer balun (transformer base) in accordance with one embodiment of the present invention;

FIG. 104 is a schematic diagram of an implementation of a transformer balun (transformer base) in accordance with an embodiment of the present invention;

FIG. 105 is a schematic diagram of an implementation of a transformer balun (transformer balun) according to another embodiment of the present invention;

FIG. 106 is a schematic block diagram of a portion of each of a Front End Module (FEM) and an LNA in accordance with another embodiment of the invention;

FIG. 107 is a schematic block diagram of a portion of each of a Front End Module (FEM) and an LNA in accordance with another embodiment of the invention;

FIG. 108 is a schematic block diagram of impedances in accordance with one embodiment of the present invention;

FIG. 109 is a schematic block diagram of impedances according to another embodiment of the present invention;

FIG. 110 is a schematic block diagram of a balancing network in accordance with one embodiment of the present invention;

FIG. 111 is a schematic block diagram of a balancing network according to another embodiment of the present invention;

FIG. 112 is a schematic block diagram of a negative impedance in accordance with one embodiment of the present invention;

FIG. 113 is a schematic block diagram of a polarization receiver according to one embodiment of the present invention;

FIG. 114 is a schematic block diagram of a buffer circuit according to one embodiment of the present invention;

FIG. 115 is a schematic block diagram of a woven connection in accordance with one embodiment of the present invention;

fig. 116 is a schematic block diagram of a receiver according to one embodiment of the present invention.

Detailed Description

Fig. 2 is a schematic block diagram of an embodiment of a portable computing communication device 10 including a system-on-chip (SOC)12 and a front-end module (FEM)14, where SOC12 and FEM14 are implemented on separate integrated circuits. The portable computing communication device 10 may be any device that can be carried by an individual, is at least partially battery powered, includes a radio transceiver (e.g., radio frequency and/or millimeter wave (MMW)) and executes one or more software applications. For example, the portable computing communication device 10 may be a cellular telephone, a laptop computer, a personal digital assistant, a video game joystick, a video game player, a personal entertainment unit, a desktop computer, or the like.

SOC12 includes saw-less receiver section 18, saw-less transmitter section 20, baseband processing unit 22, processing module 24, and power management unit 26. The saw-less receiver 18 includes a Receiver (RX) Radio Frequency (RF) -Intermediate Frequency (IF) section 28 and a Receiver (RX) IF-baseband (BB) section 30. The RX RF-IF section 28 also includes one or more frequency conversion bandpass filters (FTBPFs) 32.

The processing module 24 and the baseband processing unit 22 may be a single processing device, separate processing devices, or multiple processing devices. The processing device may be a microprocessor, microcontroller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that processes signals (analog and/or digital) according to hard code and/or operational instructions of the circuitry. The processing module 24 and/or the baseband processing unit 22 may have associated memory and/or memory components, which may be a single memory device, multiple memory devices, and/or embedded circuitry of the processing module 24. The memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module 24 and/or the baseband processing unit 22 includes multiple processing devices, the processing devices may be centrally located (e.g., directly connected together via a wired and/or wireless bus section) or distributed (e.g., cloud-computing via an indirect connection via a local area network and/or a wide area network). It is further noted that when the processing module 24 and/or the baseband processing unit 22 performs one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory components storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. It should also be noted that the memory components store, and the processing module 24 and/or baseband processing unit 22 execute, hard code and/or operational instructions related to at least some of the steps and/or functions illustrated in at least one of the figures.

The Front End Module (FEM)14 includes a plurality of Power Amplifiers (PAs) 34-36, a plurality of receiver-transmitter (RX-TX) splitting modules 38-40, a plurality of Antenna Tuning Units (ATUs) 42-44, and a band (FB) switch 46. Note that FEM14 may include more than two paths Pas 34-36 (with RX-TX splitting modules 38-40 and ATUs 42-44 connected to FB switch 46) or may include a single path. For example, FEM14 may include one path for 2G (second generation) cellular services, one path for 3G (third generation) cellular services, and a third path for Wireless Local Area Network (WLAN) services. Of course, many other exemplary path combinations exist in FEM14 to support one or more wireless communication standards (e.g., IEEE802.11, bluetooth, global system for mobile communications (GSM), Code Division Multiple Access (CDMA), Radio Frequency Identification (RFID), enhanced packet radio service (EDGE), General Packet Radio Service (GPRS), WCDMA, High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Long Term Evolution (LTE), WiMAX (worldwide interoperability for microwave access), and/or variations thereof).

In one working example, processing module 24 performs one or more functions of a portable computing device that require wireless transmission of data. At this point, the processing module 24 provides outbound data (e.g., voice, text, audio, video, graphics, etc.) to the baseband processing unit or module 22, and the baseband processing unit or module 22 converts the outbound data into one or more outbound symbol streams in accordance with one or more wireless communication standards (e.g., GSM, CDMA, WCDMA, HSUPA, HSDPA, WiMAX, EDGE, GPRS, IEEE802.11, bluetooth, zigbee, Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), IEEE802.16, data optimization improvement (EV-DO), etc.). Such conversion includes at least one of: scrambling, puncturing (puncturing), encoding, interleaving, constellation mapping, modulation, spreading, frequency hopping, beamforming, space-time block coding, space-frequency block coding, frequency-to-time domain conversion, and/or digital baseband-to-intermediate frequency conversion. Note that the baseband processing unit 22 converts outbound data into a single outbound symbol stream to implement single-input single-output (SISO) communications and/or multiple-input single-output (MISO) communications, and converts outbound data into multiple outbound symbol streams to implement single-input multiple-output (SIMO) and multiple-input multiple-output (MIMO) communications.

The baseband processing unit 22 provides the one or more outbound symbol streams to the saw-less transmitter section 20, and the saw-less transmitter section 20 converts the outbound symbol streams into one or more outbound RF signals (e.g., signals in one or more frequency bands of 800MHz, 1800MHz, 1900MHz, 2000MHz, 2.4GHz, 5GHz, 60GHz, etc.). The saw-less transmitter section 20 includes at least one up-conversion module, at least one frequency conversion band pass filter (FTBPF), and an output module; it may be configured as a direct conversion topology (e.g., direct conversion of a baseband or near baseband symbol stream to an RF signal) or as a super heterodyne topology (e.g., converting a baseband or near baseband symbol stream to an IF signal and then converting the IF signal to an RF signal).

For direct conversion, the saw-less transmitter section 20 may have a cartesian-based topology, a polar-based topology, or a hybrid polarization-cartesian-based topology. In a Cartesian-based topology, the SAW-less transmitter portion 20 combines the in-phase and quadrature components (e.g., A, respectively) of the outbound symbol stream(s)_I(t)cos(ω_BB(t)+Φ_I(t)) and A_Q(t)cos(ω_BB(t)+Φ_Q(t))) and the in-phase and quadrature components of one or more transmit-side local oscillations (TX LO) (e.g., cos (ω), respectively_RF(t)) and sin (ω)_RF(t))) to produce a mixed signal. The FTBPF filters the mixed signals and an output module conditions (e.g., common-mode filtering and/or differential to single-ended) them to generate one or more output upconverted signals (e.g., a (t) cos (ω) signals_BB(t)+Φ(t)+ω_RF(t))). A Power Amplifier Driver (PAD) module amplifies the outbound upconverted signal to generate a pre-power amplified (pre-PA) outbound RF signal.

In a phase polarization based topology, the saw-less transmitter section 20 includes an oscillation (e.g., based on phase information (+/- Δ Φ [ phase shift ]) for generating the outbound symbol stream]And/or phi (t) [ phase modulation ]]Cos (omega) to be regulated_RF(t))). The resulting adjusted oscillation (e.g. cos (ω)_RF(t) +/- Δ Φ) or cos (. omega.) (ω)_RF(t) + Φ (t))) may be further determined by amplitude information of the outbound symbol stream (e.g., a (t) [ amplitude modulation ]]) To produce one or more upconverted signals (e.g., a (t) cos (ω)_RF(t) +/- Δ Φ) or A (t) cos (. omega.) (t)_RF(t) + Φ (t))). The FTBPF filters one or more upconverted signals and an output module conditions (e.g., common mode filtering and/or differential single-ended conversion) them. A Power Amplifier Driver (PAD) module amplifies the outbound upconverted signal to generate a pre-power amplified outbound RF signal.

Based on frequencyIn a polarized topology, the SAW-less transmitter portion 20 includes an oscillator (e.g., frequency shifted according to frequency information (e.g., +/- Δ f [ frequency shift ]) for generating the outbound symbol stream]And/or f (t) [ frequency modulation ]]Cos (omega) to be regulated_RF(t))). The resulting adjusted oscillation (e.g. cos (ω)_RF(t) +/- Δ f) or cos (. omega.) of_RF(t) + f (t))) may be further modulated by amplitude information (e.g., A (t)) [ amplitude modulation ] of the outbound symbol stream]) To produce one or more upconverted signals (e.g., a (t) cos (ω)_RF(t) +/- Δ f) or A (t) cos (. omega.) (t)_RF(t) + f (t))). The FTBPF filters one or more upconverted signals and an output module conditions (e.g., common mode filtering and/or differential single-ended conversion) them. A Power Amplifier Driver (PAD) module amplifies the outbound upconverted signal to generate a pre-power amplified outbound RF signal.

In a mixed polarization-cartesian based topology, the saw-less transmitter section 20 will extract phase information (e.g., cos (ω) for the outbound symbol stream_BB(t) +/- Δ Φ) or cos (. omega.) (ω)_BB(t) + Φ (t))) and amplitude information (e.g., a (t)). The SAW-less transmitter portion 20 transmits the in-phase and quadrature components (e.g., cos (ω), respectively) of the one or more outbound symbol streams_BB(t)+Φ_I(t)) and cos (. omega.) of_BB(t)+Φ_Q(t))) and the in-phase and quadrature components of one or more transmit-side local oscillations (TX LO) (e.g., cos (ω), respectively_RF(t)) and sin (ω)_RF(t))) to produce a mixed signal. The FTBPF filters the mixed signals and an output module conditions (e.g., common mode filtering and/or differential single-ended conversion) them to generate one or more outbound upconverted signals (e.g., a (t) cos (ω)_BB(t)+Φ(t)+ω_RF(t))). A Power Amplifier Driver (PAD) module amplifies the normalized outbound upconverted signal and injects amplitude information (e.g., A (t)) into the normalized outbound upconverted signal to generate a pre-power amplified (pre-PA) outbound RF signal (e.g., A (t) cos (ω [) ω)_RF(t) + Φ (t))). Other examples of the surface acoustic wave-less transmitter section 20 will be described with reference to fig. 23 and 24.

For the super-heterodyne topology, the saw-less transmitter section 20 includesA baseband (BB) -Intermediate Frequency (IF) section and an IF-Radio Frequency (RF) section. The BB-IF section may be a polarization based topology, a cartesian based topology, a hybrid polarization-cartesian based topology, or a hybrid stage of up-converting the outbound symbol stream. In the first three examples, the BB-IF unit generates an IF signal (e.g., A (t) cos (ω)_IF(t) + Φ (t))), the IF-RF section includes a mixing stage, a filtering stage, and a Power Amplifier Driver (PAD) to generate a pre-power amplified outbound RF signal.

When the BB-IF section includes a hybrid stage, the IF-RF section may have a polarization-based topology, a cartesian-based topology, or a hybrid polarization-cartesian-based topology. In this case, the BB-IF section outputs an outbound symbol stream (e.g., A (t) cos ((ω)_BB(t) + Φ (t))) into an intermediate frequency symbol stream (e.g., a (t) cos (ω) and_IF(t) + Φ (t))). The IF-RF section converts the IF symbol stream into a pre-power amplified outbound RF signal.

The saw-less transmitter section 20 outputs a pre-power amplified outbound RF signal to the power amplifier modules (PAs) 34-36 of the Front End Module (FEM) 14. The PAs 34-36 include one or more power amplifiers connected in series and/or parallel with the amplified pre-power amplified RF signal to produce an outbound RF signal. Note that parameters of PAs 34-36 (e.g., gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, stability factor, etc.) may be adjusted based on control signals received from baseband processing unit 22 and/or processing module 24. For example, as transmit conditions change (e.g., the channel changes accordingly, the distance between the TX and RX units changes, antenna properties change, etc.), the processing source of SOC12 (e.g., BB processing unit 22 and/or processing module 24) monitors the transmit condition changes and adjusts the properties of PAs 34-36 to optimize performance. This determination is not made independently; for example, this may be done based on other parameters of the front end modules (e.g., ATUs 42-44, RX-TX separation modules 38-40) that can be adjusted to optimize the transmission and reception of RF signals.

The RX-TX splitting modules 38-40, which may be duplexers, circulators (circulators) or transformer balun or other devices that provide separation of the TX and RX signals using a common antenna, attenuate the outbound RF signal. The RX-TX separation modules 38-40 may adjust its attenuation of the outbound RF signal based on control signals received from the baseband processing unit and/or processing module 24 of the SOC 12. For example, when the transmit power is relatively low, the RX-TX separation module 38-40 may be adjusted to reduce its attenuation of the TX signal.

The Antenna Tuning Units (ATUs) 42-44 are tuned to provide a desired impedance that substantially matches the antenna 16. After tuning, the ATUs 42-44 provide attenuated TX signals from RX-TX separation modules 38-40 to antenna 16 for transmission. Note that ATUs 42-44 may be continuously or periodically adjusted to track changes in the impedance of antenna 16. For example, the baseband processing unit 22 and/or the processing module 24 may detect a change in the impedance of the antenna 16 and provide control signals to the ATUs 42-44 to change their impedances accordingly based on the detected change.

In this example, the saw-less transmitter section 20 has two outputs: one for the first frequency band and the other for the second frequency band. The above discussion has focused on the conversion process of outbound data to outbound RF signals in a single frequency band (e.g., 850MHz, 900MHz, etc.). This process is similar to the conversion of outbound data to RF signals in other frequency bands (e.g., 1800MHz, 1900MHz, 2100MHz, 2.4GHz, 5GHz, etc.). Note that when a single antenna 16 is used, no surface acoustic wave transmitter 20 generates outbound RF signals in other bands and later. A band (FB) switch 46 of the FEM14 connects the antenna 16 to the appropriate output without a surface acoustic wave transmitter output path. The FB switch 46 receives control information from the baseband processing unit 22 and/or the processing module 24 to select a path to connect to the antenna 16.

The antenna 16 also receives one or more inbound RF signals and provides them to one of the ATUs 42-44 through a band (FB) switch 46. The ATUs 22-24 provide inbound RF signals to RX-TX splitting modules 38-40, which RX-TX splitting modules 38-40 route the signals to the Receiver (RX) RF-IF portion of SOC 12. RX RF-IF section 28 converts an inbound RF signal (e.g., A (t) cos (ω)_RF(t) + Φ (t))) into an inbound IF signal (e.g., A)_I(t)cos(ω_IF(t)+Φ_I(t)) and A_Q(t)cos(ω_IF(t)+Φ_Q(t))). Various embodiments of the RXRF-IF section 28 will be illustrated in fig. 15-23 or other figures.

The RX IF-BB section 30 converts the incoming IF signal into one or more incoming symbol streams (e.g., A (t) cos (ω)_BB(t) + Φ (t))). In this case, the RX IF-BB unit 30 includes a mixer unit and a combiner&And a filtering unit. The mixing section mixes the inbound IF signal with a second local oscillation (e.g., LO2 ═ IF-BB, where BB may range from zero to several MHz) to produce I and Q mixed signals. Combination of&The filtering section combines (e.g., adds the mixed signals together-including the sum and differential components) and then filters the combined signal to substantially attenuate the sum component and pass the substantially unattenuated differential component as the inbound symbol stream.

The baseband processing unit 22 converts the inbound symbol streams into inbound data (e.g., voice, text, audio, video, graphics, etc.) according to one or more wireless communication standards (e.g., GSM, CDMA, WCDMA, HSUPA, HSDPA, WiMAX, EDGE, GPRS, IEEE802.11, bluetooth, zigbee, Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), IEEE802.16, data optimization and improvement (EV-DO), etc.). Such conversion may include at least one of: digital intermediate frequency-baseband conversion, time domain-frequency domain conversion, space-time block decoding, space-frequency block decoding, demodulation, spread spectrum decoding, frequency hopping decoding, beamforming decoding, constellation demapping, deinterleaving, decoding, de-puncturing, and/or descrambling. Note that the processing module 24 converts a single inbound symbol stream to inbound data to implement single-input single-output (SISO) communications and/or multiple-input single-output (MISO) communications, and converts multiple inbound symbol streams to inbound data to implement single-input multiple-output (SIMO) and multiple-input multiple-output (MIMO) communications.

A power management unit 26 is integrated in the SOC12 to perform various functions. These functions include monitoring power connections and battery charging, charging the battery as necessary, controlling power to other components of the SOC12, generating a supply voltage, shutting down unnecessary SOC modules, controlling sleep modes of the SOC modules, and/or providing a real time clock. To facilitate generation of the power supply voltage, the power management unit 26 may include one or more switched-mode power supplies and/or one or more linear regulators.

Using such a portable computing communication device 10, expensive and discrete off-chip components, such as SAW filters, duplexers, inductors, and/or capacitors, may be eliminated and their functionality may be incorporated into a front-end module (FEM)14 implemented on a single die. In addition, SAW-less receiver sections and SAW-less transmitter sections provide a facility for eliminating discrete off-chip components.

Fig. 3 is a schematic block diagram of a portable computing communication device 10 according to another embodiment of the present invention, which includes a system on a chip (SOC)52 and another embodiment of a Front End Module (FEM) 50. The SOC 52 includes the power management unit 26, the SAW-less receiver section 18, the SAW-less transmitter section 20, the baseband processing unit 22, and may further include a processing module. The FEM 50 includes a plurality of power amplifier modules (PAs) 34-36, a plurality of RX-TX separation modules 38-40, and at least one Antenna Tuning Unit (ATU) 54.

In the present embodiment, the SOC 52 is configured to support at least two wireless communications (e.g., cellular telephone calls and WLAN communications and/or bluetooth communications) simultaneously. Accordingly, the SAW-less transmitter 20 generates two (or more) different frequency band outbound RF signals in the manner described with reference to fig. 2 and/or with reference to one or more of the following figures. A first one of these outbound RF signals of different frequencies may be provided to one of the PAs 34-36 of the FEM 50 and the other outbound RF signals may be provided to the other PAs 34-36. The functionality of each of the TX-RX separation modules 38-40 is as described with reference to fig. 2 and will be described with reference to at least one of the following figures. The ATU54, tuned according to the control signal from the SOC 52, provides the antenna 16 with both outbound RF signals for transmission.

The antenna 16 also receives two or more different frequency bands of inbound RF signals and provides them to the ATU 54. The ATU54 may include a splitter (splitter) of an impedance matching circuit (e.g., one or more LC circuits) for separating the two inbound RF signals and separating each separated signal; a balun transformer for splitting the signal and splitting the impedance matching circuit; or impedance matching circuits for both signals provided to RX-TX separation modules 38-40.

The RX-TX separation modules 38-40 rely on respective frequency bands that pass only the inbound and outbound RF signals within the respective frequency bands (e.g., 850-900MHz and 1800-1900 MHz). Thus, the first TX-RX splitting modules 38-40 provide the first band inbound RF signal to the first input of the SAW-less RX portion 18, and the second TX-RX splitting modules 38-40 provide the second band inbound RF signal to the second input of the SAW-less RX portion 18. The SAW-less RX portion 18 processes the inbound RF signal to generate the first inbound data and the second inbound data in accordance with the method described with reference to fig. 2 and/or to be described with reference to at least one of the following figures.

Fig. 4 is a schematic block diagram of a portable computing communication device 10 including a System On Chip (SOC)12 or 52 connected to a Front End Module (FEM) network 60 via an RF connection 70 in accordance with another embodiment of the present invention. The SOC12 or 52 includes a power management unit 26, a SAW-less receiver section 18, a SAW-less transmitter section 20, a baseband processing unit 22, and may also include a processing module. The RF connection 70 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable. The FEM network 60 includes a plurality of FEMs 62-68 (e.g., two or more), where each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

Each of FEMs 62-68 may support the same frequency band, different frequency bands, or a combination thereof, respectively. For example, two FEMs may support the same frequency band (e.g., 850-900MHz and 1800-1900MHz), while the other two may support different frequency bands (e.g., 2.4GHz, 5GHz, 60GHz, etc.). In this example, SOC12 or 52 may select one of FEMs 62-68 having the same frequency band based on at least one of a plurality of RF communication parameters (e.g., transmit power level, received signal strength, out-of-band blocker, signal-to-noise ratio, signal-to-interference ratio, operating frequency, interference with other wireless communications, etc.). For example, the SOC12 or 52 selects an FEM that can provide the current best performance level of cellular communications and another FEM that can provide the current best performance level of WLAN, personal area network, or other wireless network communications.

Since each of FEMs 62-68 is programmable, SOC12 or 52 may program selected modules to reduce interference with each other. For example, a FEM supporting cellular communications may be tuned to have additional attenuation within a wireless area network communications band (e.g., 2.4GHz, 5GHz, 60GHz, etc.). Additionally, as conditions (e.g., interference, transmit-receive distances, antenna parameters, environmental factors, etc.) change, the SOC12 or 52 may adjust parameters of the selected FEM to substantially compensate for the change. Alternatively, SOC12 or 52 may select another FEM for at least one of the two communications.

SOC12 or 52 may select multiple FEMs 62-68 to support MIMO, SIMO, and/or MISO communications. For example, in 2 x 2MIMO communications, one FEM may be selected for one of TX/RX MIMO communications and another FEM may be selected for another TX/RX MIMO communications.

The SOC12 or 52 may also select one FEM to support transmission in one frequency band and another FEM to support reception in the same frequency band. For example, the SOC12 or 52 may select a first FEM to support 1800MHz cellular telephone transmission and a second FEM to support 1800MHz cellular telephone reception. As another example, the SOC12 or 52 may select a first FEM to support 1800MHz cellular telephone transmission, a second FEM to support 900MHz cellular telephone transmission, a third FEM to support 1800MHz cellular telephone reception, and a fourth FEM to support 900MHz cellular telephone reception. As another example, the SOC12 or 52 may select a first FEM to support 1800MHz cellular telephone transmission, a second FEM to support 900MHz cellular telephone transmission, and the second FEM to support 1800MHz cellular telephone reception, the first FEM to support 900MHz cellular telephone reception.

FEM network 60 may be implemented on a single die (die) on a single package substrate; implemented on multiple dies on a single substrate (e.g., one on each FEM); each FEM is implemented as a separate Integrated Circuit (IC). In the latter case, at least one of FEMs 62-68 may be located remotely from SOC12 or 52. For example, the portable computing communication device may be a wireless femtocell base station (femtocell) transceiver that supports cellular telephone communications, wherein at least one FEM is physically located a distance (e.g., greater than 1 meter) from SOC12 or 52. In addition, one of the FEMs may be used to communicate with a base station while one or more other FEMs may be used to communicate with other wireless communication devices (e.g., cellular).

For example, the device 10 communicates with a Base Station (BS) using a conventional cellular service while links between the device and other wireless communication devices use another frequency band. The SOC processing module coordinates internet and/or cellular access by other devices and signal conversion of the various links.

As another example, device 10 may be used as a wireless femtocell base station for 1-4 cells or other handheld devices. The wireless local area link between the devices may conform to one or more protocols. One protocol conforms to the legacy cellular standard (e.g., a wireless femtocell allocates local area wireless links as BSs). Another protocol makes wireless femtocell base station devices available as user interface extensions over Internet Protocol (IP) channels. One link of the handset (handset) is connected to an Access Point (AP), or the handset is linked to other devices to form a mesh, thereby logically connecting to the AP by other means.

As another example, device 10 operates as a wireless femtocell (e.g., AP) that uses data calls to the call system to wirelessly access, thereby providing the AP with an IP tunnel that logically connects the AP to an application server anywhere on the internet. For example, the carrier wave need not provide a telephone system interface for voice calls. The IP tunnel passes through the AP to connect, for example, internet phone clients within the domain with the internet phone network. The load and capacity of the data channel from the AP's carriers determines the number of active handsets supported by an AP.

In this example, the link from the AP to the supported wireless devices is not within the cellular band, but rather uses the traditional cellular standard (i.e., the AP resembles a BS and performs the translator function when the handset client is running on the supported wireless devices). Alternatively, the link between device 10 and the supported wireless device uses a proprietary series of call steps that do not belong to the cellular standard. At this time, the AP runs the device client and the device is simply a remote UI extension on the IP channel.

As another example, the device 10 determines whether it should become a femtocell base station for other wireless devices. At this point, the device 10 determines whether it meets a quality threshold (e.g., can give a good and persistent signal, has better battery life, is not used for mobile calls, etc.). If so, it will register with the carrier as a femtocell in the given geographic location. Once registered, it will search for nearby wireless devices (e.g., cells) via point-to-point wireless means (60GHz, TVWS, 2.4GHz, etc.). For the devices it identifies, the device 10 determines the signal strength of the carrier of each wireless device (e.g., they communicate information). For wireless devices with weak or no signal strength per carrier (e.g., BS of the carrier), the device 10 is actively acting as a femtocell host for the wireless device. If the wireless device desires the device 10 to become its own femtocell base station, the device 10 registers itself with the carrier for use as the femtocell base station of the wireless device. Note that this may be a dynamic process between several devices, where one device may act as a femtocell AP for the other device. If the conditions change, one of the other devices may become a femtocell base station AP of the devices, and the device serving as the femtocell base station AP becomes a client of a new femtocell base station AP.

As another example, multiple devices may be mated together to form a femto-network (femto-network). At this time, one device serves as a relay station for one or more other devices for accessing a device serving as a wireless femtocell base station AP. Alternatively, the coordination may include hosting multiple wireless femtocell apparatuses as local apparatuses, and linking them to other APs to provide connectivity. Such sharing may be where one wireless femtocell apparatus provides a cellular voice connection, another provides a cellular data connection, and a third provides a WLAN connection.

As another example, a plurality of devices are in a closed geographic area (e.g., in a car, a room, etc.) and utilize a protocol to determine which device will act as a wireless femtocell AP for other devices and which services to provide. For example, a group of devices, at least one of which can act as a femtocell AP, establish point-to-point links (60GHz, TVWS, 2.4GHz, etc.) with each other, and then determine whether these links can persist over time by comparing nodes on mobile stations that they span time in groups, and whether they are moving substantially together (e.g., in the same car or train, etc.). If they determine that they are in the same mobile vehicle, they will report their own specific average carrier quality measurements to each other. From these quantities, they can determine which handset has the best overall signal for the carrier. Each device may be on a different carrier, or they may all be on the same carrier. In each case, the signals of one device are very different from those of another device, and this difference can be a function of many variables (e.g., position in the vehicle, distance from the vehicle body, etc.). If the best signal is significantly better than what a given device can achieve over its direct carrier link, it will request that the device with the best signal be the master. Once registration is complete, the call will be passed to other devices through the AP host. If the carrier signal is below the threshold, the process repeats and another device may be elected as the new master. In this special case, all devices know which other devices to test, at least until they are out of range of each other.

As another example, for devices participating in a network conference, each device provides a user interface to one person (i.e., device user) at a time. Thus, each device supports substantially the same one-to-one wireless connection using a carrier. In order to reduce redundant traffic and reduce the cost of increasing network capacity, the first device of the netmeeting is actively becoming a wireless femtocell AP for other devices in the same geographical area. If accepted, the first device registers with the carrier and then serves as the wireless femtocell AP of the other device in the teleconference. Extensions of this approach may be applied to any type of audio and/or video conference, whether or not multiple users within a given geographic area will participate in the conference via the portable computing communication device. Another extension may include sharing server-based applications with other devices (e.g., one device is a wireless femtocell AP accessing an internet-hosted application (e.g., a database, a video game, etc.), and the other device accesses the internet-hosted application through the wireless femtocell AP).

As another example, a device serving as a wireless femtocell base station AP is configured according to its environment (e.g., for use in offices, homes, cars, public places, private places, public uses, private uses, etc.). The configuration options include frequency usage patterns, transmit power, number of units for support, centralized femtocell control, distributed femtocell control, allocated capacity, coding levels, symbols, and/or channel access. For example, if in a public place, the device will function as a public wireless femtocell or a private wireless femtocell. When the device is operating as a private femtocell, it selects a configuration that ensures the privacy of the communications it supports.

Fig. 5 is a schematic block diagram of a portable computing communication device 10 including a System On Chip (SOC)12 or 52 connected to a Front End Module (FEM) network 80 via an RF connection 90 in accordance with another embodiment of the present invention. The SOC12 or 52 includes a power management unit 26, a SAW-less receiver section 18, a SAW-less transmitter section 20, a baseband processing unit 22, and may also include a processing module. The RF connection 90 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable. The FEM network 80 includes a plurality of FEMs 62-68 (e.g., two or more) and a frequency conversion module 82. The frequency conversion module 82 includes one or more bypass RF-to-RF conversion modules. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

The function of SOC12 or 52 and FEMs 62-68 is similar to SOC12 or 52 and FEMs 62-68 in FIG. 4. In this embodiment, the inbound RF signals from the FEM and/or the outbound RF signals from the SOC12 or 52 may be frequency converted prior to routing between the SOC12 or 52 and the respective FEM. For example, the SOC12 or 52 may form a baseband function for processing incoming and outgoing RF signals at a carrier frequency of 2.4GHz, but with symbol streams generated according to a plurality of standardized wireless protocols and/or proprietary protocols. At this point, the SOC12 or 52 generates an outbound symbol stream in accordance with the given wireless protocol and upconverts the symbol stream to an RF signal having a carrier frequency of 2.4 GHz.

An RF-RF frequency conversion module 86, which includes a local oscillator, a mixing module and filtering, mixes the outbound RF signal with the local oscillator to produce a mixed signal. The filtering section filters the mixed signal to generate an outbound RF signal at a desired carrier frequency (e.g., 900MHz, 1800MHz, 1900MHz, 5GHz, 60GHz, etc.). Note that the frequency conversion module 82 may include multiple RF-to-RF conversion modules (one or more for increasing the carrier frequency and/or one or more for decreasing the carrier frequency). In this regard, implementations of the generic SOC12 or 52 may be coupled with various implementations of the FEM network 80 (e.g., number of FEM modules 62-68, number of RF-RF conversion modules, etc.) to form various portable computing communication devices.

Fig. 6 is a schematic block diagram of a portable computing communication device 10 including a plurality of Systems On Chip (SOCs) 12 or 52 connected to a Front End Module (FEM) network 60 via RF connections 78 in accordance with another embodiment of the present invention. Each SOC12 or 52 includes a power management unit 26, a SAW-less receiver section 18, a SAW-less transmitter section 20, a baseband processing unit 22, respectively, and may also include a processing module. The RF connection 78 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable. The FEM network 60 includes a plurality of FEMs 62-68 (e.g., two or more), where each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

In the present embodiment, one SOC12 or 52 uses at least one of FEMs 62-68 to support one or more wireless communications (e.g., cellular, WLAN, WPAN, etc.), and the other SOC 12-52 uses one or more other FEMs 62-68 to support one or more other wireless communications. To reduce interference between wireless communications and/or to optimize each wireless communication, at least one SOC12 or 52 provides control signals to FEMs 62-68 to adjust its performance. In addition to the example of using different FEMs 62-68 for each SOC12 or 52, in another example, two or more SOCs 12 or 52 may share FEMs 62-68 in a time-division manner via a switching module (not shown). In yet another example, one SOC12 or 52 may use one path of FEMs 62-68 and the other SOC12 or 52 may use at least one of the other paths of FEMs 62-68.

Fig. 7 is a schematic block diagram of a portable computing communication device 10 including a plurality of Systems On Chip (SOCs) 12 or 52 connected to a Front End Module (FEM) network 80 via RF connections 90 in accordance with another embodiment of the present invention. The SOC12 or 52 includes a power management unit 26, a SAW-less receiver section 18, a SAW-less transmitter section 20, a baseband processing unit 22, and may also include a processing module. The RF connection 90 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable. The FEM network 80 includes a plurality of FEMs 62-68 (e.g., two or more) and a frequency conversion module 82. The frequency conversion module 82 includes one or more bypass RF-to-RF conversion modules. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

In the present embodiment, one SOC12 or 52 uses at least one of FEMs 62-68 to support one or more wireless communications (e.g., cellular, WLAN, WPAN, etc.), and the other SOC 12-52 uses one or more other FEMs 62-68 to support one or more other wireless communications. To reduce interference between wireless communications and/or to optimize each wireless communication, at least one SOC12 or 52 provides control signals to FEMs 62-68 to adjust its performance. In addition, at least one wireless communication may be passed through the frequency conversion module 82 to increase or decrease the carrier frequency of the wireless communication.

Fig. 8 is a schematic block diagram of a portable computing communication device 10 including a System On Chip (SOC)100 connected to a Front End Module (FEM) network 60 via an RF connection 70 in accordance with another embodiment of the present invention. The SOC 100 includes a power management unit 26, a plurality of SAW-less receiver sections 18-1-18-2, a plurality of SAW-less transmitter sections 20-1-20-2, one or more baseband processing units 22, and may also include processing modules. The RF connection 70 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable. The FEM network 60 includes a plurality of FEMs 62-68 (e.g., two or more), where each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

In the present embodiment, SOC 100 is capable of multiple concurrent wireless communications using at least one of FEMs 62-68. For example, one SAW-less transmitter & receiver pair may be used for WLAN communications and another SAW-less transmitter & receiver pair may be used for 850 or 900MHz cellular telephone communications. As another example, one SAW-less transmitter & receiver pair may be used for cellular voice communications and another SAW-less transmitter & receiver pair may be used for cellular data communications. Note that these concurrent wireless communications may be in the same frequency band with different carrier frequencies and/or in different frequency bands.

Fig. 9 is a schematic block diagram of a portable computing communication device 10 including a System On Chip (SOC)100 connected to a Front End Module (FEM) network 80 via an RF connection 70 in accordance with another embodiment of the present invention. The SOC 100 includes a power management unit 26, a plurality of SAW-less receiver sections 18-1-18-2, a plurality of SAW-less transmitter sections 20-1-20-2, one or more baseband processing units 22, and may also include processing modules. The RF connection 70 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable. The FEM network 80 includes a plurality of FEMs 62-68 (e.g., two or more) and a frequency conversion module. The frequency conversion module 82 includes one or more bypass RF-to-RF conversion modules. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

In this embodiment, the SOC 100 is capable of multiple concurrent wireless communications using at least one of the FEMs 62-68, and the carrier frequency of at least one wireless communication may be converted by the frequency conversion module 82. For example, one SAW-less transmitter & receiver pair may be used for WLAN communications and another SAW-less transmitter & receiver pair may be used for 850 or 900MHz cellular telephone communications. As another example, one SAW-less transmitter & receiver pair may be used for cellular voice communications and another SAW-less transmitter & receiver pair may be used for cellular data communications. In any of the above examples, the carrier frequency of at least one wireless communication may be increased or decreased by the frequency conversion module 82.

Fig. 10 is a schematic block diagram of a portable computing communication device 10 including a System On Chip (SOC)110 connected to a Front End Module (FEM) network 120 via an RF connection 122 in accordance with another embodiment of the present invention. The SOC110 includes a power management unit 26, an Intermediate Frequency (IF) -baseband (BB) receiver section 112, a BB-IF transmitter section 114, a baseband processing unit 22, and may further include a processing module. The RF connection 122 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable.

The FEM network 120 includes a plurality of FEMs 62-68 (e.g., two or more) and a plurality of RF-IF TX and RX section pairs 124-138. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Each of the TX IF-RF sections 132-138 includes a polarization based topology, a cartesian based topology, a hybrid polarization-cartesian based topology, or a mixing, filtering & mixing module, respectively. Each of the RX RF-IF sections 124 and 130 includes a low noise amplifier section and a down conversion section, respectively. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

In the present embodiment, the baseband processing module 22 converts the outbound data into one or more outbound symbol streams in accordance with one or more wireless communication protocols. The TX BB-IF section 114 includes a mixing module that mixes the outbound symbol stream with a transmit IF local oscillation (e.g., an oscillation having a frequency of tens of MHz to tens of GHz) to produce one or more outbound IF signals.

The SOC110 provides the outbound IF signal to the FEM network 120 over an RF connection 122. In addition, SOC110 provides selection signals indicating which of the RX-TX section pairs 124 and 130 and the corresponding FEMs 62-68 will support wireless communications. The selected TX IF-RF section 132-138 mixes the IF signal with a second local oscillation (e.g., an oscillation at a frequency RF-IF) to produce one or more mixed signals. The combine & filter section combines one or more of the mixed signals and filters them to produce a pre-PA outbound RF signal to be provided to the respective FEMs 62-68.

For inbound RF signals, the antenna associated with the FEMs 62-68 receives the signal and provides it to a band Switch (SW), if included, or to an ATU, if not included. The FEMs 62-68 process the inbound RF signals in the manner described above and provide the processed inbound RF signals to the respective RX RF-IF section 124-130. The RX RF-IF section 124 mixes the inbound RF signal with a second RX local oscillation (e.g., an oscillation at a frequency of RF-IF) to generate one or more inbound IF mixed signals (e.g., I and Q mixed signal components or polarization format signals at IF (e.g., A (t) cos (ω) signals)_IF(t)+Φ(t))。

The RX IF-BB section 112 of the SOC110 receives and converts one or more inbound IF mixed signals into one or more inbound symbol streams. The baseband processing module 22 converts the one or more inbound symbol streams into inbound data. Note that SOC110 may include multiple RX IF-BB and TX BB-IF sections to support multiple concurrent wireless communications.

FIG. 11 is a schematic block diagram of a portable computing communication device 10 including a System On Chip (SOC)140 connected to a Front End Module (FEM) network 142 via an RF connection 152 and 154 in accordance with another embodiment of the present invention. SOC 140 includes power management unit 26, Intermediate Frequency (IF) -baseband (BB) receiver section 144, BB-IF transmitter section 146, baseband processing unit 22, and may further include processing modules. The RF connection 152 and 154 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable.

The FEM network 142 includes a plurality of FEMs 62-68 (e.g., two or more) and a pair of RF-IF TX and RX sections 148-150. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. The TX IF-RF section 150 includes a polarization-based topology, a cartesian-based topology, a hybrid polarization-cartesian-based topology, or a mixing, filtering & mixing module. The RX RF-IF section 148 includes a low noise amplifier section and a down-conversion section. Note that the structure of at least one of FEMs 62-68 is as described with reference to FIG. 3.

In the present embodiment, the baseband processing module 22 converts the outbound data into one or more outbound symbol streams in accordance with one or more wireless communication protocols. The TX BB-IF section 146 includes a mixing module that mixes the outbound symbol stream with a transmit IF local oscillation (e.g., an oscillation having a frequency of tens of MHz to tens of GHz) to produce one or more outbound IF signals.

The SOC 140 provides outbound IF signals to the FEM network 142 via RF connections 152 and 154. The TXIF-RF section 150 mixes the IF signal with a second local oscillation (e.g., an oscillation at a frequency RF-IF) to produce one or more mixed signals. The combine & filter section combines one or more of the mixed signals and filters them to produce a pre-PA outbound RF signal to be provided to the respective FEMs 62-68.

For inbound RF signals, the antenna associated with the FEMs 62-68 receives the signal and provides it to a band Switch (SW), if included, or to an ATU, if not included. The FEMs 62-68 process the inbound RF signals in the manner described above and provide the processed inbound RF signals to the RX RF-IF section 148. The RX RF-IF section 148 mixes the inbound RF signal with a second RX local oscillation (e.g., an oscillation at a frequency of RF-IF) to generate one or more inbound IF mixed signals (e.g., I and Q mixed signal components or a polarization format signal at IF (e.g., A (t) cos (ω) signals)_IF(t)+Φ(t))。

RX IF-BB section 144 of SOC 140 receives the one or more inbound IF mixed signals and converts them into one or more inbound symbol streams. The baseband processing module 22 converts the one or more inbound symbol streams into inbound data. Note that SOC 140 may include multiple RX IF-BB144 and TX BB-IF section 146 to support multiple concurrent wireless communications.

Fig. 12 is a schematic block diagram of a portable computing communication device 10 including a System On Chip (SOC)160 connected to a Front End Module (FEM) network 162 via an RF connection 176 according to another embodiment of the present invention. SOC 160 includes power management unit 26, SAW-less Receiver (RX) down conversion section 164, SAW-less Transmitter (TX) up conversion section 166, baseband processing unit 22, and may also include processing modules. The RF connection 176 may be at least one of a coaxial cable, a flexible fiber optic cable, a flexible waveguide, and/or other high frequency cable.

The FEM network 162 includes a plurality of FEMs 168 and 174 (e.g., two or more) and a pair of RF-IF TX and RX sections. Each of the FEMs 168-174 includes a plurality of Power Amplifier Drivers (PADs), a plurality of Low Noise Amplifiers (LNAs), a plurality of power amplifier modules (PAs), a plurality of RX-TX splitting modules, at least one Antenna Tuning Unit (ATU), and a band Switch (SW), respectively. Note that the structure of at least one of FEM 168-174 is as described with reference to FIG. 3.

In the present embodiment, the baseband processing module 22 converts the outbound data into one or more outbound symbol streams in accordance with one or more wireless communication protocols. The SAW-less TX up-conversion section 166 converts the outbound symbol stream into one or more outbound up-converted signals, and the SAW-less TX up-conversion section 166 may be implemented similar to the SAW-less TX up-conversion section 166 lacking a power amplifier driver.

The SOC 160 provides the outbound upconverted signal to the FEM network 162 via an RF connection 176. SOC 160 may also provide FEM selection signals to FEM network 162. The selected FEM module receives the outbound upconverted signal through a Power Amplifier Driver (PAD). The PAD amplifies the outbound upconverted signal to produce an outbound RF signal of the pre-PA, which is then processed by the FEM 168-174 in the manner described above and/or as will be described with reference to at least one of the figures below.

For inbound RF signals, the antenna associated with FEM 168-174 receives the signal and provides it to either a band Switch (SW) if included or to an ATU if not included. The ATU and RX-TX separation modules process the inbound RF signals in the manner described above and provide the processed inbound RF signals to the LNA. The LNA amplifies the inbound RF signal to generate an amplified inbound RF signal.

The SAW-less RX portion 164 (similar to the LNA-less SAW receiver portion implementation) receives one or more amplified inbound IF mixing signals and converts them into one or more inbound symbol streams. The baseband processing module 22 converts the one or more inbound symbol streams into inbound data. Note that the baseband processing unit 22 and/or processing module may provide control signals to the LNA and/or PAD of each FEM 168-174 to adjust its performance (e.g., gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot (overshoot), stability factor, etc.).

FIG. 13 is a schematic block diagram of a portable computing communication device including a System On Chip (SOC)180 connected to a Front End Module (FEM)182 in accordance with another embodiment of the invention. SOC 180 includes a plurality of SAW-less receiver sections (only LNAs and frequency conversion bandpass filters (FTBPFs) of the receiver sections are shown), a plurality of SAW-less transmitter sections (only Power Amplifier Drivers (PADs) are shown), a processing module, a baseband processing module (not shown or contained within the processing module), and a power management unit (not shown).

The FEM 182 includes a Low Band (LB) path, a High Band (HB) path, and a band switch (FBSW). The LB path includes a power amplifier module (PA), a low-band impedance stage (LB Z), a low-band low pass filter (LB LPF), a Switch (SW), a transmit-receive splitting module (TX-RX ISO) (e.g., duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). The HB path includes a power amplifier module (PA), a high-band impedance stage (HB Z), a high-band low pass filter (HB LPF), a Switch (SW), a transmit-receive separation module (TX-RX ISO) (e.g., duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). Note that low-band GSM, EDGE, and/or WCDMA wireless communications can be supported using the low-band path, and high-band GSM, EDGE, and/or WCDMA wireless communications can be supported using the high-band path.

As described above and/or as will be described with reference to at least one of the following figures, the SOC 180 is used to output an outbound RF signal of the pre-PA and to input an inbound RF signal. The FEM 182 receives the pre-PA outbound RF signals through the LB path or the HB path and amplifies them through the corresponding PA modules. The impedance stage (LB Z or HB Z) provides the desired load on the output of the PA module and is connected to a low pass filter (LB LPF or HB LPF). The LPF filters the outbound RF signals, which are provided to the TX-RX ISO module or ATU, depending on the configuration of the Switch (SW). If the switch connects the LPF to the TX-RXISO module, the TX-RX module attenuates the outbound RF signals before providing them to the ATU. The function of the ATU is as described above and/or will be described with reference to at least one of the following figures.

Note that there are no discrete components between SOC 180 and FEM 182. In particular, the portable computing communication device does not require a separate SAW filter as is necessary in prior cellular telephone embodiments. At least one of the following contributes to the elimination of SAW filters and/or other conventional external components: the structure of the SAW-less receiver, the structure of the SAW-less transmitter, and/or the programming (programmability) of various components of the FEM 182.

FIG. 14 is a schematic block diagram of a portable computing communication device including a system-on-chip (SOC)190 connected to a front-end module (FEM)192 according to another embodiment of the invention. SOC 190 includes a plurality of SAW-less receiver sections (only LNAs and frequency conversion bandpass filters (FTBPFs) of the receiver sections are shown), a plurality of SAW-less transmitter sections (only Power Amplifier Drivers (PADs) are shown), a processing module, a baseband processing module (not shown or contained within the processing module), and a power management unit (not shown).

The FEM 192 includes a Low Band (LB) path, a High Band (HB) path, and a band switch (FBSW). The LB path includes a power amplifier module (PA), a low-band impedance stage (LB Z), a Switch (SW), a low-band low pass filter (LB LPF), a transmit-receive splitting module (TX-RX ISO) (e.g., duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). The HB path includes a power amplifier module (PA), a high-band impedance stage (HB Z), a Switch (SW), a high-band low pass filter (HB LPF), a transmit-receive separation module (TX-RX ISO) (e.g., duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). Note that low-band GSM, EDGE, and/or WCDMA wireless communications can be supported using the low-band path, and high-band GSM, EDGE, and/or WCDMA wireless communications can be supported using the high-band path.

In various embodiments of SOC 190, a variable frequency bandpass filter in a receiver portion of SOC 190 provides for substantially filtering out-of-band blockers (far-out blocks) and filtering the image signal that produces a non-negligible effect on the desired signal. This will reduce the dynamic range requirements of the analog-to-digital converter (ADC) of the receiver section (output of the baseband processing module or input of the RX BB-IF section). The super-heterodyne structure of the receiver section is advantageous in reducing power consumption and dead zones compared to a comparable direct conversion (comparable direct conversion) receiver section.

FIG. 15 is a schematic block diagram of an RF-IF receiver section 204 of SOC 200 according to one embodiment of the invention, which includes an FEM block (including transformer T1, tunable capacitor network C1, and/or low noise amplifier block (LNA)206), a mixing block 208, a mixing buffer 210 and 212, a frequency conversion bandpass filter (FTBPF) circuit block (including FTBPF 222 and/or other buffers 214 and 220), and a receiver IF-BB section 224. The SOC 200 also includes a SAW-less transmitter section 202, and may also include a baseband processing unit, a processing module, and a power management unit.

In one example of operation, an inbound RF signal is received via an antenna. The inbound RF signal includes both desired signal components of RF and undesired components (higher components are shown) at frequencies above or below RF. Local oscillation (e.g. f) with respect to RF-IF section 204_LO) If the signal is at r_RF-2f_IFAn image signal may appear. Note that RF, as used herein and throughout, includes frequencies in the radio band up to 3GHz as well as frequencies in the 3GHz-300GHz millimeter wave (or microwave) band.

The antenna provides an inbound RF signal to the FEM, which processes the RF signal in a manner described above and/or with reference to at least one of the figures below. Transformer T1 receives and converts the FEM processed inbound RF signal into a differential signal that is filtered by an adjustable capacitance network C1 (e.g., a plurality of series connected switches and capacitors, wherein the plurality are connected in parallel). The adjustable capacitance network C1 receives control signals from the baseband processing unit and/or processing module (e.g., SOC processing resources) to enable the required capacitance.

A low noise amplifier module (LNA)206, including one or more low noise amplifiers connected in series and/or parallel, amplifies the inbound RF signal to produce an amplified inbound RF signal. The LNA206 may receive a control signal from the SOC processing resource, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, and stability factor.

The mixing module 208 receives the amplified inbound RF signal and converts it to an in-phase (I) signal component and a quadrature (Q) signal component using a conversion module (e.g., a pi/2 phase shifter or other type of phase control circuit). One mixer of the mixing module 208 mixes the I signal component with an I signal component of a local oscillation (e.g., fLO) to produce an I mixed signal, and another mixer mixes the Q signal component with a Q signal component of the local oscillation to produce a Q mixed signal. Note that the mixers of the mixing module 208 may be balanced mixers, double balanced mixers, passive switching mixers, gilbert mixers (Gilbertcell mixers), or other types of circuits that multiply two sinusoidal signals and generate a "frequency sum" signal component and a "frequency difference" signal component, respectively. Note also that the I and Q mixed signal may be a differential signal or a single-ended signal; a differential signal is shown.

The mixing buffer 210 filters and/or buffers the I and Q mixed signals, which are then provided to the FTBPF structure (e.g., buffer 214 and 220 and frequency conversion bandpass filter (FTBPF) 222). Note that the I and Q mixed signals each include a desired signal component in IF form, and may also include an image signal component in IF form. It is further noted that the mixing module 208 and/or the mixing buffer 210 and 212 may include filtering to attenuate undesired signal components so that they have little effect on the IF signal components.

FTBPF 222 (various embodiments of which will be described with reference to several figures below) filters the IF signal by attenuating the image IF signal component and by passing the desired IF signal component substantially unattenuated. For example, assume that the FTBPF frequency translates the narrowband baseband bandpass filter response to an IF (e.g., RF-LO) filter response. For this example, it is also assumed that RF is 2GHz, LO2 is 1900GHz, and RF_imageIs 1800 GHz. Based on these assumptions, the mixing module 208 will generate an I mixed signal and a Q mixed signal, the generated signal being a combination of the desired signal and the image signal. In a simplified manner, the I-mixed signal (e.g., cos (RF) cos (LO2)) includes 1/2cos (2000-1900) +1/2cos (2000+1900) of the desired signal component and 1/2cos (1800-1900) +1/2cos (1800+1900) of the image signal component, and the Q-mixed signal (e.g., sin (RF) sin (LO)) includes 1/2cos (2000-1900) -1/2cos (2000+1900) of the desired signal component and the image signal component1/2cos (1800-1900) -1/2cos (1800+ 1900). Note that the 2000+1900 frequency components are filtered out by the post-mixer buffer.

The narrow band of the FTBPF filters out the image frequency (1800-1900) and the undesired signal components, leaving the desired signal component at the frequency (2000-1900). Specifically, what remains is 1/2cos (2000-1900) of the I mixing signal and 1/2cos (2000-1900) from the Q mixing signal. The FTBPF 222 uses these two inputs to achieve the addition of the terms of the desired signal component (e.g., 1/2cos (2000-1900) +1/2cos (2000-1900) ═ cos (2000-1900)), and to achieve the addition of the terms of the mirror signal component (e.g., 1/2cos (1800-1900) -1/2cos (1800-1900) ═ 0 (ideal)). Thus, the image signal component is attenuated while the desired signal component is passed substantially unattenuated.

To enhance the filtering of FTBPF 222, it may receive one or more control signals from the SOC processing resources. The control signal may cause FTBPF 222 to adjust the center frequency of the baseband filter response (changing the center frequency of the high Q IF filter), to change the quality factor of the filter, to change the gain, to change the bandwidth, etc.

The receiver IF-BB section 224 includes a mixing section and a combining & filtering section. The mixing section mixes the inbound IF signal with the second local oscillation to generate an I and Q mixed signal. The combining & filtering section combines the I and Q mixed signals to produce a combined signal, which is then filtered to produce one or more inbound symbol streams.

Although the RF-IF section 204 is currently shown to be connected with a single antenna for SISO (single input single output) communication, the scheme is also applicable to MISO (multiple input single output) communication and MIMO (multiple input multiple output) communication. In these cases, multiple antennas (e.g., 2 or more) are connected with a corresponding number of FEMs (or a smaller number of FEMs depending on the receive path in the FEMs). The FEM is connected to a number of receiver RF-IF sections (e.g., the same number of antennas) which are in turn connected to a corresponding number of receiver IF-BB sections 224. The baseband processing unit processes the plurality of symbol streams to generate inbound data.

RX RF-IF section 204 may include at least one of the following advantages and/or at least one of the following features: the superheterodyne receiver architecture is superior to the corresponding direct conversion receiver in terms of dead zone and power consumption; the frequency shift of the bandpass filter center frequency is achieved in the FTBPF 222 using complex baseband impedance, thereby enabling the center frequency of the on-chip high Q image band-stop filter to be tuned to the desired frequency; and only a signal local oscillator is required which can be used for the down-conversion mixer and the FTBPF 222.

FIG. 16 is a schematic block diagram of an RF-IF receiver section 232 of SOC 230 according to another embodiment of the invention, which includes an FEM interface module (including transformer T1 and/or tunable capacitance network C1), a frequency conversion bandpass filter (FTBPF)234, a low noise amplifier module (LNA)206, a mixing section (including mixing module 208 and/or mixing buffer 210 and 212). SOC 230 also includes receiver IF-BB section 224, SAW-less transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In one example of operation, an inbound RF signal is received via an antenna. The inbound RF signal includes both desired signal components of RF and undesired components (higher components are shown) at frequencies above or below RF. Local oscillation (e.g. f) with respect to RF-IF section 232_LO) If the signal is at r_RF-2f_IFAn image signal may appear. The antenna provides an inbound RF signal to the FEM, which processes the RF signal in a manner described above and/or with reference to at least one of the figures below. Transformer T1 receives the FEM processed inbound RF signal and converts it to a differential signal, which is filtered by adjustable capacitance network C1 according to control signals from the SOC processing resources.

The FTBPF 234 (various embodiments of which will be described with reference to several figures below) filters the inbound RF signal by attenuating the image signal component and the undesired signal component and by substantially unattenuated desired RF signal components. For example, assume that the FTBPF frequency converts the narrowband baseband bandpass filter response to RF (e.g., the carrier frequency of the desired signal component) to produce a high-Q RF filter response. The narrow band high Q RF filter filters out the image signal component and the undesired signal component and passes the substantially unattenuated desired signal component.

A low noise amplifier module (LNA)206 amplifies the desired inbound RF signal component to produce an amplified desired inbound RF signal. The LNA206 may receive a control signal from the SOC 230 processing resource, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, and stability factor.

The mixing module 208 receives the amplified inbound RF signal and converts it to an in-phase (I) signal component and a quadrature (Q) signal component using a pi/2 phase shifter or other type of phase control circuit. One mixer of the mixing module 208 mixes the I signal component with an I signal component of a local oscillation (e.g., fLO) to produce an I mixed signal, and the other mixer mixes the Q signal component with a Q signal component of the local oscillation to produce a Q mixed signal. Note that the signal at which I and Q are mixed may be a differential signal or a single-ended signal; a differential signal is shown.

The mixing buffer buffers the I and Q mixed signals, which are then provided to a filter (e.g., a bandpass filter). Filters 236 and 238 filter the I and Q mixed signals, respectively, which are then provided to the RX IF-BB section 224.

Although the RF-IF section 232 is currently shown to be connected to a single antenna for SISO (single input single output) communication, the scheme is also applicable to MISO (multiple input single output) communication and MIMO (multiple input multiple output) communication. In these cases, multiple antennas (e.g., 2 or more) are connected with a corresponding number of FEMs (or a smaller number of FEMs depending on the receive path in the FEMs). The FEM is connected to a number of receiver RF-IF sections (e.g., the same number of antennas) which are in turn connected to a corresponding number of receiver IF-BB sections 224. The baseband processing unit processes the plurality of symbol streams to generate inbound data.

FIG. 17 is a schematic block diagram of an RF-IF receiver section 242 of SOC 240 according to another embodiment of the invention, which includes a front-end module interface (including transformer T1 and/or adjustable capacitance network C1), a pair of inverter-based low noise amplifier modules (LNA)244 and 246, a mixing module 248, and a pair of transimpedance amplifier modules (including transimpedance amplifier (TIA)250 and 252, impedance (Z)254 and 256, and/or buffer 258 and 260, respectively). SOC 240 also includes receiver IF-BB section 224, SAW-less transmitter section 202, and may also include a baseband processing unit, a processing module, and a power management unit.

In one example of operation, an inbound RF signal is received via an antenna. The inbound RF signal includes both desired signal components of RF and undesired components (higher components are shown) at frequencies above or below RF. Local oscillation (e.g. f) with respect to RF-IF section 204_LO) If the signal is at r_RF-2f_IFAn image signal may appear. The antenna provides an inbound RF signal to the FEM, which processes the RF signal in a manner described above and/or with reference to at least one of the figures below. Transformer T1 receives the FEM processed inbound RF signal and converts it to a differential signal, which is filtered by adjustable capacitance network C1 according to control signals from the SOC 240 processing resources.

The first LNA 244 amplifies a positive term (positive leg) of the inbound RF signal to produce a positive term current (positive leg current) RF signal, and the second LNA 246 amplifies a negative term of the inbound RF signal to produce a negative term current RF signal. LNAs 244 and 246 may each receive control signals from SOC 240 processing resources indicating settings for at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, and stability factor.

The mixing module 248 receives the positive term current RF signal and the negative term current RF signal and converts them to an in-phase (I) current signal and a quadrature (Q) current signal using a pi/2-ary phase shifter or other type of phase control circuit. The mixer of the mixing module 248 mixes the I current signal with a local oscillating (e.g., fLO) I current signal to generate an I mixed current signal (e.g., I_BB-I) And mixing the Q current with the locally oscillated Q current signal to produce a Q-mixed current signal (e.g., i)_BB-Q). Note that the I and Q mixed current signal may be a differential signal or a single-ended signal; a differential signal is shown. Note also that the I and Q mixed current signals include an image component and a desired component, respectively.

TIA250-252 (one or more embodiments of which will be described with reference to at least one of the figures below) receives the I and Q mixed current signals and converts them to a voltage via an impedance (z) such that the resulting I and Q voltage mixed signal has an attenuated image component and a substantially unattenuated desired component. The structure of TIAs 250-252 in combination with impedance (z) provides a low impedance path between their inputs and a reference potential (e.g., Vdd or ground) for frequencies below IF and between their respective inputs for frequencies above IF. For frequencies near IF, TIA250-252 amplifies them and converts them to voltage signals. The buffer provides the I and Q voltage signal components to the RX IF-BB section 224, which converts them to an inbound symbol stream.

RX RF-IF section 224 provides at least one of the following advantages and/or includes at least one of the following features: the superheterodyne receiver architecture is superior to the corresponding direct conversion receiver in terms of dead zone and power consumption; and substantially eliminates the offset and flicker noise problems of a superheterodyne receiver.

FIG. 18 is a schematic block diagram of an RF-IF receiver section 271 of an SOC 270 according to another embodiment of the invention, which includes an FEM interface module (including a transformer T1 and/or an adjustable capacitance network C1), an RF frequency conversion bandpass filter (FTBPF)272, a pair of inverter-based low noise amplifier modules (LNA)274-276, a mixing module 278, a pair of transimpedance amplifier modules (including a transimpedance amplifier (TIA)280-282, an impedance (Z)284-286, and/or a buffer 280-286), and an FTIF BPF 288. SOC 270 also includes receiver IF-BB section 224, SAW-less transmitter section 202, and may also include a baseband processing unit, a processing module, and a power management unit.

In this embodiment, the RF FTBPF 272 functions as described with reference to FIG. 16 and the TIAs 280-282 function as described with reference to FIG. 17. The IF FTBPF 288 is synchronized to the RF clock and has its center frequency at RF. The bandwidth of IF FTBPF 288 is such that the image signal is substantially attenuated and the desired signal component passes substantially unattenuated. Thus, the image signal is filtered three times: by the RF FTBPF 272, by TIAs 280-282, and then by the IF FTBPF 288.

RX RF-IF section 271 provides at least one of the following advantages and/or includes at least one of the following features: using two clocks (e.g., RF and LO 2); the superheterodyne receiver architecture is superior to the corresponding direct conversion receiver in terms of dead zone and power consumption; flicker noise is not important, so the baseband circuit can be small; non-inductive LNAs 274-276 may be used (e.g., the LNAs may be implemented as inverters); no DC offset occurs, so that an offset elimination circuit occupying large space is eliminated; the receiver architecture has frequency planning flexibility comparable to a direct conversion receiver; including an advanced band pass filtering stage across the RX chain; and can be easily integrated into the SOC 270.

FIG. 19 is a schematic block diagram of an RF-IF receiver section 292 of an SOC 290 according to another embodiment of the invention, which includes an FEM interface module (including a transformer T1 and/or an adjustable capacitance network C1), an RF frequency conversion bandpass filter (FTBPF)272, a pair of inverter-based low noise amplifier modules (LNA)274-276, a mixing module 278, a pair of transimpedance amplifier modules (including a transimpedance amplifier (TIA)280-282, an impedance (Z)284-286, and/or a buffer 280-286), and an FTIF BPF 294. SOC 290 also includes receiver IF-BB section 224, SAW-less transmitter section 202, and may also include a baseband processing unit, processing modules, and a power management unit.

In the present embodiment, the IF FTBPF 294 functions as described with reference to fig. 15, and the TIA functions as described with reference to fig. 17. The RF FTBPF 272 is synchronized to the LO clock and is centered at IF. The bandwidth of the RF FTBPF 272 is such that the image signal is substantially attenuated while the desired signal component passes substantially unattenuated. Thus, the image signal is filtered three times: by the RF FTBPF 272, by TIA 280-.

RX RF-IF section 292 provides at least one of the following advantages and/or includes at least one of the following features: using one clock (e.g., LO 2); the superheterodyne receiver architecture is superior to the corresponding direct conversion receiver in terms of dead zone and power consumption; flicker noise is not important, so the baseband circuit can be small; non-inductive LNAs 274-276 may be used (e.g., the LNAs may be implemented as inverters); no DC offset occurs, so that an offset elimination circuit occupying large space is eliminated; the receiver architecture has frequency planning flexibility comparable to a direct conversion receiver; including an advanced band pass filtering stage across the RX chain; and can be easily integrated into SOC 290.

FIG. 20 is a schematic block diagram of a dual-band RF-IF receiver section 302 of a SOC 300 according to another embodiment of the invention, which includes a FEM interface module (including a transformer T1 and/or an adjustable capacitance network C1), a frequency conversion bandpass filter (FTBPF)304, a pair of low noise amplifier modules (LNA)306-308, and a mixing section (including a pair of mixing modules 310-312, a mixing buffer 314-320, and/or a filter 322-328). SOC 300 also includes receiver IF-BB section 224, SAW-less transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In one example of operation, an inbound RF signal is received via an antenna. The inbound RF signal includes one or more desired signal components (e.g., one at f)_RF1And the other is in f_RF2) And undesired components at frequencies above or below RF (components above are shown). Local oscillation about the RF-IF section (one for a first desired RF signal and the other for a second desired RF signal-f_LO1And f_LO2) If the signal is at r_RF1-2f_IF1And/or at r_RF2-2f_IF2One or more image signal components may be present. The antenna provides an inbound RF signal to the FEM, which processes the RF signal in a manner described above and/or with reference to at least one of the figures below. Transformer T1 receives the FEM processed inbound RF signal and converts it to a differential signal, which is filtered by adjustable capacitance network C1 according to control signals from the SOC processing resources.

The FTBPF 304 (various embodiments of which will be described with reference to several figures below) filters the inbound RF signal by attenuating the image signal component and the undesired signal component and by substantially unattenuated desired RF signal components. For example, assume that the FTBPF frequency converts the narrowband baseband bandpass filters to RF1 and RF2 (e.g., carrier frequencies of desired signal components) to produce two high-Q RF filters. The narrow band high Q RF filter filters out the image signal component and the undesired signal component, respectively, and passes the substantially unattenuated desired signal component.

A first low noise amplifier module (LNA) amplifies the desired inbound RF1 signal component (when included in the inbound RF signal) to produce an amplified desired inbound RF1 signal, and a second low noise amplifier module (LNA) amplifies the desired inbound RF2 signal component (when included in the inbound RF signal) to produce an amplified desired inbound RF2 signal. Each LNA may receive a control signal from the SOC processing resource, respectively, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, and stability factor.

A first mixing module of the mixing section receives the amplified desired inbound RF1 signal and converts it to an in-phase (I) signal component and a quadrature (Q) signal component using a pi/2 phase shifter or other type of phase control circuit. The mixer of the first mixing module mixes the I signal component with a local oscillation (e.g. f)_LO1) Is generated to generate a first I mixed signal, and mixes the Q signal component with the locally oscillating Q signal component to generate a first I mixed signalQ mixed signal. Note that the first I and Q mixed signal may be a differential signal or a single-ended signal; a differential signal is shown.

The second mixing module of the mixing section receives the amplified desired inbound RF2 signal and converts it to an in-phase (I) signal component and a quadrature (Q) signal component using a pi/2 phase shifter or other type of phase control circuit. The mixer of the second mixer module couples the I signal component to a local oscillator (e.g., f)_LO2) And mixing the Q signal component with the locally oscillating Q signal component to produce a second Q mixed signal. Note that the second I and Q mixed signal may be a differential signal or a single-ended signal; a differential signal is shown.

Each mixer buffers their respective I and Q mixed signals, which are then provided to a filter (e.g., a bandpass filter). The filter filters the I and Q mixed signals, which are then provided to the RX IF-BB section 224.

Although the RF-IF section 302 is currently shown to be connected with a single antenna for SISO (single input single output) communication, the scheme is also applicable to MISO (multiple input single output) communication and MIMO (multiple input multiple output) communication. In these cases, multiple antennas (e.g., 2 or more) are connected with a corresponding number of FEMs (or a smaller number of FEMs depending on the receive path in the FEM). The FEM is connected to a number of receiver RF-IF sections (e.g. the same number of antennas) which in turn are connected to a corresponding number of receiver IF-BB sections. The baseband processing unit processes the plurality of symbol streams to generate inbound data.

RX RF-IF section 302 provides at least one of the following advantages and/or includes at least one of the following features: using one clock (e.g., LO 2); capable of receiving two inbound RF signals with a single RF input; two external SAW filters are no longer required, one FTBPF 304 effectively filters two channels (e.g., RF1 and RF2 signals); the center frequencies of the two high-Q RF filters are controlled by a local oscillation clock; and can be easily integrated into the SOC 300.

FIG. 21 is a schematic block diagram of an RF-IF receiver section 332 of an SOC 330 according to another embodiment of the invention, which includes an FEM interface module (including a transformer T1 and/or an adjustable capacitance network C1), a low noise amplifier module (LNA)336 with a frequency conversion bandpass filter (FTBPF)338, an RF frequency conversion bandpass filter (FTBPF)334 with negative resistance, and a mixing section (including a mixing module 340, a mixing buffer 342 and/or a filter 346 and 348). SOC 330 also includes receiver IF-BB section 224, SAW-less transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In the present embodiment, parasitic resistance (Rp) is shown in relation to the FEM interface block to represent switching losses (e.g., of FTBPF) and/or inductive losses. The inductive losses are mainly due to the ohmic resistance of the transformer coil (e.g. metal lines on the substrate) and/or the substrate losses under the transformer, which are the main components of the RF section impedance due to the tuning of the capacitor C1. Lower parasitic resistance will reduce the quality factor of the filtering and reduce out-of-band attenuation of frequencies outside the RF. The negative resistance in the FTBPF334 effectively increases the parasitic resistance, thereby increasing the quality factor and out-of-band attenuation.

In one example of operation, an inbound RF signal is received via an antenna. The inbound RF signal includes both desired signal components of RF and undesired components (higher components are shown) at frequencies above or below RF. Local oscillation (e.g. f) with respect to the RF-IF section 332_LO) If the signal is at r_RF-2f_IFAn image signal component may be present. The antenna provides an inbound RF signal to the FEM, which processes the RF signal in a manner described above and/or with reference to at least one of the figures below. Transformer T1 receives the FEM processed inbound RF signal and converts it to a differential signal, which is filtered by adjustable capacitance network C1 according to control signals from the SOC 330 processing resources.

The FTBPF334 (various embodiments of which will be described with reference to several figures below) filters the inbound RF signal by attenuating the image signal component and the undesired signal component and by substantially unattenuated desired RF signal components. For example, assume that FTBPF334 frequency converts a narrowband baseband bandpass filter to RF (e.g., the carrier frequency of the desired signal component) to produce a high Q RF filter. The narrow band high Q RF filter filters out the image signal component and the undesired signal component, respectively, and passes the substantially unattenuated desired signal component. In addition, FTBPF334 includes a negative resistance that is similar to the parasitic resistance (Rp) and compensates for the losses represented by the parasitic resistance (e.g., effectively increasing the quality factor of the filtering and increasing the out-of-band attenuation). The negative resistance may be dynamically adjusted according to changes in parasitic resistance by control signals from the SOC 330 processing resources.

A low noise amplifier module (LNA)336 amplifies the desired inbound RF signal component to produce an amplified desired inbound RF signal. LNA 336 may receive a control signal from the SOC 330 processing resource, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, and stability factor. In addition, LNA 336 may include an RF FTBPF 338, RF TFBPF 338 functioning similarly to RF FTBPF334 described above to further attenuate the image signal component.

The mixing module 340 receives the amplified desired inbound RF signal and converts it to an in-phase (I) signal component and a quadrature (Q) signal component using a pi/2 phase shifter or other type of phase control circuit. The mixer of the mixing module 340 mixes the I signal component with a local oscillator (e.g., f)_LO) And mixing the Q signal component with the locally oscillating Q signal component to produce a Q mixed signal. Note that the signal at which I and Q are mixed may be a differential signal or a single-ended signal; a differential signal is shown.

The mixing buffer buffers the I and Q mixed signals, which are then provided to a filter (e.g., a bandpass filter). The filter filters the I and Q mixed signals, which are then provided to the RXIF-BB section 224.

Although the RF-IF section 332 is currently shown to be connected with a single antenna for SISO (single input single output) communication, the scheme is also applicable to MISO (multiple input single output) communication and MIMO (multiple input multiple output) communication. In these cases, multiple antennas (e.g., 2 or more) are connected with a corresponding number of FEMs (or a smaller number of FEMs depending on the receive path in the FEMs). The FEM is connected to a number of receiver RF-IF sections (e.g. the same number of antennas) which in turn are connected to a corresponding number of receiver IF-BB sections. The baseband processing unit processes the plurality of symbol streams to generate inbound data.

RX RF-IF section 332 provides at least one of the following advantages and/or includes at least one of the following features: off-chip SAW filters and matching components are no longer required; negative resistance increases the quality factor of FTBPF 334; the loss of the inductance can be compensated, so that the inductance has lower tolerance; the requirement for the number of thick metal layers is reduced, thereby reducing the die manufacturing cost; the center frequencies of the two high-Q RF filters are controlled by a local oscillation clock; and can be easily integrated into the SOC 330.

FIG. 22 is a schematic block diagram of an RF-IF receiver section 352 of a SOC 350 according to another embodiment of the invention, which includes an FEM interface module (including a transformer T1 and/or an adjustable capacitance network C1), a frequency-translating bandpass filter (FTBPF)354 having a complex baseband (BB) impedance, a low noise amplifier module (LNA)356, and a mixing section (including a mixing module 340 and/or a mixing buffer 342 and 344). SOC 350 also includes receiver IF-BB section 224, SAW-less transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In one example of operation, an inbound RF signal is received via an antenna. The inbound RF signal includes both desired signal components of RF and undesired components (higher components are shown) at frequencies above or below RF. Local oscillation (e.g. f) with respect to the RF-IF section 332_LO) If the signal is at R_RF-2f_IFAn image signal component may be present. The antenna provides an inbound RF signal to the FEM, which processes the RF signal in a manner described above and/or with reference to at least one of the figures below. The transformer T1 receives the FEM processed inbound RF signal and converts it to differentialIn turn, the tunable capacitance network C1 filters the differential signal according to control signals from the SOC 350 processing resources.

The FTBPF 354 (various embodiments of which will be described with reference to several figures below) filters the inbound RF signal by attenuating the image signal component and the undesired signal component and by substantially unattenuated desired RF signal components. For example, assume that FTBPF 354 frequency converts a narrowband baseband bandpass filter to RF (e.g., the carrier frequency of the desired signal component) to produce a high Q RF filter. The narrow band high Q RF filter filters out the image signal component and the undesired signal component, respectively, and passes the substantially unattenuated desired signal component. The center frequency of the narrowband baseband BPF may be adjusted through the use of a complex baseband impedance 354. The band pass region can be made higher or lower in frequency, for example, depending on the adjustment of the complex BB impedance 354.

A low noise amplifier module (LNA)356 amplifies the desired inbound RF signal component to produce an amplified desired inbound RF signal. The LNA 356 may receive a control signal from the SOC 350 processing resource, where the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, and stability factor.

The mixing module 340 of the mixing section receives the amplified desired inbound RF signal and converts it to an in-phase (I) signal component and a quadrature (Q) signal component using a pi/2 phase shifter or other type of phase control circuit. The mixer of the mixing module 340 mixes the I signal component with a local oscillator (e.g., f)_LO) And mixing the Q signal component with the locally oscillating Q signal component to produce a Q mixed signal. Note that the signal at which I and Q are mixed may be a differential signal or a single-ended signal; a differential signal is shown.

The mixing buffer 342 and 344 buffers the I and Q mixed signals, which are then provided to a filter (e.g., a bandpass filter). The filter 346 and 348 filter the I and Q mixed signals, which are then provided to the RX IF-BB section 224.

Although the RF-IF section 352 is currently shown to be connected to a single antenna for SISO (single input single output) communication, the scheme is also applicable to MISO (multiple input single output) communication and MIMO (multiple input multiple output) communication. In these cases, multiple antennas (e.g., 2 or more) are connected with a corresponding number of FEMs (or a smaller number of FEMs depending on the receive path in the FEM). The FEM is connected to a number of receiver RF-IF sections (e.g. the same number of antennas) which in turn are connected to a corresponding number of receiver IF-BB sections. The baseband processing unit processes the plurality of symbol streams to generate inbound data.

RX RF-IF section 352 provides at least one of the following advantages and/or includes at least one of the following features: the advantages of a superheterodyne receiver over a similar direct conversion receiver are minimal area and power; the use of complex baseband impedance in FTBPF 354 causes the center frequency of the bandpass filter to change; the complex baseband impedance 354 may be implemented with switches and capacitors and its center controlled by the LO clock; tuning an on-chip high-Q image rejection filter (e.g., FTBPF) to a desired frequency using the same LO clock used by the downconversion mixer; the RF-IF section 352 uses a signal Phase Locked Loop (PLL); and can be easily integrated into the SOC 350.

FIG. 23 is a schematic block diagram of a transmitter portion of SOC 360, including an up-conversion mixing module 362, a transmitter local oscillation module (LO)364, a frequency conversion bandpass filter (FTBPF)366, an output module (including a capacitor array 368 and/or a transformer T1) and a Power Amplifier Driver (PAD)372, according to one embodiment of the invention. PAD 372 includes transistors Q1-Q2, resistor R1 and capacitor C1 connected as shown. Note that the capacitor C1 and/or the resistor R1 may be implemented with one or more transistors Q1-Q2. SOC 360 also includes SAW-less receiver section 364 and may also include a baseband processing unit, a processing module, and/or a power management unit.

In one example of operation, the up-conversion mixing module 362 receives baseband (BB) I and Q signals (e.g., analog and quadrature representations of the outbound symbol streams). The up-conversion mixing module 362 may employ a direct conversion topology or a super-heterodyne topology to convert the BB I and Q signals to up-converted signals having a carrier frequency at the desired RF.

FTBPF 366 (various embodiments of which will be described with reference to several figures below) filters the upconverted signal by attenuating out-of-band signal components and by substantially unattenuated upconverting the signal. For example, assume that FTBPF 366 frequency converts a narrowband baseband bandpass filter to RF (e.g., frequency upconverts the carrier frequency of the signal) to produce a high-Q RF filter. The narrowband high-Q RF filter filters out-of-band signals and passes the substantially unattenuated upconverted signal.

The capacitor array 368-370 provides an adjustable low pass filter that filters common mode noise and/or linear noise. Transformer T1 converts the differential up-converted signal to a single-ended signal, which is then amplified by PAD 372. The PAD 372 provides the amplified up-converted signal to the FEM, which further amplifies it, separating it from the inbound RF signal and providing it to the antenna for transmission.

The TX portion provides at least one of the following advantages and/or includes at least one of the following features: the advantages of a superheterodyne receiver over a similar direct conversion receiver are minimal area and power; the use of FTBPF 366 synchronized with TX LO 364 of the transmitter up-conversion mixer LC load reduces transmitter noise and other out-of-band noise at the RX frequency with little impact on the desired TX signal; the baseband impedance of high-Q FTBPF 366 can be implemented with a capacitor, and its center frequency is controlled by TX LO 364; the TX SAW filter is eliminated; and easy integration into SOC 360.

FIG. 24 is a schematic block diagram of a transmitter portion 382 of a SOC 380 that includes an up-conversion mixing module 362, a transmitter local oscillation module (LO), a frequency conversion bandpass filter (FTBPF), an output module (including a capacitor array 368 and/or a transformer T1), and a Power Amplifier Driver (PAD)372, according to another embodiment of the invention. PAD 372 includes a transistor, a resistor, and a capacitor connected as shown. Note that the capacitance and/or resistance may be implemented using one or more transistors. The SOC 380 also includes a SAW-less receiver portion 364 and may also include a baseband processing unit, a processing module, and/or a power management unit.

In this embodiment, the up-conversion mixing module includes a passive mixing structure as shown, which may employ a 50% duty cycle LO clock. In one example of operation, LO I and Q signal components are mixed by the circuitry on the left of the figure, and BB I and Q signal components are mixed by the circuitry on the right of the figure. The mixed LO signal component is then mixed with the mixed BB signal component to produce an upconverted signal. For example, LO I + injects energy into its corresponding capacitance and LO I-extracts energy from the capacitance (or vice versa) to produce a varying voltage across the capacitance at a rate corresponding to LO. LO Q + and LO Q-similarly treat their capacitances, only 90 degrees out of phase. The varying voltages across the capacitors are added together by a summing node to produce a mixed LO signal component. A similar process occurs on the baseband side of the mixer.

TX portion 382 provides at least one of the following advantages and/or includes at least one of the following features: the transistors driven by Vb1 and Vb2 are high voltage transistors (e.g., Vds voltage > 2.5V); and the TX architecture provides a low power high efficiency area design and uses a passive mixer driven by a 50% duty cycle LO clock, reducing power consumption compared to a mixer driven by a 25% duty cycle clock.

Fig. 25 is a schematic block diagram of a portion of an RF-IF receiver section according to one embodiment of the present invention, including a single-ended FTBPF (frequency conversion bandpass filter) 394. This portion of the RX RF-IF section includes transformer T1, variable capacitance network C1, and LNA 392. FTBPF 394 includes a plurality of transistors (e.g., a switching network) and a plurality of baseband impedances (Z)_BB(s))396-402。

In one example of operation, a Front End Module (FEM)390 receives an inbound RF signal via an antenna, processes the RF signal in a manner described above and/or with reference to at least one of the following figures, and provides the inbound RF signal processed by the FEM 390 to a transformer T1. The transformer T1 steps up or down the voltage level of the inbound RF signal, which is then filtered by the variable capacitance network C1. Note that transformer T1 may be omitted if no adjustment to the voltage level of the inbound RF signal is required and/or no separation provided by transformer T1 is required.

The FTBPF 394 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA392 substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated. To implement the filter, the baseband impedance (Z)_BBz(s))396-402 collectively provide a low Q baseband filter with a corresponding filter response, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

The low-Q baseband filter is converted to a desired RF frequency by a clock signal provided by a clock generator 404 to produce a high-Q RF filter. Fig. 27 illustrates the conversion of a low Q baseband filter response to a high Q RF filter response, and fig. 26 illustrates one embodiment of clock generator 404.

As shown in fig. 26, the clock generator (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each having a 25% duty cycle and being sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. The clock generator 404 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal.

Returning to the discussion of fig. 25, FTBPF 394 receives clock signals that are coupled to transistors to in turn couple their respective baseband impedances to the inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (low Q bandpass filter in common) is transferred to RF, thereby implementing a high Q RF bandpass filter.

Fig. 28 is a schematic block diagram of a single-ended FTBPF410 including 4 transistors and 4 capacitors, where the transistors and capacitors provide baseband impedance, according to one embodiment of the invention. The 4 capacitors provide a concentrated baseband impedance that provides a low Q baseband bandpass filter as shown in fig. 29. In particular, the impedance of one capacitor (or 4 in parallel) is 1/sC, where s is 2 π f. Thus, as the frequency (f) approaches zero, the impedance of the capacitor approaches infinity, and as the frequency (f) increases, the impedance of the capacitor decreases. In addition, the phase of the capacitor changes from 90 to-90 at zero frequency.

Returning to the discussion of fig. 28, as the clock signal is applied to the transistors, the capacitors are connected to a common node of the FTBPF410 (e.g., the input of the FTBPF). In this way, the performance of the capacitor can be frequency shifted to the rate of the clock signal (e.g., f) as shown in FIG. 30_LO). Specifically, the impedance of the capacitor (and 4 capacitors in parallel) is shifted to the frequency of the clock. FTBPF410 has a high impedance at the LO due to the near infinite impedance of the LO, and therefore has less effect on signal components at carrier frequencies comparable to the LO. As the frequency deviates from the LO, the impedance of the FTBPF410 decreases, and thus the FTBPF410 effectively "attenuates" (short) signal components whose carrier frequencies are not appropriate for the LO.

Fig. 31 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes a differential FTBPF 412 (frequency conversion bandpass filter). This portion of the RX RF-IF section includes transformer T1, variable capacitance network C1, and LNA 393. The FTBPF 412 includes a plurality of transistors and a plurality of baseband impedances (Z)_BB(s))414-420。

In one example of operation, a Front End Module (FEM)390 receives an inbound RF signal via an antenna, processes the RF signal in a manner described above and/or with reference to at least one of the following figures, and provides the inbound RF signal processed by the FEM 390 to a transformer T1. The transformer T1 converts the single-ended inbound RF signal to a differential inbound RF signal.

The FTBPF 412 provides a differential high Q (quality factor) RF filter that filters the differential inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA393 substantially unattenuated and undesired signal components (e.g., blockers, mirrors, etc.) are attenuated. To implement the filter, the baseband impedance (Z)_BBz(s))414-420 together provide a low Q baseband filter having a corresponding filter response, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

The low Q baseband filter is converted to a desired RF frequency by a clock signal provided by clock generator 422 to produce a high Q RF filter. Fig. 33 illustrates the conversion of a low Q baseband filter response to a high Q RF filter response, and fig. 32 illustrates one embodiment of a clock generator 422.

As shown in fig. 32, clock generator 422 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each having a 25% duty cycle and being sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. The clock generator 422 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal.

Returning to the discussion of fig. 31, FTBPF 412 receives clock signals that are coupled to transistors to in turn connect their respective baseband impedances to the inbound RF signal. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (low Q bandpass filter in common) is transferred to RF, thereby implementing a high Q RF bandpass filter.

Fig. 34 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes a single-ended FTBPF 430 (frequency conversion bandpass filter). This portion of the RX RF-IF section includes transformer T1, variable capacitance network C1, and LNA 392. FTBPF 430 includes a plurality of transistors and a complex baseband filter 432.

The FTBPF 430 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA392 substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated. To implement this filter, complex baseband filter 432 provides a low-Q baseband filter whose bandpass region may be offset by zero frequency. Note that the performance (e.g., bandwidth, attenuation rate, quality factor, frequency offset, etc.) of the complex baseband filter 432 may be adjusted by control signals from the SOC processing resources.

The frequency shifted low Q baseband filter is converted to a desired RF frequency by a clock signal provided by clock generator 434 to produce a frequency shifted high Q RF filter. Fig. 36 illustrates the conversion of a frequency-shifted low-Q baseband filter to a frequency-shifted high-Q RF filter, and fig. 35 illustrates one embodiment of a clock generator 434.

As shown in fig. 35, clock generator 434 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each having a 25% duty cycle and being sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. The clock generator 434 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of FTBPF 430 may be used as the LO clock signal.

Returning to the discussion of fig. 34, FTBPF 430 receives clock signals that are coupled to transistors to in turn couple their respective complex baseband filters to the inbound RF signal. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of the complex baseband filter 432 is shifted to RF (and/or LO), thereby implementing a high Q RF bandpass filter.

Fig. 37 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes a differential FTBPF 440 (frequency conversion bandpass filter). This portion of the RX RF-IF section includes transformer T1, variable capacitance network C1, and LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA393 substantially unattenuated and undesired signal components (e.g., blockers, mirrors, etc.) are attenuated. To implement this filter, complex baseband filter 442 provides a low-Q baseband filter whose bandpass region may be offset by zero frequency. Note that the performance (e.g., bandwidth, decay rate, quality factor, frequency offset, etc.) of the complex baseband filter 442 may be adjusted by control signals from the SOC processing resources.

The frequency shifted low Q baseband filter is converted to a desired RF frequency by a clock signal provided by clock generator 444 to produce a frequency shifted high Q RF filter. Fig. 39 illustrates the conversion of a frequency-shifted low-Q baseband filter to a frequency-shifted high-Q RF filter, and fig. 38 illustrates one embodiment of a clock generator 444.

As shown in fig. 38, clock generator 444 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each having a 25% duty cycle and being sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. The clock generator 444 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of FTBPF 440 may be used as the LO clock signal.

Returning to the discussion of fig. 37, the FTBPF 440 receives clock signals that are coupled to the transistors to in turn couple their respective complex baseband filters to the inbound RF signal. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of the complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high-Q RF bandpass filter.

Fig. 40 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes an FTBPF 440 (frequency conversion bandpass filter). This portion of the RX RF-IF section includes transformer T1, variable capacitance network C1, and LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442. The complex baseband filter 442 includes a plurality of baseband impedances (e.g., Z)_BB(s)) 450-.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA393 substantially unattenuated and undesired signal components (e.g., blockers, mirrors, etc.) are attenuated. To implement this filter, complex baseband filter 442 provides a low-Q baseband filter whose bandpass region may be offset by a zero frequency based on the ratio between the gain stage and the baseband impedance. Note that each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note also that the impedance of each baseband impedance may be the same, different, or a combination thereof. It is further noted that the impedance of each baseband impedance and/or the gain of at least one gain stage may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

The frequency shifted low Q baseband filter is converted to a desired RF frequency by a clock signal provided by clock generator 444 to produce a frequency shifted high Q RF filter. Fig. 42 shows a frequency-shifted high Q RF filter, and fig. 41 shows one embodiment of a clock generator 444.

As shown in fig. 41, clock generator 444 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each having a 25% duty cycle and being sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. The clock generator 444 may also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of FTBPF 440 may be used as the LO clock signal.

Returning to the discussion of fig. 40, the FTBPF 440 receives clock signals that are coupled to the transistors to in turn couple their respective complex baseband filters 442 to the inbound RF signal. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of the complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high-Q RF bandpass filter.

Fig. 43 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes an FTBPF 440 (frequency conversion bandpass filter). This portion of the RX RF-IF section includes transformer T1, variable capacitance network C1, and LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442. Complex baseband filter 442 includes a plurality of capacitors, a positive gain stage (Gm)458 and a negative gain stage (-Gm) 460.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA393 substantially unattenuated and undesired signal components (e.g., blockers, mirrors, etc.) are attenuated. To implement this filter, complex baseband filter 442 provides a low-Q baseband filter whose bandpass region may be offset by a zero frequency based on the ratio between the gain stage and the capacitance. Note that the capacitance value of each capacitor may be the same, different, or a combination thereof. It is further noted that the capacitance of each capacitor and/or the gain of at least one gain stage may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

The frequency shifted low Q baseband filter is converted to a desired RF frequency by a clock signal provided by clock generator 444 to produce a frequency shifted high Q RF filter. A clock generator 444, as shown in fig. 44 (various embodiments of which will be described with reference to at least one of the following figures), produces 4 clock signals, each with a 25% duty cycle, and sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. The clock generator 444 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of FTBPF 440 may be used as the LO clock signal.

Returning to the discussion of fig. 43, the FTBPF 440 receives clock signals that are coupled to the transistors to in turn couple their respective complex baseband filters 442 to the inbound RF signal. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of the complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high-Q RF bandpass filter.

Fig. 45 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes an FTBPF 440 (frequency conversion bandpass filter). This portion of the RX RF-IF section includes transformer T1, variable capacitance network C1, control module 470, and LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442. The complex baseband filter 442 includes a plurality of baseband impedances (e.g., Z)_BB(s)) 450-.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA393 substantially unattenuated and undesired signal components (e.g., blockers, mirrors, etc.) are attenuated. To implement this filter, complex baseband filter 442 provides a low-Q baseband filter whose bandpass region may be offset by a zero frequency based on the ratio between the gain stage and the baseband impedance set by a control signal provided by control module 470.

Control module 470 is part of the SOC processing resources that determines a desired low Q band pass filter response (e.g., gain, bandwidth, quality factor, frequency offset, etc.) based on at least one of: a signal-to-noise ratio (SNR) of the inbound RF signal, a signal-to-interference ratio (SIR) of the inbound RF signal, a strength of the received signal, a bit error rate, and the like. Based on the desired response, the control module 470 determines the settings of the baseband impedance and/or gain module. Note that control module 470 may continuously update the desired response based on changes in the various factors it monitors, periodically update, and/or update when performance characteristic criteria are met (e.g., transmit power level changes, SNR is below a threshold, SIR is below a threshold, strength of received signal is below a threshold, etc.).

Once the frequency response of the low Q baseband filter is determined (or updated), the low Q baseband filter is frequency converted to the desired RF frequency by a clock signal provided by clock generator 476 to produce a frequency-shifted high Q RF filter. A clock generator 476 as shown in fig. 46 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each having a 25% duty cycle and being sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. Clock generator 476 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of FTBPF 440 may be used as the LO clock signal.

Returning to the discussion of fig. 45, the FTBPF 440 receives clock signals that are coupled to the transistors to in turn couple their respective complex baseband filters 442 to the inbound RF signal. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of the complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high-Q RF bandpass filter.

Fig. 47 is a schematic block diagram of a complex baseband (BB) filter 442 including a plurality of adjustable baseband impedances 480-. Each adjustable baseband impedance may include at least one of: optional capacitance network 492 (e.g., tunable capacitance), programmable switched capacitance network 494, programmable switched capacitance filter 496(1 st order to n th order), and any combination of components (e.g., inductance, capacitance, resistance) capable of providing a desired baseband frequency response.

The adjustable gain stages (+ Gm and-Gm) 488-490 may each include an amplifier with a gain network connected thereto. The gain network may include at least one of: resistance, capacitance, variable resistance, variable capacitance, and the like. In this regard, the gain of each gain stage may be adjusted to change the performance of the complex baseband filter 442. Specifically, the frequency offset of the low-Q band-pass filter can be changed by changing the gain by the impedance value of the adjustable impedance. Additionally or alternatively, the control signal provided by the control module 470 may change the bandwidth, gain, swing rate, quality factor, and/or other properties of the complex baseband filter 442.

Fig. 48 is a schematic diagram of the conversion of the frequency response of the complex BB filter 442 to the frequency response of the high Q RF filter for the RX RF-IF section according to one embodiment of the present invention, including the FTBPF 440 with the adjustable complex baseband filter 442 shown in fig. 47. In this illustration, the bandwidth, slew rate, gain, frequency offset, and/or other performance of the low-Q baseband filter provided by complex baseband filter 442 may be adjusted. The tunable and adjusted characteristics of the low Q band pass filter can be converted to RF (or LO). In this regard, by adjusting the performance of the low-Q baseband filters, the performance of the corresponding high-Q baseband filters may be similarly adjusted.

Fig. 49 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, including an FTBPF 412 (frequency conversion bandpass filter). This portion of the RX RF-IF section includes I504 and Q RF-IF mixers 500 and a mixing buffer 502. The FTBPF block includes the FTBPF and other buffers. The FTBPF includes a plurality of transistors and a plurality of baseband impedances (e.g., Z)_BB(s))414, 416, 418 and 420.

In a fortuneIn the line example, the I-mixer 504 couples the I-component of the inbound RF signal to a local oscillation (e.g., f)_LO2＝f_RF-f_IF500) Is mixed to produce an I mixed signal. The I mixing buffer buffers the I mixed signal and provides the buffered I mixed signal to the FTBPF block 412. Similarly, the Q mixer couples the Q component of the inbound RF signal to a local oscillation (e.g., f)_LO2＝f_RF-f_IF) To produce a Q-mixed signal. The Q mixing buffer buffers the Q mixed signal and provides the buffered Q mixed signal to the FTBPF block 412.

The FTBPF 412 provides a high Q (quality factor) IF filter that filters the inbound IF signal (e.g., the I and Q mixed signal) such that desired signal components of the inbound IF signal pass substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated. To implement the filter, the baseband impedance (Z)_BBz(s))414, 416, 418, and 420 collectively provide a low Q baseband filter having a baseband filter response, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistance, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

The frequency shifted low Q baseband filter is converted to a desired IF frequency by a clock signal provided by clock generator 510 to produce a frequency shifted high Q IF filter. Fig. 51 illustrates the conversion of a frequency-shifted low-Q baseband filter to a frequency-shifted high-Q IF filter, and fig. 50 illustrates one embodiment of a clock generator 510.

As shown in fig. 50, a clock generator 510 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each having a 25% duty cycle and being sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound IF signal and may be adjusted to better track the carrier frequency. Clock generator 510 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal (e.g., LO 2). Alternatively, at least one clock signal of FTBPF 412 may be used as the LO clock signal.

Returning to the discussion of fig. 49, FTBPF 412 receives clock signals that are coupled to transistors to in turn connect their respective baseband impedances to the inbound IF signal. Since the clock rate is at the IF (e.g., the carrier frequency of the desired component of the inbound IF signal), the baseband impedance response (low Q bandpass filter collectively) shifts to the IF (and/or LO2), thereby implementing a high Q IF bandpass filter.

Fig. 52 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes an IF FTBPF (frequency conversion bandpass filter) block 530. The portion of the RX RF-IF section includes I and Q RF-IF mixers and mixing buffers. The IF FTBPF 530 block includes a differential IF FTBPF 530 and other buffers. The differential IF FTBPF 530 includes a plurality of transistors and a plurality of baseband impedances (e.g., Z)_BB(s))。

In one example of operation, the I-mixer 522 couples the I-component of the inbound RF signal to a local oscillation (e.g., f)_LO2＝f_RF-f_IF520) Is mixed to produce an I mixed signal. I mixing buffer 522 buffers the I mixed signal and provides the buffered I mixed signal to FTBPF 530 module. Similarly, the Q mixer 523 couples the Q component of the inbound RF signal to a local oscillation (e.g., f)_LO2＝f_RF-f_IF521) To produce a Q-mixed signal. Q mixing buffer 523 buffers the Q mixed signal and provides the buffered Q mixed signal to FTBPF 530 module.

FTBPF 530 provides a high Q (quality factor) IF filter that filters the inbound IF signal (e.g., the I and Q mixed signal) such that desired signal components of the inbound IF signal pass substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated. To implement the filter, the baseband impedance (Z)_BBz(s))532、534、536、538、540. 542, 544 and 546 collectively provide a low-Q baseband filter, wherein each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

The frequency-shifted low-Q baseband filter is converted to a desired IF frequency by a clock signal provided by a clock generator to produce a frequency-shifted high-Q IF filter. A clock generator 550, as shown in fig. 53 (various embodiments of which will be described with reference to at least one of the following figures), produces 8 clock signals, each having a 12.5% duty cycle and being sequentially phase-shifted by 45 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound IF signal and may be adjusted to better track the carrier frequency. Clock generator 550 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal (e.g., LO 2). Alternatively, at least one clock signal of the FTBPF may be used as the LO clock signal.

Returning to the discussion of fig. 52, FTBPF 530 receives clock signals that are coupled to transistors to in turn couple their respective baseband impedances to the inbound IF signal. Since the clock rate is at the IF (e.g., the carrier frequency of the desired component of the inbound IF signal), the baseband impedance response (low Q bandpass filter collectively) shifts to the IF (and/or LO2), thereby implementing a high Q IF bandpass filter.

Fig. 54 is a schematic block diagram of a portion of an RF-IF receiver section according to one embodiment of the invention, which includes a single-ended FTBPF 560 (frequency translating bandpass filter), and the single-ended FTBPF 560 includes a negative resistance. The portion of the RXRF-IF section includes a transformer, a variable capacitance network, and an LNA. FTBPF 560 includes a plurality of transistors and a plurality of baseband impedances (Z)_BB(s))562, 564, 566, and 568.

In one example of operation, a Front End Module (FEM)390 receives an inbound RF signal via an antenna, processes the RF signal in a manner described above and/or with reference to at least one of the following figures, and provides the inbound RF signal processed by the FEM 390 to a transformer. The transformer steps up or down the voltage level of the inbound RF signal, which is then filtered by the variable capacitance network. Note that the transformer may be omitted if no adjustment to the voltage level of the inbound RF signal is required and/or no separation provided by the transformer is required.

The FTBPF 560 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that desired signal components of the inbound RF signal are passed to the LNA392 substantially unattenuated and undesired signal components (e.g., blockers, mirrors, etc.) are attenuated. To implement the filter, the baseband impedance (Z)_BB(s))562, 564, 566, and 568 collectively provide a low-Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

In addition, FTBPF 560 includes a negative resistance (e.g., -2R) to compensate for inductive losses, to compensate for switching losses, and/or to improve the selectivity and/or quality factor of the low Q bandpass filter. The negative resistance may be implemented as shown in fig. 56, i.e. comprising a plurality of transistors.

The low-Q baseband filter is converted to a desired RF frequency by a clock signal provided by a clock generator to produce a high-Q RF filter. A clock generator as shown in fig. 55 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals, each with a 25% duty cycle and sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. Clock generator 572 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal.

Returning to the discussion of fig. 54, FTBPF 560 receives clock signals that are coupled to transistors to in turn couple their respective baseband impedances to the inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (low Q bandpass filter in common) is transferred to RF, thereby implementing a high Q RF bandpass filter.

Fig. 57 is a schematic block diagram of a portion of an RF-IF receiver section according to one embodiment of the present invention, which includes a differential FTBPF 580 (frequency translating bandpass filter), and the differential FTBPF 580 includes a negative resistance. The portion of the RXRF-IF section includes a transformer, a variable capacitance network, and an LNA 393. The differential FTBPF 580 includes a plurality of transistors and a plurality of baseband impedances (Z)_BB(s))。

FTBPF 580 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that desired signal components of the inbound RF signal are passed to LNA393 substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated. To implement the filter, the baseband impedance (Z)_BB(s)) collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Also note that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resource to adjust the performance of the low-Q baseband filter(e.g., bandwidth, decay rate, quality factor, etc.).

In addition, FTBPF 580 includes a negative resistance (e.g., -2R) to compensate for inductive losses, to compensate for switching losses, and/or to improve the selectivity and/or quality factor of the low Q bandpass filter. Negative resistance may be implemented as shown in fig. 56.

The low-Q baseband filter is frequency converted to a desired RF frequency by a clock signal provided by a clock generator 582 to produce a high-Q RF filter. A clock generator 582 (various embodiments of which will be described with reference to at least one of the following figures) as shown in fig. 58 produces 4 clock signals, each with a 25% duty cycle and sequentially phase-shifted by 90 °. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and may be adjusted to better track the carrier frequency. The clock generator 582 may also generate a local oscillator clock signal (not shown) that is used to downconvert the inbound RF signal to an inbound IF signal.

Returning to the discussion of fig. 57, FTBPF 580 receives clock signals that are coupled to transistors to in turn couple their respective baseband impedances to the inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (low Q bandpass filter in common) is transferred to RF, thereby implementing a high Q RF bandpass filter.

Fig. 59 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes a dual-band FTBPF (frequency conversion bandpass filter) 590. This portion of the RX RF-IF section includes a transformer, a variable capacitance network, and LNAs 392-1 and 392-2. The FTBPF 590 comprises a plurality of transistors and a plurality of baseband impedances (Z)_BB(s))592, 594, 596, and 598.

In one example of operation, a Front End Module (FEM)390 receives a dual-band inbound RF signal (e.g., f) via an antenna_RF1And f_RF2) The RF signal is processed in a manner as described above and/or as will be described with reference to at least one of the following figures, and the FEM processed inbound RF signal is provided to a transformer. Transformer up or down inbound RF signalsThe voltage level of the sign, which is then filtered by the variable capacitance network C1. Note that the transformer may be omitted if no adjustment to the voltage level of the inbound RF signal is required and/or no separation provided by the transformer is required.

FTBPF 590 provides two high Q (quality factor) RF filters (one with f)_RF1As the center frequency, the other being f_RF2Center frequency) that filters the inbound RF signal such that desired signal components of the dual-band inbound RF signal are passed to LNAs 392-1 and 392-2 substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated. The two high Q RF filters are composed of multiple baseband impedances (Z)_BB(s)592, 594, 596, and 598) and a plurality of transistors, wherein each baseband impedance comprises another plurality of baseband impedances (e.g., Z)_BB'(s) 592, 594, 596, and 598) and a plurality of additional transistors. A plurality of further base band impedances (Z)_BB'(s) 592, 594, 596, and 598) provide a low-Q baseband filter, wherein each of the additional plurality of baseband impedances may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

The clock signal (frequency f) provided by the clock generator 600_D) Frequency converting a low Q baseband filter to a desired RF frequency (e.g., f)_D＝(f_LO1-f_LO2) /2) to produce a high Q RF filter. Clock generator 600 as shown in FIG. 60 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals (e.g., LO'₁To LO'₄) Each clock signal has a 25% duty cycle and is in turn phase shifted by 90 °. The frequency of the clock signal corresponds to a carrier frequency (e.g., f) of a first frequency band of the inbound RF signal_RF1Or f_LO1) Subtracting the carrier frequency (e.g., f) of the second frequency band of the inbound RF signal_RF2Or f_LO2) Difference of (2)1/2 and may be adjusted to better track at least one carrier frequency.

Since the first plurality of transistors has a rate f_CLO(s) of₁-LO₄(produced by clock generator 600 as shown in fig. 60) the high-Q RF filter formed by the first plurality of baseband impedances is frequency-converted to a higher desired RF frequency, where f_C＝(f_LO1+f_LO2)/2. For example, referring to FIG. 61, a low Q baseband filter formed from another plurality of baseband impedances is frequency converted to +/-f_D. Thus, the response of the first high Q band pass filter is at +/-f_DThird order harmonics are also shown for the center frequency. Referring to fig. 62, the first high-Q band-pass filter is frequency-converted to f_C-f_DAnd f_C+f_DTo produce two high Q bandpass filters. Because f is_C＝(f_LO1+f_LO2)/2，f_D＝(f_LO1-f_LO2) /2, so f_C-f_D＝LO2，f_C+f_DLO 1. Thus, one of the high Q bandpass filters is provided with LO2 (or f)_RF2) Centered, another high Q bandpass filter is LO1 (or f)_RF1) As the center. Thus, the frequency at which the first high Q bandpass filter passes the inbound RF signal is LO2 (or f)_RF2) The frequency of the second high-Q bandpass filter passing the inbound RF signal is LO1 (or f)_RF1) Of the desired signal component.

Fig. 63 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes a dual-band differential FTBPF (frequency conversion bandpass filter) 610. The portion of the RX RF-IF section includes a transformer, a variable capacitance network, and LNAs 393-1 and 393-2. FTBPF 610 includes a plurality of transistors and a plurality of baseband impedances (Z)_BB(s))612, 614, 616, and 618.

In one example of operation, a Front End Module (FEM)390 receives a dual-band inbound RF signal (e.g., f) via an antenna_RF1And f_RF2) Processing the RF signal in a manner as described above and/or as will be described with reference to at least one of the following figures, and providing the FEM processed inbound RF signal to a receiverTransformer T1. The transformer converts the inbound RF signal to a differential inbound RF signal.

FTBPF 610 provides two high Q (quality factor) RF filters (one with f)_RF1As the center frequency, the other being f_RF2Center frequency) that filters the inbound RF signal such that desired signal components of the dual-band inbound RF signal are passed to LNAs 393-1 and 393-2 substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated. The two high Q RF filters are composed of multiple baseband impedances (Z)_BB(s)612, 614, 616, and 618) and a plurality of transistors, wherein each baseband impedance comprises another plurality of baseband impedances (e.g., Z_BB'(s) 612, 614, 616, and 618) and a further plurality of transistors. A plurality of further base band impedances (Z)_BB'(s) 612, 614, 616, and 618) provide a low-Q baseband filter, wherein each of the further plurality of baseband impedances may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

The clock signal (frequency f) provided by the clock generator 600_D) Frequency converting a low Q baseband filter to a desired RF frequency (e.g., f)_D＝(f_LO1-f_LO2) /2) to produce a high Q RF filter. Clock generator 600 as shown in FIG. 60 (various embodiments of which will be described with reference to at least one of the following figures) produces 4 clock signals (e.g., LO'₁To LO'₄) Each clock signal has a 25% duty cycle and is in turn phase shifted by 90 °. The frequency of the clock signal corresponds to a carrier frequency (e.g., f) of a first frequency band of the inbound RF signal_RF1Or f_LO1) Subtracting the carrier frequency (e.g., f) of the second frequency band of the inbound RF signal_RF2Or f_LO2) 1/2 and may be adjusted to better track at least one carrier frequency.

Since the first plurality of transistors has a rate f_CLO(s) of₁-LO₄(produced by a clock generator as shown in fig. 60) and the high-Q RF filter formed by the first plurality of baseband impedances is frequency-converted to a higher desired RF frequency, where f_C＝(fLO₁+fLO₂)/2. Thus, one of the high Q bandpass filters is provided with LO2 (or f)_RF2) Centered, another high Q bandpass filter is LO1 (or f)_RF1) As the center. Thus, the frequency at which the first high Q bandpass filter passes the inbound RF signal is LO2 (or f)_RF2) The frequency of the second high-Q bandpass filter passing the inbound RF signal is LO1 (or f)_RF1) Of the desired signal component.

Fig. 64 is a schematic block diagram of a portion of an RF-IF receiver section according to another embodiment of the present invention, which includes a transformer, a variable capacitance network, a pair of inverter-based LNAs 395, a mixer, and an output buffer (or unity gain driver). The mixer includes a plurality of transistors, a pair of transimpedance amplifiers (TIAs) 622 and 624, and accompanying impedances (Z)626 and 628.

In one example of operation, LNA395 provides differential current (i) to the mixer_RFAnd-i_RF). In the current domain, the mixer couples a differential current to a differential I630 component (LO) of the local oscillation_IPAnd LO_IN) Mixing to produce an I-mixed current signal. The mixer also couples the differential current to a differential Q632 component (LO) of the local oscillation_QPAnd LO_QN) Mixing to produce a Q-mixed current signal.

The first TIAs 622 and 624 amplify the mixed I current signal through associated impedances (Z)626 and 628 and generate a voltage domain mixed I signal. Likewise, the second TIA amplifies the Q-mixed current signal through associated impedances (Z)626 and 628 and generates a voltage domain Q-mixed signal.

Fig. 65 is a schematic block diagram of a clock generator 634 for an RF-IF receiver section according to another embodiment of the present invention. The clock generator (various embodiments of which will be described with reference to at least one of the figures below) produces 4 clock signalsClock signals (e.g. LO)_IP、LO_IN、LO_QPAnd LO_QN) Each clock signal has a 25% duty cycle and is in turn phase shifted by 90 °.

Figure 66 is a schematic block diagram of a transimpedance amplifier (TIA) and respective impedances (Z)640 and 642 according to one embodiment of the invention. The TIA includes a current source, a frequency dependent (frequency dependent) amplifier (-A (s)), an IF transistor (T)_IF) And a low frequency transistor (T)_LF). The respective impedance in each output pin of the TIA includes a resistor, a capacitor, and a transistor.

In one example of operation, differential input currents are received at in-and in +. Current node analysis of the negative input node (e.g., KCL-Kirchoff's current law) shows that the current source current (ib) is equal to the input current (iI)_N) + current through capacitance (iC) + through T_IFCurrent (i) of_OUT) + through T_LFThe current of (2). KVL (kirchhoff's voltage law) with positive input (out +) indicates that the output voltage (Vout +) is equal to Vdd-Z I_OUT(i.e., through T)_IFCurrent of (d).

At high frequencies (e.g., r above the inbound RF signal)_RF) The impedance of the capacitor becomes dominant and the input is substantially reduced; thus, the current (i) is output_OUT) Substantially free of high frequency components. At low frequencies (e.g., r lower than the inbound RF signal)_RF) For T_IFConfiguring the amplifier and the low-frequency transistor for a low-frequency current T_IFEssentially an open circuit. This can be achieved by changing the size of the transistor and biasing the amplifier so that T_LFImpedance at low frequencies is much less than Z + T_IF。

For frequencies within a desired frequency range (e.g. f)_RF) Comparison of T_IFAnd the corresponding impedances Z640, 642, the capacitances and T_LFHas a high impedance. Thus, iO_UT＝i_b-i_INAnd v is_OUT＝Z*i_OUT. Accordingly, the TIA and the respective impedances Z640, 642 may be tuned to provide a high Q RF bandpass filter. Note that at least one component of the TIA may pass through SThe control signal provided by the OC processing resource adjusts the performance of the high-Q band-pass filter.

FIG. 67 is a schematic block diagram of a Low Noise Amplifier (LNA)670 including FTBPFs 650, 672, 674 and 678 according to one embodiment of the invention. LNA 670 includes a current source, a pair of input transistors (T3 and T4), a pair of bias transistors (T1 and T2), and an output impedance (resistors are shown, but may also be inductors, transistors, capacitors, and/or combinations thereof.

FIG. 68 is a schematic block diagram of a differential 4-phase FTBPF (frequency conversion bandpass filter) 680 including a plurality of transistors and 4 baseband impedances (e.g., Z) according to one embodiment of the invention_BB(s))682, 684, 686 and 688. Base band impedance (Z)_BB(s))682, 684, 686 and 688 collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistance and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

Clock signals (e.g. LO) provided by a clock generator₁-LO₄) The low Q baseband filter is converted to the desired RF frequency to produce a high Q RF or IF filter. The differential high-Q RF filter filters the differential RF or IF signal such that desired signal components of the RF or IF signal pass substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated.

FIG. 69 is a schematic diagram of the frequency response of a 4-phase FTBPF 680 showing a signal feed-through harmonic and a superimposed signal harmonic in accordance with one embodiment of the present invention. Signal feed-through harmonics 692 are at +/-3, +/-5, +/-7 and +/-9, and superimposed signal harmonics 690 are at-3, -5, -7 and-9.

FIG. 70 is a schematic block diagram of a 3-phase FTBPF (frequency conversion bandpass filter) 700 including a plurality of transistors and 3 baseband impedances (e.g., Z) according to another embodiment of the present invention_BB(s))702, 704, and 706. Base band impedance (Z)_BB(s))702, 704, and 706 collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

By a clock signal (e.g. LO) provided by a clock generator as shown in FIG. 71₁-LO_^) The low Q baseband filter is converted to the desired RF frequency to produce a high Q RF or IF filter. The differential high-Q RF filter filters the differential RF or IF signal such that desired signal components of the RF or IF signal pass substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated.

Fig. 72 is a schematic diagram of the frequency response of a 3-phase FTBPF 700 showing signal feed-through harmonics and superimposed signal harmonics, in accordance with one embodiment of the present invention. Signal feed-through harmonics 708 are at +/-5 and +/-7 and superimposed signal harmonics 710 are at 5 and 7.

Fig. 73 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) 712 according to another embodiment of the present invention, which includes a plurality of transistors and 4 capacitors. These capacitors collectively provide a low Q baseband filter. Note that the capacitance value of each capacitor may be the same, different, or a combination thereof. Note also that the capacitance of each capacitor may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

Clock signals (e.g. LO) provided by a clock generator₁-LO₄) Low Q basebandThe filter is frequency converted to the desired RF frequency to produce a high Q RF or IF filter. The differential high-Q RF filter filters the differential RF or IF signal such that desired signal components of the RF or IF signal pass substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated.

FIG. 74 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) 714 including a plurality of transistors and 2 baseband impedances (e.g., Z) connected to the transistors as shown, according to another embodiment of the present invention_BB(s)). Base band impedance (Z)_BB(s)) collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

FIG. 75 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) 716 including multiple transistors and 4 baseband impedances (e.g., Z) according to another embodiment of the present invention_BB(s)). Base band impedance (Z)_BB(s)) collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

FIG. 76 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) 720 including a plurality of transistors and 1 complex baseband impedance (e.g., Z) according to another embodiment of the invention_BB，C(ω)) 722. The complex baseband impedance provides a low Q baseband filter that is offset wOC from 0. Note that the complex baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation ratio, quality factor, frequency offset, etc.) of the low-Q baseband filter.

Fig. 77 is a schematic block diagram of complex baseband impedance for an FTBPF (frequency translating bandpass filter) according to one embodiment of the invention. The complex baseband impedance 726 includes a first baseband impedance (e.g., Z)_BBOmega), negative gain stages (e.g., -jGm omega V_IMω), second baseband impedance (e.g., Z)_BB(ω)) and a positive gain stage (e.g., jGm (ω) V_RE(ω)). Thus, the complex-basis band impedance includes a real component (RE) and an imaginary component (IM). The complex-based band rejection provides a low Q bandpass filter with a frequency response as shown, where the real component is represented by a curve w > 0 and the imaginary component is represented by a curve w < 0.

FIG. 78 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) including complex baseband impedances that pass electrical baseband impedance according to one embodiment of the inventionAnd (4) realizing. The complex baseband impedance provides a low Q baseband filter 730 that is offset wOC from 0 by an amount that depends on the gain (Gm) and the capacitive impedance (C)_BB) The ratio of (a) to (b). Note that the complex baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation ratio, quality factor, frequency offset, etc.) of the low-Q baseband filter. For example, the capacitance and/or gain module may be adjusted.

Clock signals (e.g. LO) provided by a clock generator₁-LO₄) The frequency shifted low-Q baseband filter is converted to the desired RF frequency to produce a high-Q RF or IF filter. The differential high-Q RF filter filters the differential RF or IF signal such that desired signal components of the RF or IF signal pass substantially unattenuated and undesired signal components (e.g., blockers, images, etc.) are attenuated.

Fig. 79 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 732, which includes a plurality of transistors and m capacitors, where m > 2, according to one embodiment of the present invention. These capacitors collectively provide a low Q baseband filter. Note that the capacitance value of each capacitor may be the same, different, or a combination thereof. Note also that the capacitance of each capacitor may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, decay rate, quality factor, etc.) of the low-Q baseband filter.

FIG. 80 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 734 including multiple transistors and m baseband impedances (e.g., Z) according to one embodiment of the invention_BB(s)), wherein m is an integer multiple of 4 and is greater than 4. Base band impedance (Z)_BB(s)) together provide a low Q baseband filter, each of whichThe baseband impedances may be capacitors, switched capacitor filters, switched capacitor resistors and/or complex impedances, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

Clock signals (e.g. LO) provided by a clock generator₁-LO_M) The low Q baseband filter is converted to the desired RF frequency to produce a high Q RF or IF filter. The differential high-Q RF filter filters the differential I and Q signal components of the IF signal such that the desired signal component of the IF signal passes substantially unattenuated and the undesired signal component (e.g., blocker, image, etc.) is attenuated.

FIG. 81 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 736 including a plurality of transistors and m/2 baseband impedances (e.g., Z/2) according to one embodiment of the present invention_BB(s)), wherein m is 4 or more. Base band impedance (Z)_BB(s)) collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

FIG. 82 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 738 that includes multiple crystals according to one embodiment of the inventionTransistor and m base band impedances (e.g. Z)_BB(s)), wherein m is 2 or more. Base band impedance (Z)_BB(s)) collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

FIG. 83 is a schematic block diagram of a single-ended m-phase FTBPF (frequency conversion bandpass filter) 740 including multiple transistors and m baseband impedances (e.g., Z) according to one embodiment of the invention_BB(s)), wherein m is 2 or more. Base band impedance (Z)_BB(s)) collectively provide a low Q baseband filter, where each baseband impedance may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance may be the same, different, or a combination thereof. Note also that the impedance of each baseband impedance may be adjusted by control signals from the SOC processing resources to adjust the performance (e.g., bandwidth, attenuation rate, quality factor, etc.) of the low-Q baseband filter.

FIG. 84 is a schematic diagram of the frequency response of an m-phase FTBPF 740 showing a low Q bandpass filter being frequency converted to a higher frequency (e.g., f) in accordance with one embodiment of the invention_LO)。f_LOCorresponding to RF frequencies, IF frequencies, local oscillations, or a combination thereof.

Fig. 85 is a schematic block diagram of a clock generator 750 for an m-phase FTBPF, according to one embodiment of the invention. The clock generator includes a plurality of flip-flops (DFFs) 752, 754, and 756 and a plurality of pulse winders (pulse winders) 758, 760, and 762. Flip-flops 752, 754, and 756 and at rate m f_RFIs synchronized with the clock gate signal (clkb). The resulting clock pulses from each flip-flop 752, 754, and 756 are pulse narrowed by a corresponding pulse narrowing device.

The pulse narrowers 758, 760 and 762 include two pairs of transistors connected as shown. The transistor below the left is smaller than the other transistors, making the rising edge time slower than the falling edge time, thereby narrowing the pulse.

Fig. 86 is a schematic block diagram of a clock generator 770 for an m-phase FTBPF according to another embodiment of the present invention. The clock generator includes a plurality of flip-flops (DFFs) 772, 774, and 776 and a plurality of and gates. Flip-flops 772, 774 and 776 and the rate is (1/2) × m × f_RFIs synchronized with the clock gate signal (clkb). The and gate receives a non-inverted output from the first flip-flop 772 and an inverted output from the next flip-flop 774 to ensure that consecutive clock pulses do not overlap.

Fig. 87 is a schematic block diagram of a clock generator 790 for an m-phase FTBPF according to another embodiment of the invention. The clock generator includes a ring oscillator 792 and a plurality of logic circuits. Each logic circuit includes an and gate and an inverter or buffer. The grid value of the ring oscillator 792 is the clock rate m f_RF(m is an odd number, which is equal to or greater than 3). Each logic circuit receives successive pulses from the ring oscillator 792 such that successive clock pulses do not overlap.

FIG. 88 is an illustration of a clock generator 800 for a 3-phase FTBPF according to one embodiment of the inventionA block diagram of the clock generator includes a ring oscillator 792 and a plurality of logic circuits. Each logic circuit includes a combination of and gates and buffers and/or inverters. For example, each logic circuit includes an and gate, an inverter, and a buffer. The gate value (gated) of ring oscillator 792 is clock rate 3 f_RF. Through the logic circuits, the AND gates are biased to generate 1/3 duty cycle non-overlapping clocks (e.g., clk 1802, clk 2806, and clk 3804).

Fig. 89 is a schematic block diagram of a clock generator 810 for a 3-phase FTBPF that includes two ring oscillators 792 and a plurality of logic gates, according to another embodiment of the invention. Each logic circuit includes a combination of and gates and buffers and/or inverters. For example, each logic circuit includes an and gate, an inverter, and a buffer. The first ring oscillator 792 has a gate value of clock rate 3 x f_RFSecond ring oscillator 792 has a grid value of 3 x f_RFInverse (inversion) (e.g. -3 f)_RF). In this configuration, clock signals 1-3812, 814 and 816 are shown in FIG. 88, and clock signals 4-6818, 820 and 822 are the inverse of clock signals 1-3, respectively.

FIG. 90 is a schematic block diagram of a portion of a Front End Module (FEM)810 and a portion of an SOC812, according to one embodiment of the invention. The portion of FEM 810 includes a power amplifier module (PA)814, a duplexer, a balancing network 818, and a common mode sensing circuit. The duplexer includes a transformer (or other structure, such as a frequency selective duplexer and/or an electronically balanced duplexer), and the balancing network 818 includes at least one variable resistance and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of SOC812 includes a peak detector 820, a tuning engine 822, and a low noise amplifier module (LNA). Alternatively, the peak detector 820 and/or the tuning engine 822 may be located in the FEM 810.

In one example of operation, PA 814 provides an outbound RF signal to a center tap of the transformer's primary dual coil. The current of the outbound RF signal is split between the two coils according to the impedance difference between the antenna and the balancing network 818. If the impedance of the balancing network 818 substantially matches the antenna impedance, the current is substantially equally split to the two coils.

With the coil configuration as shown, if the currents of the primary coils are substantially equal, they substantially cancel each other out in the magnetic field of the secondary coil. Thus, the secondary outbound RF signal is substantially attenuated. For inbound RF signals, the primary two coils generate magnetic fields in accordance with the current of the inbound RF signal. At this time, the magnetic field is increased, and thus twice as much current is generated in the secondary as in the primary (assuming that each coil has the same number of turns). Thus, the transformer amplifies the inbound RF signal.

If the antenna impedance does not match the impedance of the balancing network 818, an outbound RF signal current component (e.g., TX leakage) will be present in the secondary. For example, assume that the current flowing from the coil to the inductor is i_P1The current flowing from the coil to the balance network 818 is i_P2Then the TX leakage can be expressed as i_P1-i_P2. The resistance of the common mode sense current senses the amount of TX leakage. For example, the voltage at the center node of the resistor is equal to VS- (R)₁*2i_R+R₁*i_P2-R₂*i_P1) Where VS is the secondary voltage, 2i_RIs the current of the received inbound RF signal. Let R be₁＝R₂And i is_P1＝i_P2Then the voltage at the center node is equal to 1/2 for VS. However, if i_P1Is not equal to i_P2The voltage at the center node of the resistor will deviate 1/2VS by an amount proportional to the difference.

The detector 820 detects the difference in the voltage of the center node of the resistor from 1/2VS and provides an expression for the difference to the tuning engine 822. The tuning engine 822 interprets the difference and generates a control signal to adjust the impedance of the balancing network. For example, if i_P1＞i_P2Then the voltage of the common mode sensing circuit (e.g., the center node of the resistor) will be greater than 1/2VS, indicating that the impedance of the balancing network 818 is too large. Accordingly, the tuning engine 822 generates a control signal to reduce the impedance of the balancing network 818. As another example, if i_P1＜i_P2Then the voltage of the common mode sensing circuit will be less than1/2VS, which means that the impedance of the balancing network is too small. Accordingly, the tuning engine 822 generates a control signal to increase the impedance of the balancing network 818.

The tuning engine 822 may resolve the common mode voltage deviation, determine a desired impedance of the balancing network 818, and generate a control signal accordingly. Alternatively, the tuning engine 822 may iteratively generate control signals to gradually adjust the impedance of the balancing network 818 until a desired impedance is obtained. Using either approach, the tuning engine 822 functions to keep the impedance of the balancing network 818 substantially matched to the impedance of the antenna (over time, usage, and/or environmental conditions) to minimize the amount of TX leakage.

FIG. 91 is a schematic block diagram of a portion of a Front End Module (FEM)830 and a portion of an SOC832 according to another embodiment of the invention. The portion of the FEM 830 includes a power amplifier module (PA)836, a duplexer 838, a balancing network 842, an Antenna Tuning Unit (ATU)840, and a common mode sensing circuit. The duplexer 838 includes a transformer (or other structure, such as a frequency selective duplexer 838 and/or an electronically balanced duplexer 838), and the balancing network includes at least one variable resistance and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of SOC832 includes a peak detector 848, a tuning engine 850, a look-up table (LUT)844, a processing module 846, and a low noise amplifier module (LNA) 852. Alternatively, the peak detector 848 and/or the tuning engine 850 may be located in the FEM 830.

The FEM 830 includes an ATU 840 in addition to the function provided by the common mode sensing circuit (i.e., resistance), the detector 848, the tuning engine 850, and the balancing network 842 (as described with reference to fig. 90) to balance the impedance of the balancing network 842 with the antenna impedance. ATU 840 includes one or more fixed passive components and/or one or more variable passive components. For example, ATU 840 may include a variable capacitance-inductance circuit, a variable capacitance, a variable inductance, and/or the like.

In one example of operation, the PA 836 provides the amplified outbound RF signal to a duplexer 838, which includes a transformer that functions as described with reference to fig. 90. The duplexer 838 outputs the amplified outbound RF signal to the ATU 840, tuning the ATU 840 through settings stored in the LUT 844 to provide the desired antenna matching circuitry (e.g., impedance matching, quality factor, bandwidth, etc.). The ATU 840 outputs the outbound RF signal to an antenna for transmission.

For inbound RF signals, the antenna receives the signal and provides it to ATU 840, which in turn provides it to duplexer 838. The duplexer 838 outputs the inbound RF signal to the LNA 852 and the common mode sensing circuitry. The functions of the common mode sensing circuit, detector 848, tuning engine 850, and balancing network 842 are as described above with reference to fig. 90.

Processing module 846 is used to monitor various parameters of FEM 830. For example, the processing module 846 may monitor antenna impedance, transmit power, performance of the PA 836 (e.g., gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, setup time, overshoot, stability factor, etc.), received signal strength, SNR, SIR, adjustments made by the tuning engine 850, and so forth. Processing module 846 parses these parameters to determine whether the performance of FEM 830 can be further optimized. For example, processing module 846 may determine that adjusting ATU 840 may improve performance of PA 836. At this point, processing module 846 addresses LUT 844 to provide the desired settings for ATU 840. If such a change in ATU 840 affects the impedance balance between ATU 840 and balancing network 842, tuning engine 850 will make the appropriate adjustments.

In another embodiment, processing module 846 provides the functionality of tuning engine 850 and adjusts the balance of ATU 840 and balancing network 842 to achieve the desired performance of FEM 830. In yet another embodiment, balancing network 842 is fixed, and ATU 840 provides the desired adjustments in FEM 830 to achieve impedance balancing and to achieve the desired performance of FEM 830.

FIG. 92 is a schematic block diagram of a portion of a Front End Module (FEM)860 and a portion of an SOC 862 for 2G and 3G cellular operation, according to another embodiment of the invention. The portion of the FEM 860 includes a power amplifier module (PA)866, a duplexer, a balancing network, and common mode sensing circuitry. The duplexer comprises a transformer (or other structure, such as a frequency selective duplexer and/or an electronically balanced duplexer), and the balancing network comprises a switch, at least one variable resistance, and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 862 includes peak detector 872, tuning engine 874, switches, and low noise amplifier module (LNA) 876. Alternatively, the peak detector 872 and/or tuning engine 874 may be located in the FEM 860.

In this embodiment, the duplexer is best suited for Frequency Division Duplexing (FDD) which is used in 3G cellular telephone applications and the balanced network switch and LNA 876 switch are open. In Time Division Duplexing (TDD) for 2G cellular applications, the balancing network is shorted by a switch. This essentially eliminates the 3-dB theoretical insertion loss limit and leaves only the implementation loss(s). Note that the LNA 876 switch is off for 2G transmit and the LNA 876 switch is on for 2G receive. Also note that for the 3G mode, FEM and SOC 862 function as described with reference to fig. 90 and/or 91.

FIG. 93 is a schematic block diagram of a portion of Front End Module (FEM)860 and a portion of SOC 862 shown in FIG. 92 in 2G TX mode, in accordance with one embodiment of the present invention. In this mode, the LNA 876 switch shorts the LNA 876 and the balance network switch shorts the balance network. Due to the short circuit across the secondary coil, the primary coil is also substantially short circuited. Thus, the PA 866 is efficiently connected directly to the antenna.

Fig. 94 is a schematic block diagram of a portion of Front End Module (FEM)860 and a portion of SOC 862 shown in fig. 92 in 2G RX mode in accordance with one embodiment of the present invention. In this mode, the LNA switch is open and the balance network switch is closed, thus shorting the balance network. In this configuration, the transformer functions like a balun transformer for the receiver section.

FIG. 95 is a schematic block diagram of a small signal balancing network 880 including a plurality of transistors, a plurality of resistors, and a plurality of capacitors in accordance with one embodiment of the present invention. The selection of the resistances comprised in the balancing network may be controlled by a multi-bit signal (e.g. 10 bits) and the selection of the capacitances comprised in the balancing network may be controlled by another multi-bit signal (e.g. 5 bits).

For example, if the resistive side of the balancing network includes 4 resistor-transistor circuits, the common node (common node) of one resistor-transistor circuit is connected to the gate of the next resistor-transistor circuit. In this example, each gate is also connected to receive a 4-bit control signal. For example, the gate of the leftmost resistor-transistor circuit receives the most significant bit, the next leftmost resistor-transistor circuit receives the second most significant bit, and so on. Additionally, the resistance of the leftmost resistor-transistor circuit is R4, the resistance of the next leftmost resistor-transistor circuit is R3, and so on. Thus, for example, when the 4-bit control signal is 0001, only the rightmost resistor-transistor circuit is on, and its resistor R1 provides the final resistance. When the 4-bit control signal is 0011, the two resistor-transistor circuits at the rightmost end are turned on, and the resulting resistance is R1// R2. When the 4-bit control signal is 0111, the three resistor-transistor circuits at the far right end are turned on, and the resulting resistors are R1// R2// R3. When the 4-bit control signal is 1111, all four resistor-transistor circuits are turned on, and the resulting resistors are R1// R2// R3// R4. The capacitive side of the balancing network functions similarly.

In another embodiment, each resistor-transistor circuit and each capacitor-transistor circuit may be independently controlled by a bit of a respective control signal. For the four resistor-transistor circuit configuration described in the above figures and modified herein, control signal 1000 generates resistor R4; control signal 0100 generates resistor R3; the control signal 1010 generates a resistance R4// R2; and so on.

Fig. 96 is a schematic block diagram of a large signal balance network 882 including an RLC (resistor-inductor-capacitor) network and a plurality of transistors according to one embodiment of the present invention. The transistors are gated on and off to provide different combinations of resistance, inductance, and/or capacitance of the RLC network to balance the network impedance as desired. At this point, the transistors have relatively small voltage swings, so lower voltage transistors may be used.

FIG. 97 is a schematic block diagram of a portion of a Front End Module (FEM)890 and a portion of SOC892, according to another embodiment of the invention. The portion of FEM 890 includes power amplifier module (PA)896, duplexer 898, balancing network 900, and common mode sensing circuitry. The diplexer 898 includes a transformer (or other structure, such as a frequency selective diplexer 898 and/or an electronic balancing diplexer 898), and the balancing network includes at least one variable resistance and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of the SOC includes a peak detector 902, a tuning engine 904, a leakage detection 906 module, and a low noise amplifier module (LNA) 908. Alternatively, the peak detector 902, leak detection 906 module, and/or tuning engine 904 may be located in the FEM 890.

This embodiment functions similarly to the embodiment shown in FIG. 90, except for the leak detection 906 module. The leakage module is used to detect the change in the on-resistance of the transistors of the circuit in the balancing network 900 from the PA 896 output. For example, if the PA 896 output increases, it will cause the on-resistance of the transistors in the balancing network 900 to change. This change affects the overall impedance of the balancing network 900. Accordingly, the leak detection 906 module detects the on-resistance change and provides a representative signal to the tuning engine 904 and/or the processing module (as shown in fig. 91).

Based on the input of the leak detection 906 module, the tuning engine 904 adjusts the impedance of the balancing network 900. Alternatively or additionally, the processing module uses input from the leak detection 906 module to adjust the settings of the ATU. Regardless of the particular approach taken, variations in the on-resistance of the transistors in the balancing network 900 and/or the transistors in the power amplifier are compensated for.

FIG. 98 is a schematic block diagram of a portion of a front-end module (FEM)910 and a portion of an SOC912, according to another embodiment of the invention. The portion of the FEM 910 includes a power amplifier module (PA)916, a duplexer 918, a balancing network 920, and common mode sensing circuitry. The diplexer 918 includes a transformer (or other structure, such as a frequency selective diplexer 918 and/or an electronically balanced diplexer 918), and the balancing network includes at least one variable resistance and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of SOC912 includes a peak detector 922, a processing module 926 (containing the functionality of the tuning engine), and a low noise amplifier module (LNA) 924. Alternatively, the peak detector 922 and/or tuning engine may be located in the FEM 910.

The present embodiment functions similarly to the embodiment shown in fig. 90 with respect to the ability to adjust the TX attenuation and/or RX gain of duplexer 918. For example, when the transmit power is relatively low (e.g., the blocker of the inbound RF signal is small and/or the signal strength of the inbound RF signal is relatively high), the processing module 926 provides a signal to the duplexer 918 that causes the duplexer 918 to reduce TX attenuation, thereby reducing insertion loss.

For example, if the duplexer 918 includes a transformer as shown in fig. 90 and/or other type of frequency selective duplexer 918, portions of the filters may be shorted to increase losses at the expense of reducing separation. For another example, if the duplexer 918 comprises an electronically balanced duplexer, the separation may be balanced with the separation of the balancing network.

FIG. 99 is a schematic block diagram of a partial Front End Module (FEM)930 and a partial SOC932 in accordance with another embodiment of the invention. The portion of the FEM 930 includes a power amplifier module (PA)936, a duplexer 938, and a balancing network 940. The diplexer 938 includes a transformer (or other structure, such as a frequency selective diplexer 938 and/or an electronically balanced diplexer 938), a parasitic capacitance, and a compensation capacitance, and the balancing network includes at least one variable resistance and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of SOC932 includes a peak detector, a processing module (including the functionality of a tuning engine), and a low noise amplifier module (LNA) 940. Only LNA940 is shown.

In this embodiment, a compensation capacitance is added to compensate for the mismatch of parasitic capacitances (e.g., Cp1 and Cp2) due to the mismatch between primary windings (e.g., L1 and L2). Therefore, the compensation capacitors (Cc1 and Cc2) are selected such that Cp1+ Cc1 becomes Cp2+ Cc 2. With the addition of the compensation capacitor, the separation bandwidth of the duplexer 938 is greater than it would be without the compensation capacitor.

FIG. 100 is a schematic block diagram of a portion of a Front End Module (FEM)950 and a portion of an LNA952 according to another embodiment of the invention. The portion of FEM 950 includes a power amplifier module (PA)954, a duplexer 956, and a balancing network 958. The diplexer 956 includes a transformer (or other structure, such as a frequency selective diplexer and/or an electronically balanced diplexer 956) with parasitic capacitances (Cp3 and Cp 4). LNA952 includes an input transistor having a parasitic capacitance (Cp), a bias transistor, an inductor (L3), and a load impedance (Z). Due to the inclusion of L3 in LNA952, the common mode separation of duplexer 956 and LNA952 is improved over conventional LNA952 input configurations.

FIG. 101 is a schematic block diagram of an equivalent circuit of a portion of the Front End Module (FEM) and a portion of the LNA shown in FIG. 100, in accordance with one embodiment of the invention. The diagram shows how the common mode spacing is increased. The unbalanced currents connected to the secondary coil (L) through the parasitic capacitances (Cp3 and Cp4) of the transformer are connected to different resonant circuits formed by the inductance (L3) and the parasitic capacitances of the input transistors. The resonant circuit provides a high differential impedance and a low common mode impedance.

FIG. 102 is a schematic block diagram of a portion of a Front End Module (FEM)960 and a portion of a SOC 962, according to another embodiment of the invention. The portion of the FEM 960 includes a power amplifier module (PA), a duplexer, a balancing network 970, and a common mode sensing circuit. The duplexer comprises a transformer (or other structure, such as a frequency selective duplexer and/or an electronically balanced duplexer), and the balancing network comprises at least one variable resistance and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of SOC 962 includes a peak detector 974, a processing module 976 (including the functionality of a tuning engine), and a single-ended low noise amplifier module (LNA) 972. Alternatively, the peak detector 974 and/or the tuning engine may be located in the FEM 960.

In this embodiment, common mode spacing is substantially eliminated by using a single-ended LNA 972. The functions of the FEM 960 and other parts of the SOC 962 shown in the figure are as described above.

Fig. 103 is a schematic block diagram of a transformer of a duplexer in accordance with one embodiment of the present invention. The transformer comprises a primary coil (L1& L2) and a secondary coil (L2). The primary coils have the same number of turns, respectively; the secondary coil may have the same number of turns or a different number of turns than the primary coil. The winding direction of the coil is shown in the figure.

Fig. 104 is a schematic diagram of an implementation of a transformer implemented on 4 thick metal layers of an integrated circuit on an IC package substrate and/or printed circuit board, according to an embodiment of the invention. The primary coil is located on the upper two layers, and the secondary coil is located on the lower two layers. The first coil of the secondary on one layer may be connected in series or in parallel with other coils on other layers.

Fig. 105 is a schematic diagram of an implementation of a transformer on 3 thick metal layers of an IC on a printed circuit board and/or IC package substrate according to an embodiment of the invention. The primary coil is located on the top layer and uses the next layer for interconnection. At least one primary coil may be rotated by 90 °. The secondary coil is located on the underlying third layer.

FIG. 106 is a schematic block diagram of a partial Front End Module (FEM)990 and a partial SOC 992 according to another embodiment of the invention. The portion of the FEM 990 includes a power amplifier module (PA)994, a duplexer 996, a balancing network 1000, a tone injection module 998, and common mode sensing circuitry. The duplexer 996 includes a transformer (or other structure, such as a frequency selective duplexer 996 and/or an electronically balanced duplexer 996), and the balancing network includes at least one variable resistance and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of SOC 962 includes a peak detector 1002, a processing module 1004 (containing the functionality of a tuning engine), a baseband processing unit, and a low noise amplifier module (LNA) 1006. Alternatively, the peak detector 1002 and/or tuning engine may be located in the FEM 990.

In one example of operation, the functions of the common mode sensing circuit, tuning engine, detector 1002 and balancing network 1000 are as described above. In many cases, these components may reduce Transmitter (TX) and/or Receiver (RX) noise when the receiver band is below or equal to the noise floor of LNA 1006. When the TX and/or RX noise is at or below the noise floor, it is difficult to track, and thus difficult to track, the impedance of the antenna.

To enhance tracking of antenna impedance, the tone note module 998 injects a tone (tone) (e.g., Acos (ω) in the receiver band_{RX_RF}(t))). The duplexer 996 attenuates the RX tone differently than the TX signal because it is located in the RX band, and the duplexer 996 and balancing network 1000 are tunable for the TX band. Therefore, an easily detectable leakage signal is generated on the RX side of the duplexer 996 (e.g., on the secondary side of the transformer).

The RX tone based leakage signal propagates through the receiver section until it is converted to a baseband signal. At baseband, the tone amplitude is a measure of the RX band spacing. From the measurements of the RX band spacing, the impedance of the antenna can be determined. As the antenna impedance changes, the antenna tuning unit and/or the balancing network 1000 may be adjusted to track the impedance of the antenna. Note that the tone can be easily removed at baseband.

FIG. 107 is a schematic block diagram of a partial Front End Module (FEM)1010 and a partial SOC 1012 according to another embodiment of the invention. The portion of FEM 1010 includes a power amplifier module (PA)1014, a duplexer 1016, a balancing network 1018, and a common mode sensing circuit (not shown). The duplexer 1016 includes a transformer (or other structure, such as a frequency selective duplexer 1016 and/or an electronically balanced duplexer 1016). The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. The portion of SOC 1012 includes a peak detector 1002 (not shown), a processing module 1020 (which performs the function of a tuning engine), and a low noise amplifier module (LNA) 1022. Alternatively, the peak detector 1002 and/or the tuning engine may be located in the FEM 1010.

The balancing network 1018 includes an RLC network having a plurality of variable resistors, a plurality of variable capacitors, and at least one inductor. In this embodiment, the balancing network 1018 may be tuned to provide a widely variable impedance to better match the antenna impedance.

FIG. 108 is a schematic block diagram of the impedance of the resistor-transistor (R-T) circuit of the balancing network, according to one embodiment of the invention. The capacitance corresponds to the parasitic capacitance of the transistor. Since the R-T circuit includes a true passive resistance, it can contribute to a theoretical limit of 3dB on insertion loss.

FIG. 109 is a schematic block diagram of the impedance of the resistor-transistor (R-T) circuit of the balancing network according to another embodiment of the invention. In this embodiment, the R-T circuit includes an inductively weakened common source transistor. It is therefore an active resistor and does not contribute to the 3dB theoretical limit on insertion loss. Thus, the only loss of the balanced network is the implementation loss.

Fig. 110 is a schematic block diagram of a balancing network 1030, including an impedance up-converter 1032 and one or more baseband impedances (Zbb 1034), according to one embodiment of the invention. Impedance up-converter and desired frequency (e.g. f)_LOOr f_RF) And (6) synchronizing. The combination of impedance up-converter 1032 and baseband impedance may be implemented in a manner similar to the m-phase change band-pass filter described above.

Fig. 111 is a schematic block diagram of a balancing network according to another embodiment of the present invention, comprising two impedance up-converters 1042, 1044 and corresponding baseband impedances (Zbb 1046, 1048). Each impedance up-converter being coupled to a desired frequency (e.g. f)_{RF_TX}Or f_{RF_RX}) And (6) synchronizing. Each combination of impedance up-converters 1042, 1044 and one or more baseband impedances may be implemented in a manner similar to the m-phase change band-pass filters described above.

FIG. 112 is a schematic block diagram for balancing negative impedance 1050 in a network, in accordance with one embodiment of the present invention. The circuit includes a baseband negative impedance 1050 circuit, for example as shown in fig. 56, and the anti-upconverter 1052 may be implemented in a manner similar to the m-phase change band pass filter described above.

FIG. 113 is a schematic block diagram of a polarization receiver 1060 according to one embodiment of the invention, which includes a Phase Locked Loop (PLL)1068, analog-to-digital converters (ADCs 1064, 1066), a phase processing module 1062, a peak detector 1070, and an amplitude processing module 1062. The PLL 1068 includes a Phase and Frequency Detector (PFD), a charge pump, a loop filter, a Voltage Controlled Oscillator (VCO), a frequency divider (which may be a 1: 1 divider), a summing module, and a modulator (sigma-delta) module.

In one example of operation, an antenna receives an inbound RF signal (e.g., A (t) cos (w)_RF(t) + θ (t))) and provided to the PLL 1068 and peak detector 1070 of the receiver portion through an FEM (not shown). The peak detector 1070 (which may be an envelope detector) separates the amplitude terms (e.g., a (t)). The amplitude term is then converted to a digital signal by the ADC 1064, 1066. PLL 1068 processes cos (ω) of an inbound RF signal_RF(t) + θ (t)) to extract a phase signal (e.g., θ (t)). The processing module 1062 parses the amplitude signal and the phase signal to recover the transmitted data.

FIG. 114 is a schematic block diagram of a buffer circuit that may be used to connect a PLL 1082 of a local oscillator with a mixer of a down-conversion mixing module and/or an up-conversion mixing module, according to one embodiment of the present invention. The buffer circuit includes a differential buffer and weave connection 1086. The braided connection 1086 creates an increased inductance (relative to a parallel line) thereby attenuating the undesirable high frequency components to the mixer. Additionally, the size and nature of the braided connection 1086 may be selected to achieve a desired inter-wire capacitance, resulting in a tuned and distributed L-C circuit.

Fig. 115 is a schematic block diagram of an interleaved connection 1100 that includes a first wire on one layer of a substrate (e.g., die, package substrate, etc.) and another wire on another layer of the substrate, according to one embodiment of the invention. The lines are interleaved on both layers to improve the magnetic coupling between each other. Additionally, at least one line may include an inductive loop to increase its inductance.

Figure 116 is a schematic block diagram of a receiver including an input, a down-conversion mixing section, and a transimpedance amplifier (TIAs 1126, 1128) according to one embodiment of the present invention. The input section includes MN 1112, a gain module, an inductance, and a capacitance. The down-conversion mixing section includes a mixer and a local oscillator. TIAs 1126, 1128 each include a transistor and a resistor connected as shown. Note that the positive input may also be connected to a common node between the resistor and the transistor on the positive output, and the negative input may also be connected to a common node between the resistor and the transistor on the negative output.

As used herein, the term "substantially" or "about" provides an industry-accepted tolerance to the corresponding terms and/or relationships between components. Such an industry-accepted tolerance ranges from less than 1% to 50% and corresponds to, but is not limited to, component values, integrated circuit process fluctuations, temperature fluctuations, rise and fall times, and/or thermal noise. The relationship between components ranges from a small percentage difference to a large difference. As also used herein, the terms "operatively connected," "connected," and/or "coupled" include direct connection and/or indirect connection through intervening components (e.g., such components include, but are not limited to, components, assemblies, circuits, and/or modules), where for indirect connection, intervening components do not alter the information of a signal but may adjust its current level, voltage level, and/or power level. As used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two elements in the same manner as "operably coupled". As also used herein, the term "operably linked" indicates that the component includes one or more of the following: power connections, inputs, outputs, etc. for performing one or more corresponding functions when activated and may further include inferred connections to one or more other components. As used herein, the term "associated," as may be used herein, includes direct and/or indirect connection of an individual component and/or of a component embedded in another component. As also used herein, the term "compares favorably", as may be used herein, indicates that a comparison between two or more components, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater amplitude than signal 2, a favorable comparison result may be obtained when the amplitude of signal 1 is greater than the amplitude of signal 2 or the amplitude of signal 2 is less than the amplitude of signal 1.

Although the transistors shown in the above figures are Field Effect Transistors (FETs), those skilled in the art will appreciate that the transistors described above may use any type of transistor structure including, but not limited to, bipolar, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), N-well transistors, P-well transistors, enhancement, depletion, and zero Voltage Threshold (VT) transistors.

The invention has been described above with the aid of method steps illustrating specified functions and relationships. For convenience of description, the boundaries and sequence of these functional building blocks and method steps have been defined herein specifically. However, given the appropriate implementation of functions and relationships, changes in the limits and sequences are allowed. Any such boundaries or sequence of changes should be considered to be within the scope of the claims.

The invention has been described, at least in part, with reference to one or more embodiments. Embodiments of the invention as used herein are suitable for illustrating aspects, features, concepts and/or examples of the invention. Physical embodiments of the devices, methods of manufacture, machines and/or steps that constitute the present invention may include at least one of the aspects, features, concepts, examples, etc. described with reference to at least one embodiment described herein.

The invention has also been described above with the aid of functional blocks illustrating some important functions. For convenience of description, the boundaries of these functional building blocks have been defined specifically herein. When these important functions are implemented properly, varying their boundaries is permissible. Similarly, flow diagram blocks may be specifically defined herein to illustrate certain important functions, and the boundaries and sequence of the flow diagram blocks may be otherwise defined for general application so long as the important functions are still achieved. Variations in the boundaries and sequence of the above described functional blocks, flowchart functional blocks, and steps may be considered within the scope of the following claims. Those skilled in the art will also appreciate that the functional blocks described herein, as well as other illustrative blocks, modules, and components, may be implemented as discrete components, special purpose integrated circuits, processors with appropriate software, and the like.

Claims

1. A portable computing device, comprising:

a front-end module connected to the antenna portion and configured to separate one or more outbound radio frequency signals from one or more inbound radio frequency signals;

a saw-less receiver for:

a baseband processing unit to:

converting outbound data into the one or more outbound symbol streams; and

converting the one or more inbound symbol streams to inbound data.

2. The portable computing device of claim 1, further comprising:

the saw-less receiver is further configured to:

converting the one or more second inbound radio frequency signals to one or more second inbound intermediate frequency signals by:

the baseband processing unit is further configured to:

3. The portable computing device of claim 1, wherein the front end module comprises:

an antenna tuning unit connected to the antenna part and tuned to provide an impedance matching the impedance of the antenna part;

4. The portable computing device of claim 3, wherein the baseband processing unit is further configured to generate at least one of:

a separation control signal for adjusting the attenuation of the one or more output radio frequency signals; and

5. The portable computing device of claim 1, wherein the surface wave free launcher comprises:

a transmit variable frequency bandpass filter for:

an output module to condition the one or more filtered upconverted signals to produce one or more conditioned upconverted signals; and

6. The portable computing device of claim 5, wherein the baseband processing unit is further to:

7. The portable computing device of claim 1, wherein the surface wave free receiver comprises:

a radio-intermediate frequency receiver section comprising:

8. The portable computing device of claim 1, further comprising:

a second integrated circuit for supporting the front end module.

9. The portable computing device of claim 1, further comprising at least one of:

a processing module to:

10. A portable computing device, comprising:

a front end module, the front end module comprising:

a saw-less receiver for converting a plurality of inbound RF signals into a plurality of inbound symbol streams;

a baseband processing unit to: