HK1157079B - Power supply controller and method - Google Patents

Description

Power supply controller and method

Technical Field

The present invention relates generally to power supplies, and more particularly to switched mode power supplies.

Background

Switched Mode Power Supplies (SMPS) are used in a variety of portable electronic devices including laptop computers, cellular telephones, personal digital assistants, video games, cameras, and the like. They may convert a dc signal at one voltage level to a dc signal at a different voltage level (this is a dc-dc converter), an alternating current (ac) signal to a dc signal (this is an ac-dc converter), a dc signal to an ac signal (this is a dc-ac converter), or an ac signal to an ac signal (this is an ac-ac converter). Generally, a switched mode power supply comprises a switching power supply controller or converter which operates in a continuous mode under heavy load conditions, i.e. loads drawing a large current, and in a transition mode or pulse transition mode under light load conditions, i.e. loads drawing a small current. In the past, semiconductor manufacturers have used various methods and structures to form switching power supply controllers, such as Pulse Width Modulation (PWM) power supply controllers that adjust the value of the voltage provided by the power supply system. In some cases, switching power supply controllers can operate at a fixed frequency or in a continuous mode of operation during ordinary operation. Some existing switching power supply controllers operate in a light-load mode skipping some PWM cycles when the current drawn by the load receiving power from the power supply system decreases. When the load again requires a higher current, the switching regulator circuit exits the trip mode and returns to normal operation.

The converter typically includes a compensation network connected to the error amplifier to stabilize the system and optimize the transient response based on small signal behavior patterns. However, when a large signal transient event occurs, such as a step load transient from a light load condition to a full load condition, the converter may not achieve the desired response due to saturation recovery of the compensation network and slew rate limitations of the error amplifier.

Fig. 1 is a prior art schematic diagram of a portion of a power supply system 10 including a switching power supply controller 12. System 10 receives power between power input terminal 14 and power return terminal 16 and forms an output voltage V between output 18 and terminal 16_OUT. The controller 12 is arranged to set the output voltage V_OUTAdjusted to a desired value or a target value within a range of values close to the target value. For example, the target value may be five volts (5v), while the range of values may be plus or minus five percent (5%) approaching five volts. System 10 generally includes a power switch, such as power transistor 20, and an inductor current I connected to control current through an inductor 24₂₄The rectifier 22. The rectifier 22 may be a synchronous metal oxide semiconductor field effect transistor, a diode, or the like. Capacitor 26 is connected between output 18 and terminal 16 to assist in forming output voltage V_OUT. A voltage sensing network 28 may be coupled to output 18 to provide a representative output voltage V at node 30_OUTIs not instantaneous value of the voltage sense signal V_S. By way of example, voltage sensing network 28 includes resistors 32 and 34 having terminals commonly connected together to form node 30. Additionally, resistor 32 has a terminal connected to output 18, and resistor 34 has a terminal connected to power return terminal 16. Voltage sensing network 28 may provide a representative output voltage V at node 30_OUTIs a value of_SAny type of sensing network. Load 36 is commonly connected between output 18 and terminal 16 to receive output voltage V_OUTAnd receives a load current I_LOAD. It should be noted that the load current I_LOADIs a current I₂₄And possibly current I flowing from capacitor 26₂₆The sum of (1).

Switching power supply controller 12 receives operating power from a regulator 35 connected between a power supply input 38 and a power supply return 40. Input 38 and return 40 are typically connected to terminals 14 and 16, respectively. It should be noted that regulator 40 may provide a reference voltage V_REF. Controller 12 is configured to form on output 42 a signal suitable for driving and operating transistor 20 to regulate output voltage V_OUTA switch drive signal of a value of (d). Voltage sense signal V from voltage sense network 28_SReceived by controller 12 on voltage sense input 44.

The controller 12 includes a PWM control module 50 adapted to generate a PWM switching signal that is input into a buffer driver or buffer 52. The buffer 52 has an output terminal connected to the gate terminal of the power transistor 20. Controller 12 also includes a feedback network 54 that includes an operational amplifier 56 and a compensation network 58. By way of example, the compensation network 58 is a passive voltage compensation network. More specifically, operational amplifier 56 functions as an error amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal, where the non-inverting input terminal is coupled to receive reference voltage V_REFThe inverting input terminal is coupled to its output terminal and to the voltage sense node 44 through a compensation network 58. To be provided withBy way of example, the compensation network 58 includes a resistor 60 connected between the inverting input terminal of the operational amplifier 56 and the voltage sense node 44, and a resistor-capacitor network 62 coupled between the inverting input terminal and the output terminal of the operational amplifier 56. The resistor-capacitor network 62 includes a capacitor 64 coupled in parallel with a resistor 66 and a capacitor 68 connected in series. The output terminal of operational amplifier 56 is directly connected to the input terminal of PWM control module 50.

In operation, the power supply system 10 generally operates in one of two modes: a continuous mode of operation or a pulse-hopping (or burst) mode of operation. Under heavy or non-light load conditions, the PWM control module 50 operates at its rated or full operating frequency and the inductor current I₂₄Is continuous. Under light load or no load condition, load current I_LOADReduced and inductor current I₂₄Becomes discontinuous. If the pulse skipping mode is active, the operating frequency or switching frequency at the output terminals of the PWM control module 50 is decreased in response to the decrease in load current, thereby reducing power consumption.

Fig. 2a, 2b, 2c and 2d are graphs showing different signals generated when controller 12 operates in a continuous mode of operation. The abscissa of the graphs 2a, 2b, 2c and 2d represents time, and the ordinate of the graphs 2a, 2b and 2c represents voltage, while the ordinate of the graph 2d represents current. More specifically, graph 2a shows the voltage V that is transmitted from the output terminal of operational amplifier 56 to the input terminal of PWM control module 50_COMP(ii) a Graph 2b shows the output voltage V appearing between output 18 and terminal 16_OUT(ii) a Graph 2c shows the voltage V appearing at node 25_SWNAnd graph 2d shows the inductor current I₂₄. In fig. 2, the controller 12 operates in a continuous pulse PWM mode, so the inductor current I₂₄Is continuous. Under such conditions, operational amplifier 56 is not operating in saturation and there is a slight change in the DC bias of the capacitors of resistor-capacitor network 62, i.e., capacitors 64 and 68. More specifically, in steady state continuous pulse mode of operationThe DC bias across capacitor 68 is substantially equal to the average voltage level at the output terminal of error amplifier 56 and the reference voltage V appearing at the non-inverting input terminal of error amplifier 56 during the continuous pulse mode of operation_REFThe difference between, i.e. V_C68＝V_{COMP_AVG}-V_REF. In pulse transition mode, when the output voltage V_OUTHigher than reference voltage V_REFTime, voltage V_COMPRemains at its minimum level. In this case, the DC bias across capacitor 68 is substantially equal to voltage V_COMPAnd a reference voltage V_REFThe difference between, i.e. V_C68＝V_{COMP_MIN}-V_REF。

When there is an incremental load transient, the voltage V_COMPTo a value substantially equal to the average voltage level of the output terminal of error amplifier 56. Since the DC bias across capacitor 68 cannot be changed immediately, is substantially equal to V_COMP-V_C68-V_REFIs added across resistor 66, which results in a sinking (drop) current being injected into node 59 and through resistor 60. Voltage V_C68Is the voltage across capacitor 68. The extra step-down current results in an extra voltage step-down and in an output voltage V_OUTA longer time is required for recovery.

Fig. 3a, 3b, 3c, and 3d are graphs showing various signals generated by controller 12 when there is an incremental load transient, the transition mode is enabled, and controller 12 operates in the transition mode. The abscissa of the graphs 3a, 3b, 3c and 3d represents time, the ordinate of the graphs 3a, 3b and 3c represents voltage, and the ordinate of the graph 3d represents current. More specifically, graph 3a shows the voltage V that is transmitted from the output terminal of operational amplifier 56 to the input terminal of PWM control module 50_COMP(ii) a Graph 3b shows the output voltage V appearing between output 18 and terminal 16_OUT(ii) a Graph 3c shows the voltage V appearing at node 25_SWN(ii) a Graph 3d shows the inductor current I₂₄And a load current I_LOAD。

Because controller 12 enters the skip mode of operation, the system transient response is reduced due to the DC level deviation in feedback network 54.

Therefore, it would be beneficial to have a power supply controller and method that has a fast transient response under heavy and light load conditions. It is further advantageous that the circuit and method are cost-effective to implement.

Drawings

The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawings in which like reference designators refer to like elements, and in which:

FIG. 1 is a circuit schematic of a prior art portion of a power control system;

FIG. 2a is a graph illustrating voltage signals generated by portions of the prior art power control system of FIG. 1 when they are operated in a continuous pulse mode of operation;

FIG. 2b is a graph illustrating voltage signals generated by portions of the prior art power control system of FIG. 1 when it is operating in a continuous pulse mode of operation;

FIG. 2c is a graph illustrating voltage signals generated by portions of the prior art power control system of FIG. 1 when it is operating in a continuous pulse mode of operation;

FIG. 2d is a graph illustrating current signals generated by portions of the prior art power control system of FIG. 1 when it is operating in a continuous pulse mode of operation;

FIG. 3a is a graph illustrating voltage signals generated by portions of the prior art power control system of FIG. 1 when they operate in a pulse-jump mode of operation;

FIG. 3b is a graph illustrating voltage signals generated by portions of the prior art power control system of FIG. 1 when they operate in a pulse-jump mode of operation;

FIG. 3c is a graph illustrating voltage signals generated by portions of the prior art power control system of FIG. 1 when they operate in a pulse-jump mode of operation;

FIG. 3d is a graph illustrating current signals generated by portions of the prior art power control system of FIG. 1 when they operate in a pulse-jump mode of operation;

FIG. 4 is a circuit schematic of a portion of a power control system according to an embodiment of the present invention;

FIG. 5 is a circuit schematic of a switch suitable for use in part of the power control system shown in FIG. 4;

FIG. 6a is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4;

FIG. 6b is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4;

FIG. 6c is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4;

FIG. 6d is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4;

FIG. 6e is a graph illustrating current signals generated by portions of the power control system of FIG. 4;

FIG. 7a is a graph showing voltage signals generated by portions of the power control system of FIG. 4 when they are operated in a continuous pulse mode of operation;

FIG. 7b is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4 when they are operated in a continuous pulse mode of operation;

FIG. 7c is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4 when they are operated in a continuous pulse mode of operation;

FIG. 7d is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4 when they are operated in a continuous pulse mode of operation;

FIG. 7e is a graph illustrating current signals generated by portions of the power control system of FIG. 4 when they are operated in a continuous mode of operation;

FIG. 8a is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4 when they operate in a pulse-jump mode of operation;

FIG. 8b is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4 when they operate in a pulse-jump mode of operation;

FIG. 8c is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4 when they operate in a pulse-jump mode of operation;

FIG. 8d is a graph illustrating voltage signals generated by portions of the power control system of FIG. 4 when they operate in a pulse-jump mode of operation;

FIG. 8e is a graph illustrating current signals generated by portions of the power control system of FIG. 4 when they are operating in a pulse-jump mode of operation;

FIG. 9 is a circuit schematic of a portion of a power control system according to another embodiment of the present invention.

Detailed Description

Generally, the present invention provides a power supply controller with a feedback controlled switch and a method for compensating an error signal in a feedback network. The power supply controller includes an error amplifier in a feedback path and a switch for opening and closing the feedback loop. The switch functions as an active compensator in the control loop when the controller is operating between the continuous pulse mode of operation and the pulse skipping mode of operation, thereby reducing the slew rate requirements of the error amplifier. In accordance with an embodiment of the present invention, an active switch is inserted into the negative feedback path of the error amplifier. By way of example, the switch is in series with a passive compensation network that provides compensation when the switch is closed and the controller is operating in a continuous pulse mode of operation. When the controller operates in a pulse-jump mode of operation, the controller opens the switch such that the passive charge storage component in the passive compensation network retains the charge stored therein. By maintaining the charge, the controller quickly and efficiently returns to its nominal operating state when changing from a pulse-jump mode of operation to a continuous pulse mode of operation, i.e., after the switch is closed.

In accordance with another embodiment, a power supply controller includes a pulse width modulation control module connected to a compensation network. The compensation network includes an amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal. A passive compensation network is coupled between the inverting input terminal and the output terminal of the amplifier. The switch is coupled between the output terminal of the amplifier and the input terminal of the compensation network.

In accordance with another embodiment, a method for improving transient response of a controller includes generating a feedback signal from a first signal using a compensation network in a closed loop setting, and the controller operates in a continuous pulse mode. The controller varies the feedback signal by opening a feedback loop when operating in the pulse-skipping mode of operation.

It should be noted that the terms light load and heavy load depend on the application and parameters, such as the inductance value of inductor 24. For example, in some applications, where the full load current is 10 amps, the light load current may be 1 amp; but in some applications where the full load current is 1 amp, the light load may be 10 milliamps. Thus, a light load is understood when the load current is less than about 15% of the full load current, and a heavy load is understood when the load current is the full load current or a current level within about 15% of the full load current.

Fig. 4 is a schematic diagram of a portion of a power supply system 100 in accordance with an embodiment of the present invention. Power supply system 100 bagIncluding switching power supply controller 12A, voltage sensing network 28, power transistor 20, rectifier 22, and inductor 24. Switching power supply controller 12A is similar to switching power supply controller 12 except that it includes a feedback network 54A having a passive voltage compensation network 58, a switch 102, a timer 104, and a bias voltage V coupled to capacitors 64 and 68 through a transistor 106_BIAS. It should be noted that the passive voltage compensation network 58 may be a single pole network, i.e., a type I network, a two pole, one zero network, i.e., a type II network, a three pole, two zero network, i.e., a type III network, or other compensation network. The terminals of capacitors 64 and 68 are connected together to form node 105. Switch 102 is connected between node 105 (i.e., at the output of compensation network 62) and the commonly connected output terminal of error amplifier 56 and the input terminal of PWM control module 50. A control terminal of the switch 102 is coupled to an output terminal of the PWM control module 50 through a timer 104. More specifically, the output terminal of the PWM control module 50 is connected to the input terminal of the timer 104 at node 107, and the output terminal of the timer 104 is connected to the control terminal of the switch 102. Resistor 106 limits the voltage V and the output terminal of error amplifier 56_BIASThe current flowing in between. Voltage V_BIASCan be generated by an adaptive DC voltage generator, in which the voltage V_BIASClose to signal V during steady state continuous pulse mode of operation_COMPThe DC voltage level of (a). When the PWM control module 50 is a voltage mode PWM controller voltage, the voltage V_BIASThis may be determined as follows:

V_BIAS＝G_VOUT＊V_OUT+V_RAMP

wherein G is_OUTIs a voltage V_BIAS/V_OUTA ratio of (A) to (B); and

V_RAMPis the offset voltage or valley of the internal ramp signal of the PWM control module 50.

In accordance with an embodiment of the present invention, switch 102 is a transistor, such as a field effect transistor. Fig. 5 shows a transistor 109 with a control electrode and a current conducting electrode. It should be noted that the control electrode of transistor 109 is similar to the control terminal of switch 102, with one current conducting electrode connected to a terminal of passive network 62 and the other current conducting electrode connected to the input terminal of PWM control module 50. Fig. 5 also shows a capacitor 111 coupled between the current conducting terminals of transistor 109. Capacitor 111 may be a parasitic capacitance of transistor 109, or it may be another capacitor with a small capacitance value that smoothes the transition from the skip mode of operation to the continuous mode of operation and provides filtering. By way of example, the capacitance of capacitor 111 is approximately one picofarad.

In operation, the timer 104 detects the output signal of the PWM control module 50 at node 107 and generates a control signal to control the switch 102 in response to the output signal. The timer 104 starts counting after it is reset by the signal of the node 107. When the PWM control module 50 operates in the continuous pulse or critical conduction mode, the timer 104 has a longer timing period than the transition period of the output signal of the PWM control module 50, i.e., the timer 104 generates a Time Out signal (Time _ Out). The timeout signal Time _ Out remains in a valid state until it is reset. Switch 102 is open when signal Time _ Out is in an active state, which opens the feedback loop, and switch 102 is closed when signal Time _ Out is in an inactive state, which closes the feedback loop. Thus, the switch 102 is closed when the PWM control module 50 operates in a continuous pulse mode, and the switch 102 is opened after it skips one or more pulses.

Fig. 6a, 6b, 6c, 6d, and 6e are graphs showing various signals generated by controller 12A, in accordance with an embodiment of the present invention. The abscissa of the graphs 6a, 6b, 6c, 6d and 6e represents time in seconds, the ordinate of the graphs 6a, 6b, 6c and 6d represents voltage, and the ordinate of the graph 6e represents current. More specifically, graph 6a shows the voltage V that is transmitted from the output terminal of operational amplifier 56 to the input terminal of PWM control module 50_COMPAnd a voltage signal V appearing at node 105_COMP1(ii) a Graph 6b shows the current appearing at node 107, i.e., the output terminal of PWM controller 50Pressure V_PWM(ii) a Graph 6c shows the signal Time _ Out sent from the timer 104 to the control terminal of the switch 102; graph 6d shows the output voltage V appearing between output 18 and terminal 16_OUTAnd a reference voltage V_REF(ii) a And graph 6e shows the inductor current I₂₄And a load current I_LOAD。

Still referring to FIGS. 6a, 6b, 6c, 6d and 6e, at time t₀The controller 12A operates in a continuous pulse PWM mode, so that the inductor current I₂₄Is continuous and carries a current I_LOADIs high. The timer 104 is presented with a PWM pulse V at the output terminal of the PWM controller 50 at each cycle_PWMAnd (4) resetting. Thus, the signal Time _ Out generated by the timer 104 remains at a logic high voltage level and the switch 102 is closed, i.e., the transistor 109 is turned on. In this case, feedback network 54A operates in a closed loop setting and the output signal V of error amplifier 56_COMPAnd a signal V appearing at the input of switch 102_COMP1At substantially the same voltage level. Signal V_COMPReferred to as the return loop output signal.

At time t₁Load release occurs, i.e., the load changes from a heavy load to a light load, so the energy stored in inductor 24 charges capacitor 26. Responsive to the output voltage V_OUTFrom error amplifier 56, voltage V_COMPFalls to a logic zero voltage and PWM controller 50 outputs a logic low voltage level, which prevents output voltage V from being output_OUTOvershoot of (3). Inductor current I₂₄Decreases and the power supply system 100 enters a pulse transition mode. Because the timer 104 is at time t₀Reset and then no PWM pulse (VPWM) at time t₂A timeout signal Time _ Out appearing at the output terminal of the timer 104 is for a predetermined period of Time T_timerIs effective.

At time t₂Thereafter, the switch 102 is opened, i.e. when the switch 102 is implemented using the transistor 109, the transistor 109 is turned off. In this case, feedback network 54A operates in an open loop setting,which changes the feedback loop output signal V_COMP. It should be noted that in the open loop configuration, error amplifier 56 operates as a comparator. Because of the output voltage V_OUTHigher than reference voltage V_REFOutput signal V from error amplifier 56_COMPRemaining at a low saturation level. The voltage V appearing at node 105_COMP1Rises and substantially equals voltage V_BIASStabilized at the same voltage level, the voltage V_BIASVoltage signal V in near steady state continuous pulse mode of operation_COMPThe DC voltage level of (a).

At slave time t₂To time t₅During the time period of (1), the load current I_LOADIs very low and it discharges the output capacitor 26, which slowly decreases the output voltage V_OUT。

At time t₃Output voltage V_OUTCross over reference voltage V_REFAnd the voltage V from error amplifier 56_COMPIncreasing, triggers the PWM controller 50 to generate a PWM pulse, thereby resetting the timer 104. The reset timer 104 causes the switch 102 to close, e.g., if the switch 102 is implemented by a transistor 109, the reset timer 104 turns on the transistor 109. Because the load is small, the energy from a single PWM pulse is sufficient to drive the output voltage V_OUTMaintained at a reference voltage V_REFA high level.

At time t₄The signal Time _ Out becomes active again and the switch 102 is opened, e.g., the transistor 109 is turned off.

At time t₅When the load increment signal occurs after the quiescent period, error amplifier 56 operates like a comparator and quickly generates output signal V at a logic high voltage level_COMP。

At time t₆The PWM controller 50 resets the PWM pulse of the timer 104. At time t₆The PWM controller 50 then continuously outputs PWM pulses to provide energy to the load 36 and the switch 102 remains closed, e.g., the transistor 109 remains conductive.

Fig. 7a, 7b, 7c, 7d and 7e are graphs showing various signals generated by controller 12A when it is operating in a continuous mode of operation. The abscissa of the graphs 7a, 7b, 7c, 7d and 7e represents time, and the ordinate of the graphs 7a, 7b, 7c and 7d represents voltage, while the ordinate of the graph 7e represents current. More specifically, graph 7a shows the voltage V at node 57_COMPAnd the voltage V of the node 105_COMP1(ii) a Graph 7b shows the signal Time _ Out; graph 7c shows the output voltage V appearing between output 18 and terminal 16_OUT(ii) a Graph 7d shows the voltage V appearing at node 25_SWN(ii) a Graph 7e shows the inductor current I₂₄. In FIG. 7, controller 12A operates in a continuous pulse PWM mode, so inductor current I₂₄Is continuous. In this case, operational amplifier 56 is not operating in saturation and there is a small change in the DC bias of the capacitors of resistor-capacitor network 62, i.e., capacitors 64 and 68. More specifically, during steady state continuous pulse operation, the DC bias across capacitor 68 is substantially equal to the average voltage level at the output terminal of error amplifier 56 and the reference voltage V appearing at the non-inverting input terminal during the continuous pulse mode of operation_REFThe difference between them.

When there is an incremental load transient, the voltage V_COMPBack to a value substantially equal to the average voltage level of the output terminal of error amplifier 56. Fig. 8a, 8b, 8c, 8d, and 8e are graphs showing various signals generated by controller 12A when there is an incremental load transient and converter 12A has been operating in a skip mode, i.e., the skip mode is active. The abscissa of the graphs 8a, 8b, 8c, 8d and 8e represents time, and the ordinate of the graphs 8a, 8b, 8c and 8d represents voltage, while the ordinate of the graph 8e represents current. More specifically, graph 8a shows the voltage V at node 57_COMPAnd the voltage V of the node 105_COMP1(ii) a Graph 8b shows the voltage Time _ Out; graph 8c shows the output voltage V appearing between output 18 and terminal 16_OUT(ii) a Graph 8d shows the voltage V appearing at node 25_SWN(ii) a And graph 8e shows the inductor current I₂₄. It should be noted that power supply system 100 has a faster response than power supply system 10 in both the continuous mode of operation and the skip mode of operation in accordance with an embodiment of the present invention because error amplifier 56 does not need to operate the entire feedback network 54A out of saturation, i.e., the feedback network acts as a load for error amplifier 56 and there is no large DC bias variation in compensation capacitors 64 and 68.

Fig. 9 is a schematic diagram of a portion of a power supply system 150 in accordance with another embodiment of the present invention. Power supply system 150 includes switching power supply controller 12B, voltage sensing network 28, power transistor 20, rectifier 22, and inductor 24. The controller 12B is similar to the switching power supply controller 12A except that the switching power supply controller 12B includes a feedback network 54B having a power supply detection network or voltage detector 152, the power supply detection network or voltage detector 152 having an input terminal connected to the output terminal of the error amplifier 56 and an output terminal connected to the control terminal of the switch 102 instead of to the timer 104. Thus, timer 104 is not present in feedback network 54B. Switch 102 is connected between output compensation network 62 and the commonly connected output terminal of error amplifier 56 and the input terminal of PWM control module 50 at node 57.

In operation, voltage detector 152 monitors error signal V_COMPAnd controls the switch 102. When error amplifier 56 enters the saturation range, voltage detector 152 opens switch 102, e.g., turns off transistor 109, thereby disconnecting compensation network 58 from node 57, and when error signal V_COMPIs within a normal range and compensation network 58 is reconnected to node 57.

Although specific embodiments are disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. For example, the switching network may be used for other types of converters such as boost converters, buck-boost converters, and the like. It is intended that the present invention embrace all such modifications and variations as fall within the scope of the appended claims.

Claims (11)

1. A power supply controller (12A, 12B) comprising:

a pulse width modulation control module (50) having an input and an output; and

a feedback network (54A, 54B) having a first input and an output connected to the input of the pulse width modulation control module (50), wherein the feedback network comprises (54A, 54B):

an amplifier (56) having an inverting input terminal, a non-inverting input terminal, and an output terminal;

a compensation network (58) having a first node (105) and a second node (59);

a switch (102) having first and second current conducting terminals and a control terminal, the first current conducting terminal coupled to the first node (105) of the compensation network and the second current conducting terminal coupled to the output terminal of the amplifier (56) and the input of the pulse width modulation control module (50), an

The control terminal is coupled to the output of the pulse width modulation control module (50), wherein the feedback network operates in an open loop setting in response to the switch being opened and operates in a closed loop setting in response to the switch being closed.

2. The power supply controller (12A, 12B) of claim 1, further comprising a timer (104) having an input coupled to the output of the pulse width control module (50) and an output coupled to the control terminal of the switch (102).

3. The power supply controller (12A, 12B) of claim 2, further comprising:

bias voltage (V)_BIAS) -the first current conducting terminal coupled to the switch (102); and

a first resistor (106), wherein the bias voltage (V)_BIAS) Coupled to the first current conducting terminal of the switch (102) through the first resistor (106).

4. The power supply controller (12A, 12B) of claim 1, further comprising a first capacitor coupled between the first current conducting terminal and the second current conducting terminal.

5. A power supply controller (12B) comprising:

a pulse width modulation control module (50) having an input and an output; and

a feedback network (54B) having a first input and an output, the output connected to the input of the pulse width modulation control module (50), wherein the feedback network comprises (54B):

an amplifier (56) having an inverting input terminal, a non-inverting input terminal, and an output terminal;

a compensation network (58) having a first node (105) and a second node (59);

a switch (102) having first and second current conducting terminals and a control terminal, the first current conducting terminal coupled to the first node (105) of the compensation network and the second current conducting terminal coupled to the output terminal of the amplifier (56) and the input of the pulse width modulation control module (50), an

A voltage detector (152) having an input and an output, the input coupled to the output terminal of the amplifier (56) and the output coupled to the control terminal of the switch (102);

bias voltage (V)_BIAS) -the first current conducting terminal coupled to the switch (102); and

a first resistor (106), wherein the bias voltage (V)_BIAS) Coupled to the first current conducting terminal of the switch (102) through the resistor (106), wherein the feedback network operates in an open loop setting in response to the switch being opened and operates in a closed loop setting in response to the switch being closed.

6. The power supply controller (12B) of claim 5 further comprising a first capacitor coupled between the first current conducting terminal and the second current conducting terminal.

7. A method for improving transient response of a controller, comprising:

generating a first signal at an output of an error amplifier in response to a reference voltage at an input of the error amplifier and a sense voltage, wherein the sense voltage represents a non-instantaneous value of an output voltage of the controller;

generating a feedback loop output signal (V) using the first signal by operating a compensation network (58) in a closed loop setting and using a pulse width modulation control module and a timer to control a switch coupled between an inverting input of the error amplifier and an output of the error amplifier_COMP) (ii) a And

changing the feedback loop output signal (V) by_COMP): the compensation network (58) is operated in an open loop setting by opening a switch in response to the error amplifier entering a saturation range, and in a closed loop setting in response to the feedback loop output signal being in its normal range.

8. The method of claim 7, further comprising:

generating the feedback loop output signal (V) when the switch (102) is in a closed setting_COMP) (ii) a And

the transistor is turned on to close the switch (102).

9. The method of claim 7, wherein the feedback loop output signal (V) is varied_COMP) The method comprises the following steps:

starting a timer (104) after the timer (104) is reset by the first signal, wherein the timer (104) has a timing period longer than at least one critical conduction mode transition period of the first signal.

10. The method of claim 7, further comprising generating the feedback loop output signal (V) in response to the controller (12A, 12B) operating in a continuous pulse mode_COMP) And changing the operation mode of the controller from a continuous pulse operation mode to a pulse jump operation mode to change the feedback loop output signal (V)_COMP)。

11. A method for improving transient response of a controller, comprising:

generating a first signal at an output of an error amplifier in response to a reference voltage at an input of the error amplifier and a sense voltage, wherein the sense voltage represents a non-instantaneous value of an output voltage of the controller;

generating a feedback loop output signal (V) by operating a compensation network (58) in a closed loop setting using the first signal_COMP) And monitoring the feedback loop output signal using a voltage detector by closing a switch coupled between an inverting input of the error amplifier and an output of the error amplifier; and

changing the feedback loop output signal (V) by_COMP): the compensation network (58) is operated in an open loop setting by opening a switch in response to the error amplifier entering a saturation range, and in a closed loop setting in response to the feedback loop output signal being in its normal range.