HK1155860B - Charge pump converter and method therefor - Google Patents

Description

Charge pump converter and method thereof

Technical Field

The present invention relates generally to electronics, and more particularly to methods and structures for forming semiconductor devices.

Background

In the past, the semiconductor industry utilized various methods and circuits to form charge pump converter circuits. These charge pump converter circuits are typically used to receive a voltage from an energy source, such as a battery, and produce various output voltages that are proportional to the value of the input voltage. With the implementation of Energy saving specifications such as Energy-Star (Energy-Star), it becomes important for charge pump converters to more efficiently utilize Energy from an Energy source. In some implementations, the charge pump converter monitors the value of the current provided to the load in order to adjust the amount of current provided to the load. However, in general, the efficiency of such implementation is not sufficient to meet all energy saving regulations.

Accordingly, a charge pump converter having high efficiency and having low cost is desired.

Drawings

Fig. 1 schematically illustrates an embodiment of a portion of a charge pump converter system including a charge pump converter according to the present invention; and

fig. 2 schematically shows an enlarged plan view of a semiconductor device comprising the charge pump converter of fig. 1 according to the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and components are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor, or a collector or emitter of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of a device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Although these devices are explained herein as certain N-channel or P-channel devices, one skilled in the art will recognize that complementary devices are also possible in accordance with the present invention. It will be appreciated by those skilled in the art that the term "during.. at the same time, when.. is used" is not an exact term to indicate that an action will occur as soon as there is a start-up action, but rather there may be some slight but reasonable delay, such as a propagation delay, between reactions provoked by the initial action. The use of "about" or "substantially" means that the value of the component has a parameter that is expected to be very close to a specified value or position. However, as is known in the art, there are always minor variations that prevent the above values or positions from being exactly as specified.

Detailed Description

Fig. 1 schematically illustrates an embodiment of a portion of a charge pump converter system 10, the charge pump converter system 10 receiving an input voltage from a battery 11 and forming an output voltage across an output capacitor 14. The system 10 includes a charge pump converter 20, the charge pump converter 20 receiving an input voltage from the battery 11 and controlling charging of the capacitor 14 to form an output voltage. The inverter 20 controls the charging and discharging of a flying capacitor (fly capacitor)17 to form an output voltage across the capacitor 14. Capacitor 14 facilitates providing load current and power to load 16. Load 16 is shown to include a light emitting diode connected in series with a current source to emit light from the light emitting diode. However, those skilled in the art will recognize that load 16 may be various other types of loads.

The charge pump converter 20 includes a plurality of transistors operatively coupled to be selectively enabled (enabled) according to different values of an input voltage received from the battery 11. The plurality of transistors are selectively enabled to provide a charging current (Ic) to charge the flying capacitor 17 during the charging cycle formed by the inverter 20. When the value of the input voltage decreases, the converter 20 selectively increases the number of the plurality of transistors that are enabled in order to control the value of the charging current (Ic) provided to charge the capacitor 17. The converter 20 includes a voltage input 21 and a voltage return 22 connected to the positive terminal 12 and the negative terminal 13, respectively, of the battery 11 to receive an input voltage. Capacitor terminals 25 and 26 of converter 20 are configured to be coupled to flying capacitor 17 and output terminal 23 is configured to be coupled to capacitor 14 in order to charge capacitor 14 to the desired value of the output voltage.

Converter 20 includes a clock circuit or clock 28 that generates a plurality of clock signals including a charge clock (C) signal that is active during a charge cycle of converter 20 and a discharge clock (D) signal that is active during a discharge cycle of converter 20. The charge clock (C) signal and the discharge clock (D) signal are generally out of phase with each other and may include a slight time interval in which neither signal is active in order to ensure that there is no overlap between the charge and discharge cycles. Transistors 31-39 are configured to provide a charging current (Ic) for charging capacitor 17. The additional plurality of transistors 57-65 are configured to provide a discharge current (Id) for charging the output capacitor 14 and to provide current to the load 16 from the flying capacitor 17 and the battery 11. Control circuit 80 receives the input voltage and forms a plurality of control signals that facilitate controlling the state of transistors 32-35 in response to different values of the input voltage during the charging period and that facilitate controlling the state of transistors 58-61 in response to different values of the input voltage during the discharging period. Circuit 80 includes a plurality of nand gates 43-46 that facilitate controlling the state of respective transistors 32-35 and a plurality of nand gates 68-71 that facilitate controlling the state of respective transistors 58-61. The exemplary embodiment of the circuit 80 shown in fig. 1 comprises a resistive divider consisting of resistors 81-85 forming four different sense signals representing the instantaneous value of the input voltage, a reference generator or reference 92 forming a reference signal, and comparators 88-91 receiving the four sense signals and comparing them with the reference signal from the reference 92.

Another control circuit 94 of converter 20 receives the output voltage and the input voltage and forms a plurality of control signals that facilitate controlling the states of transistors 36-39 in response to differences between different values of the input voltage and the output voltage during a charging cycle and that facilitate controlling the states of transistors 62-65 in response to differences between different states of the input voltage and the output voltage during a discharging cycle. Circuit 94 includes a plurality of nand gates 47-50 that facilitate controlling the state of respective transistors 36-39 and a plurality of nand gates 72-75 that facilitate controlling the state of respective transistors 62-65. The exemplary embodiment of the circuit 94 shown in fig. 1 includes a resistive voltage divider formed by resistors 95-99 that receives the output voltage and forms a different sense signal representative of the instantaneous value of the output voltage, and another resistive voltage divider formed by resistors 106 and 107 that forms a reference signal representative of the value of the instantaneous value of the input voltage on node 108. A plurality of comparators 101-104 receive the sense signals from the resistive divider formed by resistors 95-99 and compare them to the reference signal from resistor 106-107 and form a plurality of control signals.

In operation, the charge clock (C) signal goes high to assert the C signal, and the discharge clock (D) signal goes low to negate the D signal, and these states of the C and D signals indicate the charge cycle of the converter 20. The low D signal forces the output of inverter 54 high to disable transistor 53. The low D signal also forces the output of inverter 67 high and the outputs of and gates 68-75 high to disable all transistors 57-65. The high C signal enables transistor 77, which couples bottom plate capacitor 17 to return 22. The high C signal also forces the output of inverter 42 low to enable transistor 31. Enabling transistor 31 couples terminal 25 to voltage input 21, thus coupling the top plate of capacitor 17 to voltage input 21. Thus, capacitor 17 is connected in parallel with battery 11, and charging current Ic flows from battery 11 through transistor 31 to output 25 to begin charging capacitor 17. In addition, circuit 80 forms a plurality of control signals that determine the state of transistors 32-35 during this charging period. If the battery 11 is charged to a high voltage, the voltage received on the inverting input of each comparator 88-91 may be greater than the reference signal from reference 92, and thus the output of each comparator 88-91 will be low. The low from comparator 88 forces the output of gate 43 high and disables transistor 32. Similarly, the low signal from the output of each of comparators 89-91 forces the output of each of respective gates 44-46 high to disable respective transistors 33-35. Since only transistor 31 is enabled, the value of the charging current Ic is lower than when all transistors 32-35 are also enabled. If the value of the input voltage to the battery 11 is low such that the inverting input of the comparator 91 is less than the value of the reference signal from the reference 92, the output of the comparator 91 will be high. The high signal from comparator 91 and the high C signal force the output of gate 46 low, enabling transistor 35. Enabling transistors 31 and 35 in parallel reduces the series impedance of the transistors, thereby increasing the value of charging current Ic for lower values of the input voltage. If the value of the voltage of battery 11 is even lower, the output of comparator 90 may also be forced high to additionally enable transistor 34 through gate 45 to further reduce the impedance and increase the value of current Ic. Further reduction of the input voltage will force the output of comparator 89 high as well and additionally enable transistor 33 through gate 44, and further reduction of the input voltage will force the output of comparator 88 high to additionally enable transistor 32 through gate 43. As can be seen, each of the transistors 32-35 is selectively enabled during the charging period in response to different values of the input voltage in order to vary the value of the charging current Ic. When the value of the input voltage is high, the higher impedance formed by the converter 20 slowly charges the capacitor 17 and prevents large spikes or inrush currents. Selectively controlling the value of the charging current as the value of the input voltage decreases provides for a longer life of the battery 11 and more efficient operation of the system 10.

Controller 94 also forms a plurality of control signals that are used to selectively enable transistors 36-39 during the charging cycle to further control the value of charging current Ic and limit the value of the inrush current. Assuming that the output capacitor 14 is initially discharged and the output voltage is approximately zero volts (0V), the value of the input voltage is greater than the value of the output voltage, and the reference signal received from the input voltage at node 108 and received by the inverting input of the comparator 101-104 is greater than any sense signal received from the output voltage at the non-inverting input of the comparator 101-104. Thus, all control signals formed by comparators 101-104 are low or inactive. The low from comparator 101 forces the output of gate 47 high to disable transistor 36. Similarly, the low signals from comparators 102-104 force the output of the respective gates 48-50 high to disable the respective transistors 37-39. Thus, the control signal formed by circuit 94 selectively disables transistors 36-39 and does not affect the value of current Ic. If the value of the output voltage on capacitor 14 is large, the sense signal on the non-inverting input of comparator 101 may be greater than the reference signal, which will force the control signal on the output of comparator 101 high, enabling transistor 36 through gate 47. Enabling transistor 36 further decreases the series resistance and increases the value of charging current Ic in response to the difference between the value of the input voltage and the value of the output voltage. If the value of the output voltage developed across capacitor 14 is greater, the output of comparator 102 may also go high, thereby also enabling transistor 37 through gate 48 and further reducing the series impedance and increasing the value of charging current Ic. Further increases in the output voltage may additionally force the output of comparator 103 high, enabling transistor 38 through gate 49, while further increases in the output voltage may also force the output of comparator 104 high and enabling transistor 39 through gate 50. If the value of the input voltage increases such that the reference signal on node 108 is greater than one of the values of the output voltage, comparator 101 and 104 are configured to selectively reduce the value of current Ic to prevent a large current from battery 11 from charging capacitor 17. As such, circuit 94 is configured to selectively control the value of current Ic in response to the difference between the values of the input voltage and the output voltage formed by resistors 95-99. When the value of the output voltage is lower than a different ratio or value of the input voltage, the lower impedance formed by the converter 20 slowly charges the capacitor 14 from the battery 11 and the capacitor 17, thereby preventing large current spikes or inrush currents. Selectively controlling the value of the charging current in response to the difference between the values of the input voltage and the output voltage provides for a longer life of the battery 11 and more efficient operation of the system 10.

After a first time interval, clock 28 forces the charge clock (C) signal low and then forces the discharge clock (D) signal high to form a discharge cycle of converter 20. The low C signal forces the output of inverter 42 and the output of nand gates 43-50 high, thereby disabling all transistors 31-39. The low C signal also disables transistor 77, which decouples capacitor 17 from return 22. The high D signal forces the output of inverter 54 low, enabling transistor 53, which couples terminal 23 to terminal 25 and the positively charged plate of capacitor 17. The high D signal also forces the output of inverter 67 high to enable transistor 57. Enabling transistor 57 couples the bottom plate or negatively charged plate of capacitor 17 to receive the input voltage from input 21 and provides a discharge current Id to begin charging capacitor 14 from capacitor 17 and battery 11. Circuit 80 forms a plurality of control signals to selectively enable transistors 58-61 in response to a plurality of values of the input voltage during the discharge period, similar to the description of the plurality of control signals of circuit 80 during the charge period. Thus, for a first low value of the input voltage that causes the signal on the inverting input of comparator 88 to be less than the reference signal from reference 92, all control signals of circuit 80 are high, thereby enabling all transistors 58-61. For higher input voltage values, comparator 88 may force the control signal low to disable transistor 58. The next higher input voltage value may force comparator 89 low to disable transistor 59, while an even higher input voltage value may force comparator 90 low to disable transistor 60, and an even higher input voltage value may force comparator 91 high to enable transistor 61. As can be seen, each transistor 58-61 is selectively enabled during the discharge period in response to different values of the input voltage in order to control the value of the discharge current Id during the discharge period. When the value of the input voltage is high, the higher impedance formed by the converter 20 slowly charges the capacitor 14 from the battery 11 and the capacitor 17, thereby preventing a large current spike or inrush current. Selectively controlling the value of the discharge current Id in response to different values of the input voltage provides for longer life of the battery 11 and more efficient operation of the system 10.

During the discharge period, circuit 94 selectively enables transistors 62-65 in response to the difference between the values of the input voltage and the output voltage, similar to the operation described for circuit 94 during the charge period. If the difference between the instantaneous value of the input voltage and the instantaneous value of the output voltage is low enough that the non-inverting input of comparator 101 is less than the reference signal on node 108, then all of comparators 101-104 are low, thereby selectively disabling all of transistors 62-65. If the input voltage decreases or the output voltage increases (e.g., by charging capacitor 17) and the output voltage can reach a threshold value defined by the ratio of the input voltages provided by the resistors, the output of comparator 101 can be forced high to enable transistor 62 through gate 72. Similarly, a further increase in the output voltage (or decrease in the input voltage) may reach second, third and fourth thresholds defined as second, third or fourth ratios or values of the input voltage, and may cause comparator 102, then 103, then 104 to selectively enable respective transistors 63, 64 and 65. As can be seen, the circuit 94 is configured to selectively control the value of the current Id in response to several or more differences between the instantaneous value of the input voltage and the instantaneous value of the output voltage. When the value of the output voltage is lower than a different ratio of the input voltage, the lower impedance formed by the converter 20 slowly provides the discharge current Id, thereby preventing large current spikes or surge currents. Selectively controlling the value of the discharge current Id in response to the difference between the values of the input voltage and the output voltage provides for a longer life of the battery 11 and more efficient operation of the system 10.

To facilitate this function of converter 20, the charge clock output of clock 28 is commonly connected to the gate of transistor 77, the input of inverter 42, and the input of each gate 43-50. The output of inverter 42 is connected to the gate of transistor 31. A source of transistor 31 is commonly connected to input 21, a first terminal of resistor 81, a source of each of transistors 32-39, and a first terminal of resistor 106. A drain of transistor 31 is commonly connected to a drain of each of transistors 32-39, a source of transistor 53, and terminal 25. The discharge clock output of clock 28 is commonly connected to an input of inverter 54, an input of inverter 67, and a first input of each gate 68-75. An inverting input of comparator 88 is connected to the second terminal of resistor 81 and the first terminal of resistor 82. An inverting input of comparator 89 is connected to a second terminal of resistor 82 and a first terminal of resistor 83. An inverting input of comparator 90 is connected to a second terminal of resistor 83 and a first terminal of resistor 84. An inverting input of comparator 91 is connected to a second terminal of resistor 84 and a first terminal of resistor 85, resistor 85 having a second terminal connected to return 22. The output of reference 92 is commonly connected to the non-inverting input of comparators 88-91. An output of comparator 88 is commonly connected to a second input of gate 43 and a second input of gate 68. The output of gate 43 is connected to the gate of transistor 32 and the output of gate 68 is connected to the gate of transistor 58. The output of comparator 89 is commonly connected to a second input of gate 44 and a second input of gate 69. The output of gate 44 is connected to the gate of transistor 33 and the output of gate 69 is connected to the gate of transistor 59. An output of comparator 90 is commonly connected to a second input of gate 45 and a second input of gate 70. The output of gate 45 is connected to the gate of transistor 34 and the output of gate 70 is connected to the gate of transistor 60. An output of comparator 91 is commonly connected to a second input of gate 46 and a second input of gate 71. The output of gate 46 is connected to the gate of transistor 35 and the output of gate 71 is connected to the gate of transistor 61. A second terminal of resistor 106 is connected to node 108 and a first terminal of resistor 107, resistor 107 having a second terminal connected to return 22. A first terminal of resistor 95 is commonly connected to terminal 23 and the drain of transistor 53. A second terminal of resistor 95 is commonly connected to a non-inverting input of comparator 101 and a first terminal of resistor 96. A second terminal of resistor 96 is commonly connected to a non-inverting input of comparator 102 and a first terminal of resistor 97. A second terminal of resistor 97 is commonly connected to a non-inverting input of comparator 103 and a first terminal of resistor 98. A second terminal of resistor 98 is commonly connected to a non-inverting input of comparator 104 and a first terminal of resistor 99, resistor 99 having a second terminal connected to return 22. An inverting input of comparator 104 is connected to node 108 and an output of comparator 104 is commonly connected to a second input of gate 50 and a second input of gate 75. The output of gate 50 is connected to the gate of transistor 39 and the output of gate 75 is connected to the gate of transistor 65. An inverting input of comparator 103 is connected to node 108 and an output is commonly connected to a second input of gate 49 and a second input of gate 74. The output of gate 49 is connected to the gate of transistor 38 and the output of gate 74 is connected to the gate of transistor 64. An inverting input of comparator 102 is connected to node 108 and an output is commonly connected to a second input of gate 48 and a second input of gate 73. The output of gate 48 is connected to the gate of transistor 37 and the output of gate 73 is connected to the gate of transistor 63. An inverting input of comparator 101 is connected to node 108 and an output is commonly connected to a second input of gate 47 and a second input of gate 72. The output of gate 47 is connected to the gate of transistor 36 and the output of gate 72 is connected to the gate of transistor 62. A source of transistor 57 is commonly connected to terminal 26, a drain of transistor 77, and a source of each of transistors 58-65. A drain of transistor 57 is commonly connected to input 21 and to a drain of each of transistors 58-65. A source of transistor 77 is connected to return 22. The output of inverter 54 is connected to the gate of transistor 53. The output of inverter 67 is connected to the gate of transistor 57.

Fig. 2 schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 115 that is formed on a semiconductor die 116. Transducer 20 is formed on die 116. Die 116 may also include other circuits that are not shown in fig. 2 for simplicity of the drawing. Translator 20 and device or integrated circuit 115 are formed on die 115 by semiconductor fabrication techniques, which are known to those skilled in the art.

In view of the foregoing, it is apparent that a new device and method is disclosed. Included, among other features, is configuring circuit 80 to selectively enable different ones of the plurality of parallel coupled transistors 32-35 in response to different values of the input voltage to form a charging current Ic that charges flying capacitor 17 during a charging cycle of converter 20. Using different values of the input voltage increases the efficiency, and also using the difference between the different values of the input voltage and the output voltage further increases the efficiency. When integrated on a silicon semiconductor die, the use of comparators and resistor dividers to form the different values and control signals results in a simple configuration with low cost.

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, circuits 80 and 94 may use other circuit configurations instead of resistive voltage dividers and comparators to form different values for the input and output voltages. Moreover, the word "connected" is used throughout for clarity of description, but is intended to have the same meaning as the word "coupled". Accordingly, "connected" should be interpreted to include direct connections or indirect connections.

Claims (19)

1. A charge pump converter, comprising:

an output terminal configured to couple with an output capacitor and form an output voltage on the output capacitor;

a plurality of terminals configured to couple with a flying capacitor;

a first plurality of transistors coupled to receive an input voltage and form a charging current that charges the flying capacitor, wherein the first plurality of transistors are operably coupled to be selectively enabled in response to a value of the input voltage but not a value of the output voltage during a charging period of the charge pump converter;

a second plurality of transistors coupled to receive the input voltage and form the charging current that charges the flying capacitor, wherein the second plurality of transistors are operably coupled to be selectively enabled during the charging period in response to a difference between values of the input voltage and the output voltage;

a third plurality of transistors coupled to receive the input voltage and form a discharge current that discharges the flying capacitor to the output capacitor, wherein the third plurality of transistors are operably coupled to be selectively enabled in response to the value of the input voltage but not the value of the output voltage during a discharge period of the charge pump converter; and

a fourth plurality of transistors coupled to receive the input voltage and form the discharge current, wherein the fourth plurality of transistors are operably coupled to be selectively enabled in response to a difference between the values of the input voltage and the output voltage during the discharge period.

2. The charge pump converter of claim 1 further comprising a first control circuit configured to receive the input voltage and form a first plurality of control signals in response to a plurality of values of the input voltage other than a value of the output voltage, wherein the first plurality of control signals are coupled to the first plurality of transistors to selectively enable the first plurality of transistors in response to the plurality of values of the input voltage other than a value of the output voltage.

3. The charge pump converter of claim 2 wherein the first control circuit comprises a first plurality of comparators each coupled to receive a sense signal of a first plurality of sense signals, wherein each sense signal represents a different value of the input voltage, and wherein each comparator of the first plurality of comparators compares the sense signal to a first reference signal to form a control signal of the first plurality of control signals.

4. The charge pump converter of claim 3 wherein the first control circuit comprises a first plurality of logic gates coupled to receive the plurality of control signals and to receive a first clock signal representative of the charging period, and to enable the first plurality of transistors in response to the value of the input voltage during the charging period.

5. The charge pump converter of claim 4 wherein the first plurality of control signals are coupled to the third plurality of transistors to selectively enable the third plurality of transistors in response to the plurality of values of the input voltage during the discharge period.

6. The charge pump converter of claim 5 wherein the first control circuit comprises a second plurality of logic gates coupled to receive the first plurality of control signals and to receive a second clock signal representative of the discharge period, and to enable the third plurality of transistors in response to the value of the input voltage during the discharge period.

7. The charge pump converter of claim 2 further comprising a second control circuit configured to receive the input voltage and the output voltage and to form a second plurality of control signals in response to a difference between the values of the input voltage and the output voltage, wherein the second plurality of control signals are coupled to the second plurality of transistors to selectively enable the second plurality of transistors in response to a difference between the values of the input voltage and the output voltage during the charging period.

8. The charge pump converter of claim 7 wherein the second control circuit comprises a plurality of comparators, each of the plurality of comparators coupled to receive a sense signal representing a different value of the output voltage, and wherein each of the plurality of comparators compares the sense signal to a reference signal representing the input voltage to form a control signal of the second plurality of control signals.

9. The charge pump converter of claim 8 wherein the second control circuit comprises a first plurality of logic gates coupled to receive the second plurality of control signals and to receive a first clock signal representative of the charging period, and to enable the second plurality of transistors in response to a difference between the input voltage and the value of the output voltage during the charging period.

10. The charge pump converter of claim 9, wherein the second control circuit comprises a second plurality of logic gates coupled to receive the second plurality of control signals and to receive a second clock signal representative of the discharge period, and to enable the fourth plurality of transistors in response to a difference between the input voltage and the value of the output voltage during the discharge period.

11. A charge pump converter, comprising:

an output terminal configured to couple with an output capacitor and form an output voltage on the output capacitor;

a plurality of terminals configured to couple with a flying capacitor;

a first plurality of transistors coupled to receive an input voltage and form a charging current that charges the flying capacitor, wherein the first plurality of transistors are operably coupled to be selectively enabled in response to a value of the input voltage but not a value of the output voltage during a charging period of the charge pump converter;

a second plurality of transistors coupled to receive the input voltage and form the charging current to charge the flying capacitor, wherein the second plurality of transistors are operably coupled to be selectively enabled in response to a difference between values of the input voltage and the output voltage during the charging period.

12. The charge pump converter of claim 11 wherein the first plurality of transistors operably coupled to be selectively enabled in response to the value of the input voltage but not the value of the output voltage comprises: each transistor of the first plurality of transistors is coupled to be selectively enabled in response to a different value of the input voltage.

13. The charge pump converter of claim 12 wherein a first transistor of a first plurality of transistors is operably coupled to be selectively enabled in response to a first value of the input voltage, a second transistor of the first plurality of transistors is operably coupled to be selectively enabled in response to a second value of the input voltage, a third transistor of the first plurality of transistors is operably coupled to be selectively enabled in response to a third value of the input voltage, and a fourth transistor of the first plurality of transistors is operably coupled to be selectively enabled in response to a fourth value of the input voltage, wherein the first value is greater than the second value, the second value is greater than the third value, and the third value is greater than the fourth value.

14. The charge pump converter of claim 11 further comprising: a third plurality of transistors coupled to receive the input voltage and form a discharge current that discharges the flying capacitor to the output capacitor, wherein the third plurality of transistors are operably coupled to be selectively enabled in response to the value of the input voltage but not the value of the output voltage during a discharge period of the charge pump converter; and

a fourth plurality of transistors coupled to receive the input voltage and form the discharge current, wherein the fourth plurality of transistors are operably coupled to be selectively enabled in response to a difference between the values of the input voltage and the output voltage during the discharge period.

15. A method of forming a charge pump converter, comprising the steps of:

providing an output terminal configured to be coupled with an output capacitor to form an output voltage on the output capacitor;

providing a plurality of terminals configured to couple with a flying capacitor; and

a first circuit is configured to selectively enable different transistors of a first plurality of parallel coupled transistors in response to different values of an input voltage received by the charge pump converter instead of a value of the output voltage to form a charging current to charge the flying capacitor during a charging period of the charge pump converter.

16. The method of claim 15, further comprising: configuring the first circuit to selectively enable different transistors of a second plurality of parallel coupled transistors in response to different values of the input voltage but not the value of the output voltage to form a discharge current charging the output capacitor from the flying capacitor during a discharge period of the charge pump converter.

17. The method of claim 15, wherein configuring the first circuit to selectively enable different transistors of the first plurality of parallel-coupled transistors comprises: the first circuit is configured to form a plurality of sense signals and compare each sense signal to a reference signal to form a plurality of control signals, each sense signal representing a different value of the input voltage.

18. The method of claim 15, further comprising: configuring a second circuit to selectively enable different transistors of a second plurality of parallel coupled transistors in response to a difference between different values of the input voltage and the output voltage to form a charging current to charge the flying capacitor during the charging period.

19. The method as recited in claim 18, further comprising: configuring the second circuit to selectively enable different transistors of a third plurality of parallel coupled transistors in response to a difference between different values of the input voltage and the output voltage to form a discharge current that charges the output capacitor from the flying capacitor during a discharge period of the charge pump converter.