HK1140584A - Charge pump controller and method therefor - Google Patents

Description

Charge pump controller and method thereof

Technical Field

The present invention relates generally to electronics, and more particularly to methods and structures for forming semiconductor devices.

In the past, the semiconductor industry utilized various methods and structures to form charge pump controllers for providing an output voltage from an input voltage source, such as a battery. Generally, a charge pump controller is used to charge a plurality of capacitors from an input voltage and couple the capacitors to provide current to a load. Existing charge pump controllers typically form two time intervals, one time interval for charging the capacitor and a second time interval for discharging the capacitor. One such charge pump controller is disclosed in U.S. patent No. 6,198,645 issued to Kotowski et al on 3/6/2001. Due to the manner in which capacitors are charged and discharged, there is typically a high inrush current when the capacitors are charged and there is a ripple on the output voltage that is produced when the capacitors are discharged.

Accordingly, a charge pump controller that reduces inrush current and reduces ripple in the output voltage is desired.

Drawings

Fig. 1 schematically illustrates an embodiment of a portion of a charge pump power supply system including an exemplary embodiment of a charge pump controller according to the present invention;

FIG. 2 is a graph having plots that illustrate some of the signals of the charge pump controller of FIG. 1 in accordance with the present invention; and

fig. 3 schematically illustrates an enlarged plan view of a semiconductor device including the charge pump controller of fig. 1 in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, a current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor, or a collector or emitter of a bipolar transistor, or a cathode or anode of a diode; and a control electrode represents an element of the device that controls the current through the device, the control electrode being, for example, the gate of a MOS transistor or the base of a bipolar transistor. Although these devices are explained herein as certain N-channel or P-channel devices, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. Those skilled in the art will recognize that the word "during.. at the same time, when.. is used" is not an exact term to indicate that an action will occur as soon as there is a start-up action, but rather that there may be some slight but reasonable delay, such as a propagation delay, between the reactions provoked by the initial action.

Detailed Description

Fig. 1 schematically illustrates an embodiment of a portion of a charge pump power supply system 10 that includes an exemplary embodiment of a charge pump controller 20. The system 10 receives power from a DC voltage source, such as a battery 11, between a voltage input terminal 12 and a voltage return terminal 13, and forms an output voltage that is provided to a load, such as a Light Emitting Diode (LED)14, and a load current 18. Load current 18 is also used to charge output capacitor 15, and output capacitor 15 is used to help maintain the output voltage at a desired voltage value. A portion of load current 18 flows through LED14 as LED current 19.

Charge pump controller 20 receives an input voltage between a voltage input 21 and a voltage return 22 and provides an output voltage on an output 23 of controller 20. Input 21 is commonly connected to terminal 12 and return 22 is commonly connected to terminal 13. As will be seen further hereinafter, controller 20 is configured to charge a plurality of charge pump capacitors or pump capacitors, such as pump capacitors 16 and 17, during a charging time interval, and to sequentially couple capacitor 16 followed by capacitor 17 to provide current 18 during a plurality of discharging time intervals that occur sequentially or consecutively. The controller 20 includes a clock generator circuit or clock generator 33, a switch control circuit 40, a mode control circuit or mode controller 32, and a current source 31. The generator 33 or the circuit 40 together with the generator 33 may be regarded as a control circuit. Current source 31 is configured to receive current 19 from LED14 through Current Source (CS) input 24 and form a Feedback (FB) signal that is indicative of the state of current 19. If the value of current 19 is not less than the desired threshold level, the FB signal is low to indicate that the value of current 19 is not less than the desired minimum value. If the value of current 19 falls below the desired threshold level, the FB signal goes high to indicate that current 19 is below the desired value of current 19. As an alternative to using current source 31 to form the FB signal, a current sense resistor may be placed in series with input 24 to receive current 19, and the resulting voltage may be compared to a reference signal. For the exemplary embodiment shown in FIG. 1, the mode controller 32 receives the FB signal and provides two mode control signals (M1 and M2) that are used to determine the operating mode of the controller 20. The controller 20 controls the charge pump capacitors 16 and 17 in response to the mode control signals M1 and M2, which allows the controller 20 to operate in one of three different modes. The three modes of operation are commonly referred to as 1X mode, 1.5X mode, and 2X mode. For 1X mode, controller 20 couples the input voltage from input 21 directly to output 23. In the 1.5X mode, controller 20 forms an output voltage that is approximately 1.5 times the value of the voltage received on input 21. In the 2X mode, controller 20 forms an output voltage that is approximately 2 times the value of the input voltage received on input 21.

To facilitate charging and discharging capacitors 16 and 17, switch control circuit 40 includes a plurality of inverters and a plurality of switches implemented as transistors for configuring capacitors 16 and 17 to be charged and for configuring capacitors 16 and 17 to help provide current 18. Circuit 40 includes inverters 55, 56, 57, 58, and 59, and further includes transistors 41, 42, 43, 44, 45, 46, 47, 50, 51, and 52. Clock generator 33 generates a plurality of timing signals for controlling the state of the switches of circuit 40.

Fig. 2 is a graph having plots that illustrate some of the signals formed during operation of the controller 20. The abscissa represents time and the ordinate represents increasing values of the shown signal. Curves 65 and 66 show the control signals M1 and M2, respectively, generated by the controller 32. This description refers to fig. 1 and 2. Curve 67 shows the state of the 1X control signal developed by generator 33. Curves 68 and 69 show the states of the first charge clock (C1) signal and the second charge clock (C2) control signal formed by the generator 33. Curves 70, 71 and 72 show the state of the low side control signals S1, S2 and S3 generated by the generator 33. Curves 73 and 74 show the states of the sequential discharge control signals D1 and D2 formed by the clock generator 33. The discharge control signals D1 and D2 are normally inactive for the entire time of the charging interval during which the capacitors 16 and 17 are charged. After the charging time interval, the controller 20 forms a plurality of discharging time intervals to generate the discharging control signals D1 and D2 in a continuous manner. During a first discharge time interval, the signal D1 is active and the signal D2 is inactive, and during a second discharge time interval after the first discharge time interval, the signal D2 is active and the signal D1 is inactive.

For the purposes of describing the operation of controller 20, it is assumed that at time T0, battery 11 is fully charged and the value of current 19 through LED14 is not less than a desired value and is sufficient to maintain the voltage of capacitor 15 substantially equal to the voltage of battery 11. Current 19 flowing through Current Sense (CS) input 24 causes the Feedback (FB) signal to be low. The mode controller 32 receives the low Feedback (FB) signal and responsively forces the M1 control signal high and the M2 control signal low, which signals the clock generator 33 to operate in the 1X mode. In the 1X mode, generator 33 forces the 1X control signal high, forcing the output of inverter 55 low and enabling transistor 47. Enabling transistor 47 couples the voltage from input 21 to output 23 such that the output voltage is substantially equal to the value of the voltage from battery 11 minus a small loss (e.g., a small loss through transistor 47). In the 1X mode of operation, clock generator 33 forces the C1, C2, S1, S2, S3, D1, and D2 control signals low, thereby disabling the respective transistors 43, 44, 42, 41, 50, 45, and 46. Thus, in 1X mode, generator 33 does not switch charge pump capacitors 16 and 17 that will charge or provide current 18 from battery 11.

Assume that at time T1 the value of current 19 decreases to a value less than the threshold value, which forces the FB signal high. Controller 32 receives a high FB signal indicating that controller 20 needs to increase the value of the output voltage on output 23 in order to provide the desired value of current 19, and therefore, controller 32 forces the M1 and M2 signals low for controller 20 to operate in the 1.5X mode. In the 1.5X mode, clock generator 33 is configured to form a charging time interval during which capacitors 16 and 17 are connected in series, with the series combination thereof connected in parallel with battery 11, so that capacitors 16 and 17 are each charged to a voltage value of about half the voltage from battery 11. During this charging time interval between times T1 and T2, the controller 33 forces the 1X control signal low, the C1 control signal high, the C2 control signal low, the S1 control signal high, the S2 control signal low, and the S3 control signal high. The discharge control signals D1 and D2 are generally always low during the charging interval. The high C1 control signal and the low C2 control signal enable transistor 43 and disable transistor 44. The low S2 control signal disables transistor 41 and the high S1 and S3 control signals enable transistors 42 and 50. Because both the discharge control signals D1 and D2 are low, transistors 45, 46, 51, and 52 are disabled. Since transistors 42, 43, and 50 are enabled, the input voltage from input 21 is coupled to capacitor terminal 30 through transistor 43, capacitor terminal 29 is coupled to capacitor terminal 28 through transistor 50, and capacitor terminal 27 is coupled to return 22 through transistor 42. Thus, capacitors 16 and 17 are each charged to a voltage that is approximately half the voltage from battery 11. The time for the charging time interval between T1 and T2 is selected to be long enough to ensure that capacitors 16 and 17 receive sufficient charge to provide current 19 and maintain capacitor 15 charged. After the charging time interval ends at time T2, generator 33 sequentially forms a number of discharge time intervals such that the number of discharge time intervals is equal to the number of pump capacitors charged by controller 20. For the exemplary embodiment shown in fig. 1, generator 32 forms two discharge time intervals, one for each of capacitors 16 and 17. During the first discharge time interval, the signal D1 is active and the signal D2 is inactive, while during the second discharge time interval, the signal D2 is active and the signal D1 is inactive. Thus, the generator 33 sequentially forms two discharge time intervals defined by one of the active discharge control signals D1 or D2. During the first discharge time interval after time T2 to time T3, all control signals are low except for signal D1. Those skilled in the art will recognize that there is typically a small amount of time (often referred to as a dead time) between the end of time T2 and the beginning of the first discharge interval to allow the transistor to be completely disabled before enabling the transistor controlled by signal D1. The high D1 control signal forces the output of inverter 59 low, thereby enabling transistors 46 and 52. Enable transistor 46 couples input 21 to capacitor terminal 27 and enable transistor 52 couples capacitor terminal 28 to output 23, so that the voltage from battery 11 is added to the voltage of capacitor 16, thereby providing an output voltage on output 23 that is substantially 1.5 times the value of the voltage on battery 11. When the first discharge interval terminates at approximately time T3, generator 33 sequentially forms subsequent discharge intervals by asserting control signal D2 and deasserting control signal D1. Those skilled in the art recognize that there is typically a dead time after signal D1 is deactivated and before signal D2 is activated. The high D2 signal forces the output of inverter 58 low, thereby enabling transistors 45 and 51. Transistor 45 couples the voltage from input 21 to capacitor terminal 29 and enabling transistor 51 couples capacitor terminal 30 to output 23, thereby forming an output voltage substantially 1.5 times the value of the voltage on battery 11. After the second discharge time interval has expired at about time T4, the controller 20 generally begins another charge time interval, such as the time interval beginning at time T1. Generally, controller 20 continues to operate in the 1.5X mode as long as the value of current 19 remains above the threshold.

Assume that the FB signal is again low and that just after time T4, current 19 decreases to a value less than the threshold, forcing the FB signal high again. Mode controller 32 receives a high FB signal indicating that controller 20 needs to increase the value of the output voltage on output 23 in order to provide the desired value of current 19, therefore, controller 32 forces the M1 low and the M2 signal high for controller 20 to operate in the 2X mode. In the 2X mode, clock generator 33 is configured to form a charging time interval during which capacitors 16 and 17 are connected in parallel and the parallel combination is connected in parallel with battery 11 so that capacitors 16 and 17 are each charged to a voltage value approximately equal to the voltage from battery 11. After time T4 and during the charging interval up to time T5, controller 33 forces the 1X control signal low, the C1 and C2 control signals high, the S1 and S2 control signals high, and the S3 control signal low. The discharge control signals D1 and D2 are generally always low during this charging interval. The high C1 and C2 signals enable transistors 43 and 44. The high S1 and S2 signals enable transistors 41 and 42, while the low S3 signal disables transistor 50. Because both the discharge control signals D1 and D2 are low, transistors 45, 46, 51, and 52 are disabled. Since transistors 41, 42, 43, and 44 are enabled, the input voltage from input 21 is coupled to capacitor terminal 30 through transistor 43, and capacitor terminal 29 is coupled to return 22 through transistor 41. Transistor 44 couples the input voltage from input 21 to capacitor terminal 28, and capacitor terminal 27 is coupled to return 22 through transistor 42. Thus, capacitors 16 and 17 are each charged to a voltage approximately equal to the voltage from battery 11. The time for the charging time interval is selected to be long enough to ensure that capacitors 16 and 17 receive sufficient charge to provide current 19 and maintain capacitor 15 charged. After the charging time interval ends at time T5, generator 33 sequentially forms a number of discharge time intervals such that the number of discharge time intervals is equal to the number of pump capacitors charged by controller 20. For the exemplary embodiment shown in fig. 1, generator 32 forms two discharge time intervals, one for each of capacitors 16 and 17. During the first discharge time interval, the discharge control signal D1 is active and the signal D2 is inactive, while during the second discharge time interval, the signal D2 is active and the signal D1 is inactive. Thus, generator 33 again sequentially forms two discharge time intervals defined by one of the active discharge control signals D1 or D2. During the first discharge time interval after time T5 to time T6, all control signals are low except for signal D1. Those skilled in the art will recognize that there is generally a dead time between the end of time T5 and the beginning of the first discharge time interval. The high D1 control signal forces the output of inverter 59 low, thereby enabling transistors 46 and 52. Enable transistor 46 couples input 21 to capacitor terminal 27 and enable transistor 52 couples capacitor terminal 28 to output 23, so that the voltage from battery 11 is added to the voltage of capacitor 16, thereby providing an output voltage on output 23 that is substantially 2 times the value of the voltage on battery 11. When the first discharge interval terminates at approximately time T6, generator 33 sequentially forms a subsequent second discharge interval by deactivating control signal D1 and activating control signal D2 after the dead time. The high D2 signal forces the output of inverter 58 low, thereby enabling transistors 45 and 51. Transistor 45 couples the voltage from input 21 to capacitor terminal 29 and enabling transistor 51 couples capacitor terminal 30 to output 23, thereby forming an output voltage substantially 2 times the value of the voltage on battery 11. After the second discharge time interval has expired at about time T7, the controller 20 typically begins another charging time interval, such as a time interval beginning at about time T4. Generally, controller 20 continues to operate in the 2X mode as long as the value of current 19 remains above the threshold. In general, other circuitry not shown helps to develop signals that help to switch the controller 20 back to 1X or 1.5X mode.

To facilitate this function of controller 20, input 24 is connected to one terminal of current source 31. The FB output of source 31 is connected to an input of controller 32. The M1 control signal from the controller 32 is connected to a first input of the generator 32, and the M2 signal from the controller 32 is connected to a second input of the generator 32. The 1X output of generator 33 is connected to the input of inverter 55, inverter 55 having an output connected to the gate of transistor 47. The C1 output of generator 33 is connected to the input of inverter 56, inverter 56 having an output connected to the gate of transistor 43. The C2 output of generator 33 is connected to the input of inverter 57, inverter 57 having an output connected to the gate of transistor 44. The S1 output of generator 33 is connected to the gate of transistor 42. The S2 output of generator 33 is connected to the gate of transistor 41. The S3 output of generator 33 is connected to the gate of transistor 50. The D1 output of generator 33 is connected to the input of inverter 59, inverter 59 having an output commonly connected to the gate of transistor 46 and the gate of transistor 52. The D2 output of generator 33 is connected to the input of inverter 58, inverter 58 having an output commonly connected to the gate of transistor 45 and the gate of transistor 51. Input 21 is commonly connected to a source of transistor 47, a source of transistor 46, a source of transistor 45, a source of transistor 44, and a source of transistor 43. A drain of transistor 47 is commonly connected to output 23, a drain of transistor 51, and a drain of transistor 52. A drain of transistor 46 is commonly connected to terminal 27 and a drain of transistor 42. A drain of transistor 45 is commonly connected to terminal 29, a source of transistor 50, and a drain of transistor 41. A drain of transistor 44 is commonly connected to terminal 28, a drain of transistor 50, and a source of transistor 52. A drain of transistor 43 is commonly connected to terminal 30 and a source of transistor 51. A source of transistor 41 is commonly connected to a source of transistor 42, a second terminal of current source 31, and return 22.

Fig. 3 schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 80 that is formed on a semiconductor die 81. Controller 20 is formed on die 81. Die 81 may also include other circuits that are not shown in fig. 3 for simplicity of the drawing. Controller 20 and device or integrated circuit 80 are formed on die 81 by semiconductor fabrication techniques that are well known to those skilled in the art.

In view of all of the above, it is evident that a new device and method is disclosed. Included, among other features, is forming a charge pump controller to charge a plurality of pump capacitors during a charging time interval and sequentially form a plurality of discharging time intervals, a different pump capacitor being coupled to provide current to a load for each discharging time interval.

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. More specifically, the subject matter of the present invention is described with respect to a particular embodiment using two pump capacitors, however, the present technique is applicable to use with more than two pump capacitors. The number of sequential discharge time intervals is typically selected to be the same as the number of capacitors that are charged during the charging time interval.

Claims (16)

1. A charge pump controller comprising:

a plurality of terminals configured to be coupled to a plurality of pump capacitors;

an output configured to provide a load current to a load; and

a control circuit configured to form a charging time interval for charging a first pump capacitor of the plurality of pump capacitors and to sequentially form a plurality of discharging time intervals for sequentially coupling the plurality of pump capacitors to provide current to the output.

2. The charge pump controller of claim 1 wherein the control circuit sequentially forms the plurality of discharge time intervals after forming the charge time interval.

3. The charge pump controller of claim 1 wherein the control circuit sequentially forms the plurality of discharge time intervals before forming another charge time interval.

4. The charge pump controller of claim 1, wherein the charge pump controller is configured to connect at least two pump capacitors of the plurality of pump capacitors in parallel during the charging time interval to charge the at least two pump capacitors to a first voltage, and to sequentially select a pump capacitor from the at least two pump capacitors to provide current to the output corresponding to each sequential discharging time interval of the plurality of discharging time intervals.

5. The charge pump controller of claim 1, wherein the charge pump controller is configured to connect at least two pump capacitors of the plurality of pump capacitors in parallel during the charging time interval to charge the at least two pump capacitors to a first voltage and to sequentially select a first pump capacitor of the at least two pump capacitors to provide current to the output corresponding to a first discharging time interval of the plurality of discharging time intervals and to sequentially select a second pump capacitor of the at least two pump capacitors to provide current to the output corresponding to a second discharging time interval of the plurality of discharging time intervals.

6. The charge pump controller of claim 1, wherein the charge pump controller is configured to connect the plurality of pump capacitors in series during the charging time interval to charge each charge pump capacitor to a first voltage, and to sequentially select a different pump capacitor from the plurality of capacitors to provide current to the output corresponding to each sequential discharging time interval of the plurality of discharging time intervals.

7. The charge pump controller of claim 1, wherein the charge pump controller is configured to connect at least two pump capacitors of the plurality of pump capacitors in series during the charging time interval to charge the at least two pump capacitors to a first voltage, and to sequentially select a first pump capacitor of the at least two pump capacitors to provide current to the output corresponding to a first discharging time interval of the plurality of discharging time intervals, and to sequentially select a second pump capacitor of the at least two pump capacitors to provide current to the output corresponding to a second discharging time interval of the plurality of discharging time intervals.

8. The charge pump controller of claim 1 wherein a number of discharge time intervals of the plurality of discharge time intervals is no greater than a number of pump capacitors of the plurality of pump capacitors.

9. The charge pump controller of claim 1 wherein the control circuit asserts a plurality of control signals during the charging time interval, the control circuit sequentially asserting a single discharge control signal for each of the plurality of discharge time intervals.

10. A method of forming a charge pump controller, comprising:

configuring the charge pump controller to charge a plurality of pump capacitors to a first voltage during a charging time interval; and

configuring the charge pump controller to sequentially couple each of the plurality of pump capacitors to provide current to a load.

11. The method of claim 10, wherein the step of configuring the charge pump controller to charge a plurality of pump capacitors comprises: the charge pump controller is configured to connect two charge pump capacitors in parallel to charge the two pump capacitors.

12. The method of claim 11, wherein the step of configuring the charge pump controller to sequentially couple each pump capacitor comprises: configuring the charge pump controller to couple a first of the two charge pump capacitors to provide current to the load while not coupling a second of the two charge pump capacitors to provide current to the load, then sequentially coupling the second of the two charge pump capacitors to provide current to the load while not coupling the first of the two charge pump capacitors to provide current to the load.

13. The method of claim 10, wherein the step of configuring the charge pump controller to charge a plurality of pump capacitors comprises: configuring the charge pump controller to connect two charge pump capacitors in series to charge the two pump capacitors.

14. The method of claim 13, wherein the step of configuring the charge pump controller to sequentially couple each pump capacitor comprises: configuring the charge pump controller to couple a first charge pump capacitor of the two charge pump capacitors to provide current to the load while not coupling a second charge pump capacitor of the two charge pump capacitors to provide current to the load, then sequentially coupling the second charge pump capacitor of the two charge pump capacitors to provide current to the load while not coupling the first charge pump capacitor of the two charge pump capacitors to provide current to the load.

15. The method of claim 10, wherein the step of configuring the charge pump controller to sequentially couple each of the plurality of pump capacitors to provide current to a load comprises: configuring the charge pump controller to sequentially couple each pump capacitor of the plurality of pump capacitors to provide current after the charging time interval and before forming another charging time interval.

16. The method of claim 10, wherein the step of configuring the charge pump controller to sequentially couple each of the plurality of pump capacitors to provide current to a load comprises: configuring the charge pump controller to form a plurality of discharge time intervals, and coupling a different one of the plurality of pump capacitors to an output of the charge pump controller corresponding to each of the plurality of discharge time intervals.