HK1142192B - Method and apparatus rate matching with multiple code block sizes - Google Patents

Description

Method and apparatus for rate matching with multiple code block sizes

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority from U.S. provisional patent application No.60/943,545 entitled "METHODS and application programs FOR RATE MATCHING WITH multi CODE BLOCK and CODE BLOCK SIZES" filed on 12.6.2007. The present application claims priority from U.S. provisional patent application No.60/944,579 entitled "METHODS and METHODS CODE FOR RATE MATCHING WITH MULTIPLE CODE BLOCK and CODE BLOCK SIZES" filed on 18.6.2007. The present application also claims priority from U.S. provisional patent application No.60/956,101 entitled "METHOD AND DAPPARATUSES FOR RATE MATCHING WITH MULTIPLE CODE BLOCKS AND CODE BLOCK SIZES" filed on 8/15 of 2007.

Technical Field

The following description relates generally to wireless communications, and more particularly to transmitting data using circular buffer (circular buffer) based rate matching in a wireless communication system.

Background

Wireless communication systems are widely deployed to provide various types of communication; voice and/or data may be provided, for example, over such wireless communication systems. A typical wireless communication system or network may provide multi-user access to one or more shared resources, such as bandwidth, transmission power … …. For example, the system may use various multiple access techniques such as Frequency Division Multiplexing (FDM), Time Division Multiplexing (TDM), Code Division Multiplexing (CDM), Orthogonal Frequency Division Multiplexing (OFDM), and so on.

In general, a wireless multiple-access communication system can simultaneously support communication for multiple access terminals. Each access terminal may communicate with one or more base stations via transmissions on forward and reverse links. The forward link (or downlink) refers to the communication link from base stations to access terminals, and the reverse link (or uplink) refers to the communication link from access terminals to base stations. The communication link may be established via a single-input single-output system, a multiple-input single-output system, or a multiple-input multiple-output (MIMO) system.

Wireless communication systems often utilize one or more base stations that provide a coverage area. A typical base station can transmit multiple data streams for broadcast, multicast, and/or unicast services, wherein a data stream is a stream of data that can be of independent reception interest to an access terminal. An access terminal within the coverage area of that base station can be employed to receive one, more than one, or all the data streams conveyed by the composite stream. Similarly, an access terminal can transmit data to a base station or another access terminal.

Recently, Turbo codes, which are a high performance error correcting code, have been developed to improve data transmission over limited bandwidth communication links in the presence of data corrupting noise. Any wireless communication device (e.g., base station, access terminal … …) can utilize a Turbo code to encode data to be transmitted by the corresponding wireless communication device. The Turbo code encoder may combine parity bits with systematic bits (e.g., payload data … …), which increases the total number of bits to be transmitted by the wireless communication device (e.g., if X bits are input to the Turbo code encoder, then about 3X bits are output from the Turbo code encoder).

However, the total number of coded bits output from the Turbo code encoder to be transmitted over the channel may differ from the number of bits that the wireless communication device is capable of transmitting over the channel (e.g., the number of bits that the wireless communication device is capable of transmitting may depend on the allocation, the wireless communication device, and/or the properties or characteristics … … of the wireless communication environment as a whole). For example, the wireless communication device may not be able to transmit all of the coded bits because the number of coded bits may exceed the number of bits that the wireless communication device is able to transmit on the channel. By way of another example, the number of coded bits can be less than the number of bits that the wireless communication device is capable of transmitting on the channel. Thus, rate matching may be performed to vary the number of coded bits to be transmitted over a channel to match the number of bits that the wireless communication device is able to transmit over the channel; more specifically, rate matching may puncture (e.g., delete bits) bits to reduce the rate (e.g., when the number of coded bits is greater than the number of bits that can be transmitted over the channel) or repeat bits to increase the rate (e.g., when the number of coded bits is less than the number of bits that can be transmitted over the channel). By way of example, when the number of coded bits is approximately 3X bits (e.g., based on X bits being input into a Turbo code encoder), and these approximately 3X bits exceed the number of bits that can be transmitted over the channel, then less than 3X bits can be transmitted from the wireless communication device with rate matching performed. However, conventional rate matching techniques (e.g., such as rate matching in R99, R5, R6 … …) can be complex and are designed primarily for transport channel multiplexing. For example, these commonly used rate matching techniques may include several complex stages of puncturing or repetition and bit collection algorithms, which may be further complicated by the fact that a single transport block may be segmented into code blocks of different sizes in a particular operating environment.

Disclosure of Invention

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

In accordance with one or more embodiments and corresponding disclosure thereof, various schemes are described in connection with circular buffer-based rate matching in the case of transport blocks having code blocks of different sizes. The bits of each code block included in a transport block may be stored to an associated circular buffer and transmitted through a channel. The size of each circular buffer may vary in proportion to the size of the associated code block. Thus, since the size of the code blocks for a transport block may vary in a particular operating environment, the size of the circular buffer may also vary. Thus, when all data from a transport block and/or an array of circular buffers cannot be transmitted over a channel, each circular buffer in the array may transmit a portion of bits that is proportional to the size of the corresponding circular buffer (or associated code block or encoded code block). Furthermore, the number of bits transmitted from each circular buffer may be constrained by the aggregate budget for all circular buffers, and may also be constrained by integer multiples of the modulation order for the transport block.

According to a related aspect, a method for rate matching in a wireless communication environment is described herein. The method may include populating each circular buffer in the circular buffer array with bits from an associated code block in a set of code blocks that make up a transport block. Further, the method may include obtaining a transmission budget that defines a total number of bits to be transmitted from all circular buffers in the array. Further, the method may include calculating, for each circular buffer in the array, a corresponding buffer budget defining a number of bits to be transmitted from the associated circular buffer, the corresponding buffer budget occupying a portion of the transmission budget and being proportional to a size of the associated circular buffer. Additionally, the method may further include limiting the corresponding buffer budget to an integer multiple of a number of bits described by a modulation level of the transport block.

Another aspect relates to a wireless communications apparatus. The wireless communications apparatus can include a memory that retains instructions related to: for each code block of a set of code blocks that make up a transport block, storing bits from the code block into an associated circular buffer; obtaining a transmission budget defining a total number of bits to be transmitted from all circular buffers; and determining a corresponding buffer budget describing a number of bits to be transmitted from the associated circular buffer, the corresponding buffer budget occupying a portion of the transmission budget and being a function of a size of the associated circular buffer. Further, the wireless communications apparatus can include a processor coupled to the memory and configured to execute the instructions retained in the memory.

Yet another aspect relates to a wireless communications apparatus that enables employing rate matching in a wireless communication environment. The wireless communications apparatus can include means for padding data from an associated code block of a transport block into a circular buffer. Further, the wireless communications apparatus can include means for defining a total amount of data to transmit for the transport block. Further, the wireless communications apparatus can include means for calculating an amount of data transmitted from the circular buffer based on a size of the circular buffer relative to other circular buffers.

Yet another aspect relates to a machine-readable medium comprising machine-executable instructions stored thereon to: associating each code block of the transport block with one circular buffer in the circular buffer array; filling a circular buffer in the circular buffer array with bits from an associated circular buffer; determining a transmission budget defining a total number of bits to be transmitted from all circular buffers in the array; and calculating for each circular buffer in the array a buffer budget defining a number of bits transmitted recursively from that circular buffer, the buffer budget occupying a portion of the transmission budget and being proportional to the size of that circular buffer.

According to another aspect, an apparatus in a wireless communication system may include a processor, where the processor may be configured to store information included in code blocks to an associated circular buffer for each code block of a transport block. Further, the processor can configure a transmission budget that defines a total number of bits to be transmitted from all code blocks. Further, the processor can be configured to determine a block budget that defines a number of bits to transmit from the code block, the block budget occupying a portion of the transmission budget and being a function of a size of the code block relative to other code blocks in the transmission block.

To the accomplishment of the foregoing and related ends, the one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the described embodiments are intended to include all such aspects and their equivalents.

Drawings

Fig. 1 is an illustration of a wireless communication system in accordance with various aspects set forth herein.

Fig. 2 is an illustration of an example system that performs rate matching utilizing a circular buffer based algorithm in a wireless communication system.

Fig. 3 is an illustration of an exemplary schematic diagram of using a circular buffer based rate matching algorithm.

Fig. 4 is an illustration of an example methodology that facilitates rate matching in a wireless communication environment.

Fig. 5 is an illustration of an example methodology that facilitates preferentially processing systematic bits in connection with circular buffer based rate matching in a wireless communication environment.

Fig. 6 is an illustration of an example methodology that facilitates employing rate matching utilizing a circular buffer in a wireless communication environment.

Fig. 7 is an illustration of an example methodology that facilitates employing rate matching in a wireless communication environment where a transport block has a plurality of code block sizes.

Fig. 8 is an illustration of an example access terminal that performs circular buffer based rate matching in a wireless communication system.

Fig. 9 is an illustration of an example system that facilitates performing circular buffer based rate matching in a wireless communication environment.

Fig. 10 is an illustration of an example wireless network environment that can be employed in conjunction with the various systems and methods described herein.

Fig. 11 is an illustration of an example system that enables employing rate matching in a wireless communication environment.

Detailed Description

Various embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that such embodiment(s) may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

As used in this application, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to: a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).

Moreover, various embodiments are described herein in connection with an access terminal. An access terminal can also be called a system, subscriber unit, subscriber station, mobile, remote station, remote terminal, mobile device, user terminal, wireless communication device, user agent, user device, or User Equipment (UE). An access terminal may be a cellular telephone, a cordless telephone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device having wireless connection capability, a computing device, or other processing device connected to a wireless modem. Moreover, various embodiments are described herein in connection with a base station. A base station may be utilized for communicating with access terminal(s) and may also be referred to as an access point, node B, eNodeB, or some other terminology.

Moreover, various aspects or features described herein may be implemented as a method, apparatus, article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips, etc.), optical disks (e.g., Compact Disk (CD), Digital Versatile Disk (DVD), etc.), smart cards, and flash memory devices (e.g., EPROM, card, stick, key drive, etc.). In addition, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, but is not limited to: wireless channels and various other media capable of storing, containing, and/or carrying instruction(s) and/or data.

Referring now to fig. 1, a wireless communication system 100 is illustrated in accordance with various embodiments presented herein. System 100 comprises a base station 102 that can include multiple antenna groups. For example, one antenna group can include antennas 104 and 106, another group can include antennas 108 and 110, and an additional group can include antennas 112 and 114. Although only two antennas are shown for each antenna group, more or fewer antennas may be utilized for each antenna group. Base station 102 can additionally include a transmitter chain and a receiver chain, each of which can in turn comprise a plurality of components associated with signal transmission and reception (e.g., processors, modulators, multiplexers, demodulators, demultiplexers, antennas, etc.), as will be appreciated by one skilled in the art.

Base station 102 may communicate with one or more access terminals, such as access terminal 116 and access terminal 122; however, it is to be appreciated that base station 102 can communicate with substantially any number of access terminals similar to access terminals 116 and 122. Access terminals 116 and 122 can be, for example, cellular phones, smart phones, laptops, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other suitable device for communicating over wireless communication system 100. As shown, access terminal 116 can be in communication with antennas 112 and 114, where antennas 112 and 114 transmit information to access terminal 116 over forward link 118 and receive information from access terminal 116 over reverse link 120. In addition, access terminal 122 can be in communication with antennas 104 and 106, where antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 over reverse link 126. In a Frequency Division Duplex (FDD) system, forward link 118 can utilize a different frequency band than that used by reverse link 120, and forward link 124 can employ a different frequency band than that employed by reverse link 126, for example. Further, in a Time Division Duplex (TDD) system, forward link 118 and reverse link 120 can utilize a common frequency band and forward link 124 and reverse link 126 can utilize a common frequency band.

Each group of antennas and/or the area in which they are designated to communicate can be referred to as a sector of base station 102. For example, antenna groups can be designed to communicate to access terminals in a sector of the areas covered by base station 102. In communication over forward links 118 and 124, the transmitting antennas of base station 102 can utilize beamforming in order to improve signal-to-noise ratio of forward links 118 and 124 for access terminals 116 and 122. Moreover, while base station 102 utilizes beamforming to transmit to access terminals 116 and 122 scattered randomly through an associated coverage, access terminals in neighboring cells can be subject to less interference as compared to a base station transmitting through a single antenna to all its access terminals.

Base station 102, access terminal 116, and/or access terminal 122 can be a transmitting wireless communication device and/or a receiving wireless communication device at a given time. When transmitting data, the transmitting wireless communication device may encode the data for transmission. More specifically, a transmitting wireless communication device may have (e.g., generated, obtained, stored in memory, … …) a particular number of information bits to send over a channel to a receiving communication device. These information bits may be included in a transport block (or multiple transport blocks) of data, which may be partitioned to produce multiple code blocks. Further, the transmitting wireless communication device can encode each code block using a Turbo code encoder (not shown). The Turbo code encoder may output encoded code blocks for each code block input thereto. The encoded code blocks output by the Turbo code encoder may each include three elements: systematic bits, parity 1 bits, and parity 2 bits.

The transmitting wireless communication device may use a circular buffer-based rate matching algorithm that allows for simplification compared to conventional techniques (e.g., even in the presence of multiple code blocks and transport blocks). More specifically, circular buffer-based rate matching can be achieved by having the transmitting wireless communication device collect systematic bits of all encoded code blocks generated from a transport block. In addition, the collected systematic bits can be interleaved (interleave) together to produce a first set of bits for transmission over the channel. In addition, parity 1 bits and parity 2 bits of all encoded code blocks generated from the transport block may be collected. After collection, the parity 1 bits may be interleaved together. Further, after collection, the parity 2 bits may be interleaved together. Thereafter, the interleaved parity 1 bits and the interleaved parity 2 bits may be interleaved (interlace) together in an alternating manner to generate a second set of bits for transmission over the channel. The first and second sets of bits may be mapped to surround the circular buffer; however, claimed subject matter is not so limited, and contemplates using any type of mapping. The transmitting wireless communication device may then transmit bits from the first group (e.g., systematic bits) over the channel. After transmission of the first set of bits, the transmitting wireless communication device may transmit bits from the second set over the channel.

By separating the systematic bits from the parity 1 bits and the parity 2 bits, circular buffer based rate matching allows the systematic bits to be transmitted before the parity bits. Thus, under high code rate conditions where a large number of systematic bits are to be transmitted in a given time period, the circular buffer based rate matching may achieve improved performance compared to conventional techniques (e.g., R99 rate matching, R5 rate matching, R6 rate matching … …), while under low code rate conditions, the circular buffer based rate matching may have similar performance to conventional rate matching techniques. More specifically, under high code rate conditions, a transmitting wireless communication device may not be able to transmit all of the bits of an encoded code block. Thus, puncturing (e.g., deleting) of bits may be performed for rate matching purposes in order to reduce the number of bits that are communicated. In conjunction with bit puncturing, a transmitting wireless communication device preferentially selects systematic bits for transmission; thus, all systematic bits from the encoded code block are transmitted over the channel if possible, and a subset of parity 1 bits and parity 2 bits may be transmitted over the channel if other bits can be transmitted. Furthermore, when a low code rate is utilized, all systematic bits and all parity 1 bits and parity 2 bits from the encoded code block may be transmitted over the channel.

Turning now to fig. 2, illustrated is a system 200 that facilitates rate matching utilizing a circular buffer based algorithm in a wireless communication environment. System 200 includes a wireless communication device 202 that is shown to transmit data over a channel. Although depicted as sending data, the wireless communication device 202 can also receive data over the channel (e.g., the wireless communication device 202 can transmit and receive data simultaneously, the wireless communication device 202 can transmit and receive data at different times, or a combination thereof … …). For example, the wireless communication apparatus 202 can be a base station (e.g., the base station 102 … … of fig. 1), an access terminal (e.g., the access terminal 116 of fig. 1, the access terminal 122 … … of fig. 1), and/or the like.

Wireless communication apparatus 202 can include a Turbo code encoder 204 (e.g., encoder … …) that encodes data to be transmitted from wireless communication apparatus 202. Turbo code encoder 204 utilizes high performance error correction codes to optimize information transfer over a limited bandwidth connection link in the presence of data corruption noise. The input to Turbo code encoder 204 may be one or more code blocks. For example, a transport block may be partitioned into M code blocks (e.g., code block 0, code block 1 … …, code block M-1), where M may be substantially any integer, and these M code blocks may be used as inputs to Turbo code encoder 204. Turbo code encoder 204 may output M encoded code blocks (e.g., encoded code block 0, encoded code block 1 … …, encoded code block M-1) from the input M code blocks. Further, each of the M encoded code blocks output by the Turbo code encoder 204 may correspond to one of the respectively input M code blocks (e.g., encoded code block 0 may be generated from code block 0, encoded code block 1 … … may be generated from code block 1, and encoded code block M-1 may be generated from code block M-1).

The M encoded code blocks output by Turbo code encoder 204 may each include three elements: systematic bits, parity 1 bits, and parity 2 bits. An example is provided below for one of the M encoded code blocks, it being appreciated that the other encoded code blocks are substantially similar. The systematic bits of the encoded code block may include payload data. The parity 1 bits of the encoded code block may include parity bits for the payload data; these parity bits may be generated by Turbo code encoder 204 using a recursive systematic convolutional code (RSC code). Furthermore, the parity 2 bits of the encoded code block may comprise parity bits for a certain known transformation of the payload data; the RSC code may be used by Turbo code encoder 204 to generate these parity bits.

The Turbo code used by Turbo code encoder 204 may be 1/3Turbo coding functions. Thus, an X-bit input to encoder 204 (e.g., X bits included in M code blocks) may produce as output approximately 3X bits (e.g., approximately 3X bits in M encoded code blocks, 3X +12 bits … …). However, wireless communication apparatus 202 cannot transmit the 3X bits over the channel. Thus, wireless communication apparatus 202 can use rate matching to transform from the 3X bits to a smaller number of bits for transmission over the channel.

It is contemplated that Turbo code encoder 204 may obtain any number of code blocks as input. For example, a larger number of code blocks may result in a larger stream of systematic bits, a larger stream of parity 1 bits, and a larger stream of parity 2 bits. Regardless of the size of each of these streams output from Turbo code encoder 204, wireless communication device 202 can process this output as follows.

The wireless communication apparatus 202 can also include a bit type separator 206 that separates the bits output by the Turbo code encoder 204 into different sets. Bit type separator 206 may identify the type of each bit output by Turbo code encoder 204; thus, the bit-type separator 206 may determine whether a bit is a systematic bit, a parity 1 bit, or a parity 2 bit. For example, the bit-type separator 206 may utilize a priori knowledge of the operation of the Turbo code encoder 204 to interpret the type of each of these bits; according to this example, Turbo code encoder 204 may output the systematic bits, parity 1 bits, or parity 2 bits in a predetermined order known to bit type separator 206. Thus, the bit type classifier 206 may utilize this knowledge to identify systematic bits, parity 1 bits, or parity 2 bits. After identifying the bit type, bit type separator 206 may collect the systematic bits in a first group, the parity 1 bits in a second group, and the parity 2 bits in a third group.

Further, wireless communications apparatus 202 can include an interleaver 208 that interleaves bits for transmission. The interleaver 208 may randomly arrange the bits interleaved together; thus, the Y bits input into the interleaver 208 in the first sequence may be output by the interleaver 208 as a randomized second sequence of Y bits, where Y may be any integer. For example, interleaving may protect transmissions from burst errors. By way of illustration, interleaver 208 may be a Quadratic Permutation Polynomial (QPP) interleaver; however, claimed subject matter is not so limited. The systematic bits collected in the first group by the bit type separator 206 may be interleaved together by an interleaver 208 to arrange the bits in an unconnected manner. The interleaved systematic bits in this randomized sequence can be represented as a first set of bits for transmission over a channel. The interleaver 208 may also interleave the parity 1 bits collected in the second group by the bit type separator 206. In addition, the interleaver 208 may also interleave the parity 2 bits collected in the third group by the bit type separator 206. Although one interleaver 208 is described, it is contemplated that wireless communication apparatus 202 can include more than one interleaver, each of which can be substantially similar to interleaver 208 (e.g., one interleaver can interleave systematic bits, while a second interleaver can interleave parity 1 bits and parity 2 bits, a first interleaver can interleave systematic bits, a second interleaver can interleave parity 1 bits, and a third interleaver can interleave parity 2 bits, … …).

Wireless communication apparatus 202 can also include an interleaver 210 that interleaves the interleaved parity 1 bits with the interleaved parity 2 bits. Interleaver 210 may generate a second set of bits for transmission over the channel based on the interleaved parity 1 bits and the interleaved parity 2 bits. The interleaver 210 organizes the interleaved parity 1 bits and the interleaved parity 2 bits in a specific order; that is, the interleaver 210 may alternate between interleaved parity 1 bits and interleaved parity 2 bits. Thus, the output of interleaver 210 (e.g., the second set of bits for transmission over the channel) may be a sequence that alternates between interleaved parity 1 bits and interleaved parity 2 bits (e.g., every other bit is a parity 1 bit, every other bit is a parity 2 bit, … …). The use of interleaver 210 allows the parity bits output by Turbo code encoder 204 to be processed in a different manner than the systematic bits output by Turbo code encoder 204.

Wireless communication apparatus 202 may also include a mapper 212 and a transmitter 214. Mapper 212 may insert or fill a first set of bits for transmission produced by interleaver 208 and a second set of bits for transmission output by interleaver 210 into a circular buffer. For example, the circular buffer may be a fixed size buffer, which may be directly related to the size of the associated code block. Thus, mapper 212 may first wrap bits from a first group (e.g., interleaved systematic bits) around the circular buffer. Thereafter, mapper 212 may wrap bits from a second group (e.g., interleaved parity 1 bits interleaved with interleaved parity 2 bits in an alternating manner) around the circular buffer. Although the use of a circular buffer is described, it can be appreciated that mapper 212 can use any mapping of the first and second sets of bits. Further, the transmitter 214 may then transmit the bits in the circular buffer over the channel. For example, transmitter 214 may transmit the bits in the ring buffer (or in any other mapping used by mapper 212) to a different other wireless communication device (not shown).

As described, in certain situations, especially under high code rate conditions, wireless communication device 202 may not be able to transmit all bits of an encoded code block of a given transport block. It can be appreciated that in this case, the transmitter 214 will not transmit some bits of each encoded code block of the transport block (e.g., encoded code block 0, encoded code block 1 … … encoded code block M-1), which may be stored in an associated circular buffer (e.g., circular buffer 0, circular buffer 1, … … circular buffer M-1). The number of bits transmitted by the transmitter 214 from each circular buffer may (but need not) be the same in the case where all code block sizes of a transport block are the same. However, in some operating environments, a given transport block may include code blocks of different sizes. It will be appreciated that operation in such an environment may result in different sized circular buffers and opportunities to transmit different numbers of bits from one circular buffer relative to another.

Accordingly, wireless communication apparatus 202 can further include a transmission budgeter 216 and a buffer budgeter 218 to facilitate rate matching, among other things, in a wireless communication environment having a plurality of code block sizes. The transmission budgeter 216 may obtain a transmission budget that defines a total number of bits to be transmitted from all circular buffers, where each circular buffer in the circular buffer array may be mapped to and include data in an associated encoded code block and/or code block of the transport block. It will be appreciated that the transmission budget may be predefined or predetermined according to a pre-known or specified standard, or may be determined according to the discovery or detection of existing conditions.

Buffer budgeter 218 may calculate, for each circular buffer in the array, its corresponding buffer budget, where the buffer budget may specify the number of bits that the associated circular buffer may transmit in the total transmission budget. Typically, the buffer budget of a circular buffer is proportional to the size of the circular buffer. Thus, the buffer budget may be based on and proportional to the size of the associated code block of a given transport block. Accordingly, buffer budgeter 218 may apply one or more sets of recursive expressions to compute each corresponding buffer budget, for which three examples are provided below.

Before proceeding with this discussion, it is to be understood that the expressions, formulas, equations, and the like provided herein are exemplary and are intended to provide a specific illustration for ease of understanding. Accordingly, any such examples provided herein are not necessarily intended to limit the appended claims. Also, it should be noted that the included exemplary expressions may use the following notation:

N_d，jnumber of data tones (tones) of transport block i

M_iModulation stage for transport block i

C_i，jSize of jth code block of transport block i

N_i，jBig and small is C_i，jNumber of code blocks of

N_tbNumber of transport blocks

N_cb，iNumber of code blocks of different sizes of transport block i

N_t，iTotal number of code blocks of transport block i

Example 1

Example 1 considers the case where a different number of bits may be transmitted (e.g., by transmitter 214) from each circular buffer. In one embodiment, the number of bits denoted K sent from the circular buffer associated with transport block i may be recursively calculated using the following equation:

K_i，-1＝0

0≤m≤N_i，j-1

in one embodiment, the recursive formula may be applied to the circular buffers in descending order of priority. Thus, the buffer budgeter can index each circular buffer in this priority order. It should be appreciated that this priority order may be arbitrary or based on a particular design form. For example, consider an example in which there is an index ofSize of C_aN of (A)_aCode block and index ofSize of C_bN of (A)_bAnd (4) code blocks. The priority order may be arbitrary, e.g.OrOr according to some predetermined scheme.

Example 2

Example 2 considers the case where substantially the same number of bits may be transmitted (e.g., by transmitter 214) from each circular buffer of substantially the same size. This example handles the last circular buffer size differently than otherwise. The following equation may be used in one embodiment to recursively calculate the size of the slave and transport block i as C_i，mNumber of bits sent by the circular buffer corresponding to the code block:

K_i，-1＝0

K_i，-1＝0

0≤m≤N_cb，i-2

for the last circular buffer size, there are two buffer budgets calculated, each with a different size:

m＝N_cb，i-1

m＝N_cb，i-1

thus, in one embodiment, the recursive formula may be applied to all circular buffers of a given size in order of decreasing priority. It will be appreciated that this formula can be applied to all circular buffers of the same size at the same time.

Example 3

Example 3 consider the example 1 and 2 hybrid approaches, taking advantage of the fact that in certain operating environments, although the code block sizes of the transport blocks may be different, each transport block will not include more than two different code block sizes. Thus, in one embodiment, given that there are at most 2 code block sizes, the following simplified equation may be utilized, where:

N_i，0big and small is C_i，0Number of code blocks of

N_i，1Big and small is C_i，1Number of code blocks of

The first scheme may be used to calculate the available sum-sum size C_i，0And C_i，1The number of modulation symbols transmitted by all circular buffers associated with the code block, for example:

for each set of circular buffers and/or code blocks, the actual number of modulation symbols transmitted from this available number may be calculated according to a second scheme, such as:

0≤m≤N_i，0-2

m＝N_i，j-1

the above actually implies that for a certain size, the number of modulation symbols sent from all circular buffers of this size is (possibly) the same, except for the last circular buffer of this size. Thus, the total number of allocated modulation symbols per transport block (e.g., the transmission budget obtained or determined by the transmission budgeter 216) may be divided in proportion to the number of circular buffers of each size (e.g., with similar code rates across all code blocks).

In one embodiment, the buffer budget for a given circular buffer may be defined by the modulation level (e.g., M) used for transport block i_i) Integer multiples of the number of bits described. Accordingly and possibly in connection with serial transmission of data, these schemes may be used for implementation of a pipelined decoder architecture, where there are no modulation symbols spanning more than one code block.

The circular buffer based rate matching described herein may include the use of one interleaver in a hybrid automatic repeat request (HARQ) bit insertion buffer process (e.g., for evolved universal terrestrial radio access (E-UTRA)). In contrast, conventional rate matching techniques often use additional channel interleavers, which may increase the complexity associated with such techniques.

The following examples are provided for illustrative purposes, and it is to be appreciated that the claimed subject matter is not so limited. According to this example, wireless communication apparatus 202 may input 1000 bits (e.g., from code block 0 to M-1) to Turbo code encoder 204. Turbo code encoder 204 may process the 1000 bits and output approximately 3000 bits. The 3000 bits may include 1000 systematic bits, 1000 parity 1 bits, and 1000 parity 2 bits. Bit type separator 206 may identify the type of each of the 3000 bits and group the 1000 systematic bits, 1000 parity 1 bits, and 1000 parity 2 bits into different sets. In addition, interleaver 208 may randomly interleave the 1000 systematic bits together to produce a first set of bits for transmission. In addition, the interleaver 208 may randomly interleave the 1000 parity 1 bits together. In addition, the interleaver 208 may randomly interleave the 1000 parity 2 bits together. Thereafter, interleaver 210 may combine the randomly interleaved 1000 parity 1 bits with the randomly interleaved 1000 parity 2 bits (e.g., parity 1 bit, parity 2 bit … …) in an alternating manner to generate a second set of bits for transmission, wherein the second set of bits comprises 2000 bits. In addition, mapper 212 may insert bits into a circular buffer.

According to one example, 2000 bits may be transmitted by wireless communication apparatus 202 (e.g., 2000 bits may be inserted into a circular buffer). Thus, mapper 212 may insert 1000 interleaved systematic bits from the first group into the circular buffer (e.g., mapper 212 may add a sequence of these 1000 interleaved systematic bits clockwise (or counterclockwise) starting at a particular location of the circular buffer). In addition, mapper 212 may insert the first 1000 bits from the 2000 bits included in the second group into the circular buffer (e.g., mapper 212 may continue to add the sequence of 1000 parity bits to circular buffer … … in a similar manner from the end of the sequence of interleaved systematic bits); thus, the remaining 1000 bits do not have to be inserted into the circular buffer by mapper 212 (e.g., because the circular buffer is full). In addition, the transmitter 214 may transmit the 2000 bits included in the circular buffer through a channel. By utilizing system 200, the 1000 systematic bits can all be transmitted by transmitter 214 because systematic bits can be preferentially processed over parity bits (e.g., systematic bits can be considered more important than parity bits). In addition, 500 parity 1 bits and 500 parity 2 bits may be transmitted with the remaining resources (e.g., parity 1 bits and parity 2 bits may be provided with equal weighting … …). Although the foregoing describes using equal weights for parity 1 bits and parity 2 bits, it will be appreciated that any unequal weight may be used between parity 1 bits and parity 2 bits.

According to one example, consider a transport block that is divided into two code blocks (e.g., M-2). Assume further that a transport block is defined as 200 bits. This means that only 200 bits from the transport block can be sent from the 2 associated circular buffers over the channel. If all code block sizes of a transport block are equal, the first 100 bits from each of the two circular buffers may be transmitted, for example. However, if the code blocks are of different sizes, e.g., the first code block is twice the size of the second code block, then the size of the first circular buffer is twice the size of the second circular buffer, and additionally the buffer budget for the first circular buffer is twice the budget for the second circular buffer. Thus, the buffer budget may be set to be proportional to the size of the circular buffer (and/or the size of the associated code block or encoded code block). In this way, the buffer budget for the first ring buffer may be set to 133 and the budget for the second ring buffer may be set to 67, since 133+67 is 200 and 133 is approximately twice 67.

It should further be appreciated that the buffer budget may also be based on the modulation level (M) for the associated transport block_i). In particular, the buffer budget may be limited to integer multiples of the modulation order. Typically, the modulation level is set according to a particular operating characteristic, e.g., quadrature phase shift keying (QPSK, e.g., M_i2), 16-QAM (quadrature amplitude modulation, e.g. M)_i4), 64 QAM (e.g., M)_i6), and so on. Regardless of the particular modulation order, the buffer budget may be an integer multiple of that modulation order. Thus, according to the above example, assuming that the modulation order is 4, instead of setting the buffer budgets for the two circular buffers to 133 and 67, respectively, these buffer budgets are set to, for example, 132 and 68, because these latter two values are integer multiples of 4 and these actual values are still proportional to the corresponding buffer sizes.

Further, system 200 supports transmitting multiple transport blocks. Thus, if there are multiple transport blocks, rate matching may be performed on a per transport block basis.

Referring to fig. 3, shown is an exemplary diagram 300 for using a circular buffer based rate matching algorithm. At 302, a transport block may be input. The transport block may be partitioned into M code blocks (e.g., code block 0304, code blocks 1306, … …, code block M-1308), where M may be any integer. The M code blocks may be input to the Turbo encoder 310 to generate M encoded code blocks (e.g., encoded code block 0312, encoded code blocks 1314, … …, encoded code blocks M-1316). Each of the encoded code blocks 312 & 316 may be generated from a corresponding one of the code blocks 304 & 308. Each encoded code block 312 and 316 generated from the Turbo encoder 310 may include systematic bits, parity 1 bits, and parity 2 bits. Thus, the encoded code block 0312 may include systematic bits 0318, parity 1 bits 0320, and parity 2 bits 0322, the encoded code block 1314 may include systematic bits 1324, parity 1 bits 1326, and parity 2 bits 1328, … …, and the encoded code block M-1316 may include systematic bits M-1330, parity 1 bits M-1332, and parity 2 bits M-1334.

Thereafter, each class of bits may be identified and grouped. Thus, systematic bits 0318, systematic bits 1324, … …, systematic bits M-1330 may be identified as systematic bits and collected in a first group. Parity 1 bit 0320, parity 1 bits 1326, … …, parity 1 bits M-1332 may be identified as parity 1 bits and collected in the second group. Further, parity 2 bits 0322, parity 2 bits 1328, … …, parity 2 bits M-1334 may be identified as parity 2 bits and collected in a third group.

Systematic bits 318, 324, and 330 may be input into an interleaver 336 to randomize their sequence. In addition, the parity 1 bits 320, 326, and 332 may be input into the interleaver 338 to randomize the sequence thereof. In addition, the parity 2 bits 322, 328, and 334 may be input into the interleaver 340 to randomize the sequence thereof. As shown, separate interleavers 336, 338, and 340 may be used for systematic bits 318, 324, and 330, parity 1 bits 320, 326, and 332, and parity 2 bits 322, 328, and 334, respectively. According to another example (not shown), a common interleaver may be used for systematic bits 318, 324, and 330, parity 1 bits 320, 326, and 332, and parity 2 bits 322, 328, and 334. Pursuant to another example, interleaver 336 can interleave systematic bits 318, 324, and 330, while a different interleaver (not shown) can interleave parity 1 bits 320, 326, and 332 together and parity 2 bits 322, 328, and 334 together (e.g., the interleaving of parity 1 bits and parity 2 bits can be separate from one another).

The output of interleaver 336 may be a random sequence of systematic bits 342. In addition, the outputs of interleavers 338 and 340 may be interleaved together in an alternating manner to produce a sequence 344 of parity 1 and 2 bits. Thereafter, the sequence of systematic bits 342 and the sequence of parity 1 and 2 bits 344 may be inserted into the circular buffer 346. For example, the sequence of systematic bits 342 may be inserted first into the circular buffer 346, and then the sequence of parity 1 and 2 bits 344 may be inserted into the circular buffer 346 using any remaining space. Thus, the filling of the ring buffer 0346 may start at a particular position of the sequence of systematic bits 342 and proceed clockwise (or counterclockwise) to fill the first segment 348 of the ring buffer 346. If the sequence of systematic bits 342 can be fully inserted into the circular buffer 346, then the insertion of the sequence of parity 1 and 2 bits 344 into the remaining spatial segments 350 and 352 of the circular buffer 346 can begin. Although shown as separate from each other, it is contemplated that segments 350 and 352 may be substantially similar to each other and/or may be incorporated into a common segment of circular buffer 346 (not shown). The insertion of the sequence of parity 1 and 2 bits 344 may continue around the circular buffer 346 until the end of this sequence 344 is reached or no space remains available for the buffer 346.

It will be appreciated that the above or similar process may be used to fill each circular buffer in one-to-one correspondence with code blocks in the transport block 302. Thus, whereas the ring buffer 0346 corresponds to data from the code block 0304 and/or the encoded code block 0312, the ring buffer M-1358 may correspond to the code block M-1308 and/or the encoded code block M-1316 and include similar components and information that is populated in a similar manner as described in connection with the ring buffer 0346.

When data is transmitted from the circular buffers through the channel, each circular buffer transmits bits from the start. Here, this starting point is denoted by reference numeral 354 for the ring buffer 0348 and by reference numeral 360 for the ring buffer M-1358, which may be determined according to the Redundancy Version (RV) used. Ideally, all of the bits included in all of the circular buffers will be transmitted over the channel, however, when only a portion of the data from transport block 302 can be transmitted over the channel, an endpoint can be calculated for each circular buffer based on the start of the particular circular buffer and a buffer budget that defines the number of bits that can be transmitted by the particular buffer. For circular buffer 0348, the endpoint is depicted as endpoint 356, and for circular buffer M-1358, the endpoint is depicted as endpoint 362.

Since the code blocks from the transport block 302 may have different size code block partitions therein, the end points of different circular buffers may be significantly different. In particular, in one embodiment, the end of the circular buffer may be determined by offsetting the start from the buffer budget, which may be proportional to the size of the associated code block. Thus, for example, if code block 0304 is of a different size than code block M-1308, then the circular buffer 0346 may be of a different size than the circular buffer M-1358 and its corresponding buffer budget (and hence resulting endpoint) may also be different. In general, the corresponding buffer budgets are different from each other in direct proportion to the size of the associated circular buffer (or code block/encoded code block).

Referring to fig. 4-7, methodologies for implementing circular buffer based rate matching in a wireless communication environment are illustrated. While, for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more embodiments, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more embodiments.

Referring to fig. 4, illustrated is a methodology 400 that facilitates rate matching in a wireless communication environment. At 402, systematic bits, parity 1 bits, and parity 2 bits from an encoder (e.g., a Turbo encoder) may be separated into different groups. For example, a transport block may be divided into a plurality of code blocks. A Turbo code may be applied to each of the plurality of code blocks to generate a plurality of encoded code blocks. The encoded code blocks output by means of the Turbo code may each comprise systematic bits, parity 1 bits and parity 2 bits. Furthermore, each of these bit types may be identified so that the bits can be separated into different groups. At 404, the systematic bits, parity 1 bits, and parity 2 bits may be interleaved in respective different groups. The systematic bits may be interleaved together to randomize the ordering of the systematic bits, the parity 1 bits may be interleaved together to randomize the ordering of the parity 1 bits, and the parity 2 bits may be interleaved together to randomize the ordering of the parity 2 bits; thus, three randomized orderings (e.g., for systematic, parity 1, and parity 2 bits, respectively) may be generated. At 406, the interleaved parity 1 bits may be interleaved with the interleaved parity 2 bits. For example, the randomized ordering of parity 1 bits and the randomized ordering of parity 2 bits may be combined in an alternating manner, where each bit in the interleaved output alternates between being either a parity 1 bit or a parity 2 bit. According to another example, the randomized ordering of the parity 1 bits and the randomized ordering of the parity 2 bits may be combined using any other different predefined manner. At 408, interleaved systematic bits may be inserted into a circular buffer followed by interleaved and interleaved parity 1 bits and parity 2 bits. Thus, interleaved systematic bits can be preferentially selected for inclusion in the circular buffer. Furthermore, after all systematic bits have been inserted into the circular buffer, the interleaved parity 1 bits and parity 2 bits may be contained in the circular buffer using any available resources. At 410, the bits inserted into the circular buffer may be transmitted. Thus, for example, if all of the systematic bits and a portion of the parity 1 bits and parity 2 bits are accommodated in a circular buffer, these included bits may be transmitted through the channel without transmitting the remaining parity 1 bits and parity 2 bits; however, if all systematic bits and all parity 1 and parity 2 bits are accommodated in the circular buffer, all these bits can be transmitted through the channel.

Turning to fig. 5, illustrated is a methodology 500 that facilitates preferentially processing systematic bits in connection with circular buffer based rate matching in a wireless communication environment. At 502, systematic bits from at least one encoded code block output by an encoder (e.g., Turbo encoder … …) may be identified. For example, systematic bits can be identified using a priori knowledge about the format of the encoded code block generated from the encoder. At 504, the identified systematic bits can be collected. At 506, the collected systematic bits can be interleaved together to produce a randomized sequence of systematic bits. At 508, the randomized sequence of systematic bits can be transmitted prior to transmitting the parity bits included in the at least one encoded code block output by the encoder. For example, the parity bits may include parity 1 bits and parity 2 bits. For example, a randomized sequence of systematic bits can be inserted into the circular buffer before the parity bits are included.

Referring now to fig. 6, illustrated is a methodology 600 that facilitates utilizing rate matching utilizing a circular buffer in a wireless communication environment. At 602, parity 1 bits and parity 2 bits may be identified from at least one encoded code block output by an encoder (e.g., Turbo encoder … …). For example, parity 1 bits and parity 2 bits may be identified with a priori knowledge about the format of the encoded code block generated from the encoder. At 604, the identified parity 1 bits may be collected in a first set and the identified parity 2 bits may be collected in a second set. At 606, the collected parity 1 bits can be interleaved together to produce a randomized sequence of parity 1 bits. At 608, the collected parity 2 bits may be interleaved together to generate a randomized sequence of parity 2 bits. At 610, the randomized sequence of parity 1 bits and the randomized sequence of parity 2 bits can be interleaved in an alternating manner to produce an interleaved sequence of parity 1 bits and parity 2 bits. According to another example, the randomized sequence of parity 1 bits and the randomized sequence of parity 2 bits may be combined using any other different predefined manner. At 612, at least a portion of the interleaved sequence of parity 1 bits and parity 2 bits can be transmitted using available resources after transmitting the complete sequence of systematic bits included in the at least one encoded code block output by the encoder.

It is to be appreciated that, in accordance with one or more aspects described herein, inferences can be made regarding utilizing circular buffer based rate matching. As used herein, the term to "infer" or "inference" refers generally to the process of reasoning about or inferring states of the system, environment, and/or user from a set of observations as captured via events and/or data. Inference can be employed to identify a specific context or action, or can generate a probability distribution over states, for example. This inference can be probabilistic-that is, the computation of a probability distribution over states of interest based on a consideration of data and events. Inference can also refer to techniques employed for composing higher-level events from a set of events and/or data. Such inference results in the construction of new events or actions from a set of observed events and/or stored event data, whether or not the events are correlated in close temporal proximity, and whether the events and data come from one or several event and data sources.

According to one example, one or more methods provided above can include making inferences pertaining to the type of parity bit (e.g., systematic bit, parity 1 bit, and parity 2 bit). By way of further illustration, inferences can be made regarding determining how to combine (e.g., interleave) parity 1 bits and parity 2 bits; thus, for example, a different weighting may be assigned to each parity bit type based on this inference. It will be appreciated that the foregoing examples are illustrative in nature and are not intended to limit the number of inferences that can be made or the manner in which such inferences are made in conjunction with the various embodiments and/or methods described herein.

Turning now to fig. 7, illustrated is a methodology 700 for implementing rate matching in a wireless communication environment with multiple code block sizes for a transport block. At 702, each circular buffer in an array of circular buffers can be filled with bits from an associated code block in a set of code blocks that make up a transport block. Thus, a given transport block may be partitioned into M code blocks, where M may be substantially any integer. For each of these code blocks, there may be an associated encoded code block for storing encoded data from that code block, and an associated circular buffer for storing data from that encoded code block.

At 704, a transmission budget defining a total number of bits to be transmitted from all circular buffers in the array may be obtained. It will be appreciated that since the circular buffer array comprises a circular buffer for each code block in a transport block, the transmission budget actually describes the number of bits that can be transmitted from a particular transport block.

In the following description, at 706, a corresponding buffer budget may be calculated for each circular buffer in the array that defines a number of bits to be transmitted from the associated circular buffer, wherein the corresponding buffer budget occupies a portion of the transmission budget and is proportional to a size of the associated circular buffer. It can be appreciated that the sum of the total buffer budget for a transport block can be substantially equal to the transmission budget, even though each corresponding buffer budget may be different in size (e.g., number of bits to transmit) from one another depending on the relative size.

At 708, the corresponding buffer budget may be defined to be an integer multiple of a number of bits described by a modulation level of the transport block. In other words, the number of bits described by the buffer budget may be a multiple of the modulation order. Typically, the modulation levels will be 2, 4, 6, etc., so (although other examples may exist, although not required), the buffer budget will define a value that is an integer multiple of 2, 4, 6, or any modulation level used for the transport block.

Fig. 8 is an illustration of an access terminal 800 that facilitates performing circular buffer based rate matching in a wireless communication system. Access terminal 800 comprises a receiver 802 that receives a signal from, for instance, a receive antenna (not shown), and performs typical operations on (e.g., filters, amplifies, and downconverts) the received signal and digitizes the conditioned signal to obtain samples. Receiver 802 can be, for example, an MMSE receiver, and can comprise a demodulator 804 that can demodulate received symbols and provide them to a processor 806 for channel estimation. Processor 806 can be a processor dedicated to analyzing information received by receiver 802 and/or generating information for transmission by a transmitter 816, a processor that controls one or more components of access terminal 800, and/or a processor that both analyzes information received by receiver 802, generates information for transmission by transmitter 816, and controls one or more components of access terminal 800.

Access terminal 800 can additionally comprise memory 808 that is operatively coupled to processor 806 and that can store data to be transmitted, received data, and any other suitable information related to performing the various operations and functions set forth herein. Memory 808 can also store protocols and/or algorithms related to circular buffer based rate matching.

It will be appreciated that the data store (e.g., memory 808) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, the non-volatile memory may include: read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable PROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, RAM may be provided in a variety of ways, such as: synchronous RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 808 of the subject systems and methods is intended to comprise, without being limited to, these memory types, as well as any other suitable memory types.

Receiver 802 is also operatively coupled to a transmission budgeter 810 and/or a buffer budgeter 812, which can be substantially similar to transmission budgeter 216 of fig. 2 and buffer budgeter 218 of fig. 2. Moreover, although not shown, it is contemplated that access terminal 800 can include a Turbo code encoder substantially similar to Turbo code encoder 204 of fig. 2, a bit type separator substantially similar to bit type separator 206 of fig. 2, an interleaver substantially similar to interleaver 208 of fig. 2, an interleaver substantially similar to interleaver 210 of fig. 2, and/or a mapper substantially similar to mapper 212 of fig. 2. Transmission budgeter 810 determines, infers, detects, receives, or otherwise obtains a transmission budget, which may be described as a number of bits transmitted for a given transport block. Thus, the circular buffers, each for one code block of a transport block, should collectively conform to the transmission budget for the total number of bits or total number of bits transmitted.

However, given that code blocks may have different sizes, each circular buffer may also differ in size and also occupy a different proportion of the total transmission budget. Thus, buffer budgeter 812 can calculate a buffer budget that describes the number of bits of the total transmission budget that can be allocated to a particular circular buffer. Buffer budgeter 812 may calculate a buffer budget for each circular buffer, where each buffer budget is proportional to a size of an associated circular buffer (or associated code block or associated encoded code block).

Access terminal 800 further comprises a modulator 814 and a transmitter 816, transmitter 816 transmits signals to, for instance, a base station, another access terminal, and/or the like. Although illustrated as being separate from the processor 806, it is to be appreciated that the transmission budgeter 810, the buffer budgeter 812, and/or the modulator 814 can be part of the processor 806 or multiple processors (not shown).

Fig. 9 is an illustration of a system 900 for circular buffer based rate matching performed in a wireless communication environment with multiple code block sizes. System 900 includes a base station 902 (e.g., access point … …), base station 902 having: a receiver 910 that receives signals from one or more access terminals 904 through a plurality of receive antennas 906; and a transmitter 922 that transmits signals to one or more access terminals 904 via transmit antenna 908. Receiver 910 can receive information from receive antennas 906 and is operatively coupled to a demodulator 912 that demodulates received information. Demodulated symbols can be analyzed by a processor 914 that is similar to the processor described above with respect to fig. 8, and coupled to a memory 916, the memory 916 storing data to be transmitted to or received from access terminal 904 (or a disparate base station (not shown)) and/or any other suitable information related to performing the various operations and functions set forth herein. Processor 914 is further coupled to a buffer budgeter 918 that can calculate a number of bits transmitted from the circular buffer, where the number is proportional to a size of the buffer or associated code block. For example, the buffer budget for a circular buffer associated with a larger code block may be larger than a circular buffer associated with a smaller code block of a given transport block.

The buffer budgeter 918 may be operatively coupled to a transmission budgeter 920, the transmission budgeter 920 determining or receiving a total number of bits that may be transmitted for a transport block. For example, the transmission budgeter 920 may obtain a total transmission allocation for the transport blocks, a portion of which may be allocated for each circular buffer. Moreover, although not shown, it is contemplated that base station 902 can comprise a Turbo code encoder substantially similar to Turbo code encoder 204 of FIG. 2, a bit type separator substantially similar to bit type separator 206 of FIG. 2, an interleaver substantially similar to interleaver 208 of FIG. 2, an interleaver substantially similar to interleaver 210 of FIG. 2, and/or a mapper substantially similar to mapper 212 of FIG. 2. Buffer budgeter 918 and transmission budgeter 920 (and/or a mapper (not shown)) can provide data to be transmitted to a modulator 922. For example, the data to be transmitted may be bits around a circular buffer allocated by buffer budgeter 918 and transmission budgeter 920. A modulator 922 can administer the frames for transmission by a transmitter 926 through antenna 908 to access terminal 904. Although illustrated as being separate from the processor 914, it is to be appreciated that interleaver 918, interleaver 920, and/or modulator 922 can be part of processor 914 or a number of processors (not shown).

Fig. 10 shows an exemplary wireless communication system 1000. The wireless communication system 1000 depicts one base station 1010 and one access terminal 1050 for sake of brevity. However, it is to be appreciated that system 1000 can include more than one base station and/or more than one access terminal, wherein additional base stations and/or access terminals can be substantially similar or different from example base station 1010 and access terminal 1050 described below. In addition, it is to be appreciated that base station 1010 and/or access terminal 1050 can employ the systems (fig. 1-2, 8-9, and 11) and/or methods (fig. 4-7) described herein to facilitate wireless communication there between.

At base station 1010, traffic data for a number of data streams is provided from a data source 1012 to Transmit (TX) data processor 1014. According to an example, each data stream can be transmitted over a respective antenna. TX data processor 1014 formats, codes, and interleaves the traffic data stream based on a particular coding scheme selected for that data stream to provide coded data.

The coded data for each data stream can be multiplexed with pilot data using Orthogonal Frequency Division Multiplexing (OFDM) techniques. Additionally or alternatively, the pilot symbols may be Frequency Division Multiplexed (FDM), Time Division Multiplexed (TDM), or Code Division Multiplexed (CDM). The pilot data is typically a known data pattern that is processed in a known manner and can be used at access terminal 1050 to estimate channel response. The multiplexed pilot and coded data for each data stream is modulated (i.e., symbol mapped) based on a particular modulation scheme (e.g., binary phase-shift keying (BPSK), quadrature phase-shift keying (QSPK), M-phase-shift keying (M-PSK), M-quadrature amplitude modulation (M-QAM), etc.) selected for that data stream to provide modulation symbols. The data rate, coding, and modulation for each data stream can be determined by instructions performed or provided by processor 1030.

The modulation symbols for the data streams are then provided to a TX MIMO processor 1020, which may further process the modulation symbols (e.g., for OFDM). TX MIMO processor 1020 then forwards N_TN are provided by a plurality of transmitters (TMTR)1022a through 1022t_TA stream of modulation symbols. In various embodiments, TX MIMO processor 1020 applies beamforming weights to the symbols of the data streams and to the antenna from which the symbol is being transmitted.

Each transmitter 1022 receives and processes a respective symbol stream to provide one or more analog signals, and further conditions (e.g., amplifies, filters, and upconverts) the analog signals to provide a modulated signal suitable for transmission over the MIMO channel. Then from N respectively_TN transmitted by antennas 1024a through 1024t from transmitters 1022a through 1022t_TA modulated signal.

At access terminal 1050, by N_RAntennas 1052a through 1052r receive the transmitted modulated signals and provide a received signal from each antenna 1052 to a respective receiver (RCVR)1054a through 1054 r. Each receiver 1054 conditions (e.g., filters, amplifies, and downconverts) a respective received signal, digitizes the conditioned signal to provide samples, and further processes the samples to provide a corresponding "received" symbol stream.

RX data processor 1060Receiving and processing data from N based on a particular receiver processing technique_RN of receiver 1054_RA stream of received symbols to provide N_TA "detected" symbol stream. RX data processor 1060 can demodulate, deinterleave, and decode each detected symbol stream to recover the traffic data for the data stream. The processing by RX data processor 1060 is complementary to that performed by TX MIMO processor 1020 and TX data processor 1014 at base station 1010.

Processor 1070 periodically determines which of the available technologies described above to use. Further, processor 1070 formulates a reverse link message comprising a matrix index portion and a rank value portion.

The reverse link message may comprise various types of information regarding the communication link and/or the received data stream. The reverse link message can then be processed by a TX data processor 1038, modulated by a modulator 1080, conditioned by transmitters 1054a through 1054r, and transmitted back to base station 1010, where TX data processor 1038 also receives traffic data for a number of data streams from a data source 1036.

At base station 1010, the modulated signals from access terminal 1050 are received by antennas 1024, conditioned by receivers 1022, demodulated by a demodulator 1040, and processed by a RX data processor 1042 to extract the reverse link message transmitted by access terminal 1050. Further, processor 1030 can process the extracted message to determine which precoding matrix to use for determining the beamforming weights.

Processors 1030 and 1070 can direct (e.g., control, coordinate, manage, etc.) operation at base station 1010 and access terminal 1050, respectively. Respective processors 1030 and 1070 can be associated with memory 1032 and 1072 that store program codes and data. Processors 1030 and 1070 can also perform computations to derive frequency and impulse response estimates for the uplink and downlink, respectively.

In one aspect, logical channels are classified into control channels and traffic channels. Logical control channels may include a Broadcast Control Channel (BCCH), which is a DL channel for broadcasting system control information. Further, the logical control channel may include a Paging Control Channel (PCCH), which is a DL channel transmitting paging information. In addition, the logical control channels may include a Multicast Control Channel (MCCH), which is a Point-to-multipoint DL channel used to transmit Multimedia Broadcast and Multicast Service (MBMS) scheduling and control information for one or several MTCHs. Typically, this channel is only used by UEs receiving MBMS (e.g. old MCCH + MSCH) after the Radio Resource Control (RRC) connection is established. In addition, the logical control channels may include a Dedicated Control Channel (DCCH), which is a point-to-point bi-directional channel for transmitting dedicated control information and may be used by UEs having an RRC connection. In one aspect, the logical traffic channels can include a Dedicated Traffic Channel (DTCH), which is a point-to-point bi-directional channel dedicated to one UE for conveying user information. In addition, the logical traffic channels may include a Multicast Traffic Channel (MTCH), which is a point-to-multipoint DL channel for transmitting traffic data.

In one aspect, transport channels are classified as DL and UL. DL transport channels include a Broadcast Channel (BCH), a downlink shared data channel (DL-SDCH) and a Paging Channel (PCH). The PCH may support UE power saving by being broadcast over the entire cell and mapped to physical layer (PHY) resources that may be used for other control/traffic channels (e.g., a Discontinuous Reception (DRX) cycle may be indicated to the UE by the network..). The UL transport channels may include a Random Access Channel (RACH), a request channel (REQCH), an uplink shared data channel (UL-SDCH), and a plurality of PHY channels.

The PHY channels may include a set of DL channels and UL channels. For example, DL PHY channels may include: common pilot channel (CPICH); a Synchronization Channel (SCH); common Control Channel (CCCH); shared DL Control Channel (SDCCH); multicast Control Channel (MCCH); shared UL Allocation Channel (SUACH); acknowledgement channel (ACKCH); DL physical shared data channel (DL-PSDCH); UL Power Control Channel (UPCCH); a Paging Indication Channel (PICH); and/or a Load Indication Channel (LICH). By way of further illustration, the UL PHY channels may include: physical Random Access Channel (PRACH); channel Quality Indication Channel (CQICH); acknowledgement channel (ACKCH); an Antenna Subset Indicator Channel (ASICH); shared request channel (SREQCH); UL physical shared data channel (UL-PSDCH); and/or a wideband pilot channel (BPICH).

It is to be understood that the embodiments described herein may be implemented by hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.

When the embodiments are implemented in software, firmware, middleware or microcode, program code or code segments, they can be stored in a machine-readable medium, such as a memory component. A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted using any suitable means including memory sharing, message passing, token passing, network transmission, etc.

For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in memory units and executed by processors. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

Referring to fig. 11, illustrated is a system 1100 that enables utilizing rate matching in a wireless communication environment. System 1100 can reside at least partially within a base station, for instance. According to another example, system 1100 can reside at least partially within an access terminal. It is to be appreciated that system 1100 can be represented as including functional blocks, which can be functional blocks that represent functions implemented by a processor, software, or combination thereof (e.g., firmware). System 1100 includes a logical grouping 1102 of electrical components that can act in conjunction. For example, logical grouping 1102 can include an electrical component for storing bits from a code block into an associated circular buffer for each code block of a set of code blocks that make up a transport block 1104. Further, logical grouping 1102 can include an electrical component for obtaining a transmission budget 1106 that defines a total number of bits to be transmitted from all circular buffers. Moreover, logical grouping 1102 can include an electrical component for determining respective buffer budgets that each describe a number of bits to be transmitted from an associated circular buffer 1108. Logical grouping 1102 can also include an electrical component for ensuring that each buffer budget is an integer multiple of a number of modulation symbols to be transmitted from an associated circular buffer 1110. For example, the number of bits transmitted from each circular buffer (e.g., in an operating environment with different block sizes for a transport block) is based on the overall transmission budget, but may still vary from circular buffer to circular buffer in a manner that is proportional to the respective buffer size. Furthermore, the respective buffer budget may also be limited such that the number of transmitted bits is an integer multiple of the modulation order of the transport block. Additionally, system 1100 includes a memory 1112 that retains instructions for executing functions associated with electrical components 1104, 1106, 1108, and 1110. While shown as being external to memory 1112, it is to be understood that electrical components 1104, 1106, 1108, and 1110 can exist within memory 1112.

What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the described embodiments are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim.

Claims (24)

1. A method for rate matching in a wireless communication environment, the method comprising:

filling each circular buffer in the circular buffer array with bits from an associated code block in a set of code blocks that make up the transport block;

obtaining a transmission budget defining a total number of bits to be transmitted from all circular buffers in the array; and

calculating, for each circular buffer in the array, a corresponding buffer budget defining a number of bits to be transmitted from the associated circular buffer, the corresponding buffer budget occupying a portion of the transmission budget and being proportional to a size of the associated circular buffer.

2. The method of claim 1, further comprising the steps of: limiting the corresponding buffer budget to an integer multiple of a number of bits described by a modulation level of the transport block.

3. The method of claim 1, further comprising the steps of: the index of each circular buffer is organized according to the order of descending priority.

4. The method of claim 1, the step of calculating a corresponding buffer budget comprising the steps of: the first recursive expression is applied when corresponding buffer budget changes for circular buffers having the same size are allowed.

5. The method of claim 1, the step of calculating a corresponding buffer budget comprising the steps of: the second recursive expression is applied when the corresponding buffer budget of circular buffers of the same size does not change.

6. The method of claim 5, further comprising the steps of: applying the second recursive expression according to a priority order based on a circular buffer size.

7. The method of claim 5, further comprising the steps of: the second recursive expression is applied simultaneously for circular buffers of the same size.

8. The method of claim 1, the step of calculating a corresponding buffer budget comprising the steps of: the hybrid recursive expression is applied when only one corresponding buffer budget among all buffer budgets of circular buffers having the same size is allowed to change.

9. The method of claim 1, further comprising the steps of: the bits in the associated code block are encoded and interleaved, and a portion of the encoded and interleaved bits are further interleaved before filling each circular buffer.

10. A wireless communication device, the wireless communication device comprising:

a mapper (212) for storing, for each code block of a set of code blocks comprising a transport block, bits from the code block into an associated circular buffer,

a transmission budgeter (216) for obtaining a transmission budget, said transmission budget defining a total number of bits to be transmitted from all circular buffers, an

A buffer budgeter (218) for determining a corresponding buffer budget describing a number of bits to be transmitted from the associated circular buffer, the corresponding buffer budget occupying a portion of the transmission budget and being a function of a size of the associated circular buffer.

11. The wireless communication apparatus of claim 10, wherein the buffer budgeter (218): ensuring that the corresponding buffer budget is an integer multiple of a number of modulation symbols to be transmitted from the associated circular buffer.

12. The wireless communications apparatus of claim 10, wherein each associated circular buffer is ordered according to descending order of priority.

13. The wireless communication apparatus of claim 10, wherein the buffer budgeter (218): when the buffer budget of a circular buffer having the same size is allowed to change, the corresponding buffer budget is determined using a first recursive formula.

14. The wireless communication apparatus of claim 10, wherein the buffer budgeter (218): when the buffer budget of a circular buffer having the same size does not change, the corresponding buffer budget is determined using a second recursion formula.

15. The wireless communication apparatus of claim 14, wherein the buffer budgeter (218): the second recursion formula is applied according to a priority order based on the size of the circular buffer.

16. The wireless communication apparatus of claim 14, wherein the buffer budgeter (218): the second recursion formula is applied simultaneously for circular buffers of the same size.

17. The wireless communication apparatus of claim 10, wherein the buffer budgeter (218): when only one buffer budget among all buffer budgets of a circular buffer having a given size is allowed to change, a hybrid recursive formula is used to determine the corresponding buffer budget.

18. The wireless communications apparatus of claim 10, the apparatus further comprising: a turbo code encoder (204) and an interleaver (208) for encoding and interleaving, respectively, bits in the code block prior to storage in an associated circular buffer.

19. A wireless communications apparatus that enables employing rate matching in a wireless communication environment, comprising:

means for padding data from an associated code block of a transport block into a circular buffer;

means for defining a total amount of data to be transmitted for the transport block; and

means for calculating an amount of data to be transmitted from the ring buffer based on a size of the ring buffer relative to other ring buffers.

20. The wireless communications apparatus of claim 19, further comprising: means for limiting an amount of data to be transmitted from the circular buffer to an integer multiple of a number of bits described by a modulation level of the transport block.

21. The wireless communications apparatus of claim 19, further comprising: means for indexing each circular buffer according to an order of decreasing priority.

22. The wireless communications apparatus of claim 21, further comprising: means for recursively applying one or more expressions with the order of priority decrementing to calculate an amount of data to be transmitted from the circular buffer.

23. The wireless communications apparatus of claim 19, further comprising: means for encoding and interleaving bits in the code block prior to filling each circular buffer.

24. An apparatus in a wireless communication system, comprising:

a processor configured to:

for each code block of the transport block, storing information included in the code block into an associated circular buffer;

configuring a transmission budget defining a total number of bits to be transmitted from all code blocks; and

determining a block budget that defines a number of bits to be transmitted from the code block, the block budget occupying a portion of the transmission budget and being a function of a size of the code block relative to other code blocks in the transport block.