HK1141164A

HK1141164A - Circular buffer based rate matching

Info

Publication number: HK1141164A
Application number: HK10107300.8A
Authority: HK
Inventors: D‧P‧马拉蒂; J‧蒙托霍; 魏永斌
Original assignee: 高通股份有限公司
Priority date: 2007-03-27
Filing date: 2008-03-27
Publication date: 2010-10-29

Description

Circular buffer based rate matching

Cross Reference to Related Applications

This patent application claims priority from U.S. provisional application No.60/908,402 entitled "A METHOD AND APPARATUS FOR CIRCULAR BUFFER BASED RATE MATCHING", filed 3, 27.2007. The entire contents of the above application are incorporated herein by reference.

Technical Field

The present disclosure relates generally to wireless communication, and more specifically to transmitting data using circular buffer based rate matching in a wireless communication system.

Background

Wireless communication systems are widely deployed to provide various types of communication such as voice and/or data over such wireless communication systems. A typical wireless data system or network may provide multiple users with access to one or more shared resources (e.g., bandwidth, transmit power). For example, the system may use various multiple access techniques such as Frequency Division Multiplexing (FDM), Time Division Multiplexing (TDM), Code Division Multiplexing (CDM), Orthogonal Frequency Division Multiplexing (OFDM), and so on.

In general, a wireless multiple-access communication system may simultaneously support communication for multiple access terminals. Each access terminal may communicate with one or more base stations via transmissions on forward and reverse links. The forward link (or downlink) refers to the communication link from the base stations to the access terminals, and the reverse link (or uplink) refers to the communication link from the access terminals to the base stations. The communication link may be established via a single-input single-output system, a multiple-input single-output system, or a multiple-input multiple-output system.

Wireless communication systems typically employ one or more base stations that provide a coverage area. A typical base station can transmit multiple data streams for broadcast, multicast, and/or unicast services, wherein a data stream can be a stream of data that can be received independently by an access terminal. An access terminal in the coverage area of such base station can be used to receive one, more than one, or all of the data streams carried by the mixed stream. Likewise, an access terminal can send data to a base station or another access terminal.

Recently, turbo codes, which are high performance error correction codes, have been developed to enhance data transmission over limited bandwidth communication links in the presence of data-corrupting noise. Any wireless communication device (e.g., base station, access terminal, etc.) can utilize turbo codes to encode data transmitted by each wireless communication device. the turbo code encoder may combine parity bits with systematic bits (e.g., payload data, etc.) to increase the total number of bits transmitted by the wireless communication device (e.g., if X bits are input to the turbo code encoder, approximately 3X bits may be output from the turbo code encoder).

However, the total number of coded bits output from the turbo code encoder to be transmitted over the channel may be different from the number of bits that the wireless communication device is capable of transmitting over the channel (e.g., the number of bits that the wireless communication device is capable of transmitting generally depends on the allocation, the properties or characteristics of the wireless communication device, and/or the wireless communication environment, etc.). For example, a wireless communication device may not be able to transmit all of the coded bits since the number of coded bits may exceed the number of bits that the wireless communication device is able to transmit on the channel. According to another example, the number of coded bits may be less than the number of bits that the wireless communication device is capable of transmitting on the channel. Thus, rate matching may be performed to vary the number of coded bits to be transmitted on the channel to match the number of bits that the wireless communication device is capable of transmitting on the channel; in particular, rate matching may puncture bits (e.g., delete bits) to reduce the rate (e.g., when the number of coded bits is greater than the number of bits that can be sent on the channel) or repeat bits to increase the rate (e.g., when the number of coded bits is less than the number of bits that can be sent on the channel). By way of example, when the number of coded bits is about 3X bits (e.g., based on X bits input to a turbo code encoder) and the about 3X bits exceeds the number of bits that can be transmitted over the channel, then less than 3X bits may be transmitted from the wireless communication device after performing rate matching. However, conventional rate matching techniques (e.g., rate matching in R99, R5, R6) are complex and are mainly used for transport channel multiplexing. For example, these commonly used rate matching techniques may involve several complex stages of puncturing or repetition and bit collection algorithms.

Disclosure of Invention

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

In accordance with one or more embodiments and corresponding disclosure thereof, various aspects are described in connection with facilitating the use of circular buffer based rate matching. A turbo code may be used to generate a coded block containing systematic bits, parity bits of a first type and parity bits of a second type. The type of bits may be identified to separate the bits into different groups. The systematic bits can be interleaved together to generate a randomized sequence of systematic bits; the first type of parity bits may be interleaved together to generate a randomized sequence of the first type of parity bits; and the second type of parity bits may be interleaved together to output a randomized sequence of the second type of parity bits. The randomized sequences of first and second parity bits may be interleaved in an alternating manner. A randomized sequence of systematic bits can be inserted into a circular buffer and, after inserting the entire sequence, interleaved parity bits can be inserted into the circular buffer (e.g., until capacity is reached). The bits inserted into the circular buffer are transmitted.

According to related aspects, a method that facilitates rate matching in a wireless communication environment is described. The method can comprise the following steps: the systematic bits, the first type of parity bits, and the second type of parity bits from the encoder are grouped into different groups. Further, the method may comprise: interleaving the systematic bits, the first type of parity bits, and the second type of parity bits in the respective different groups, respectively. Further, the method may comprise: interleaving the interleaved parity bits of the first type with the interleaved parity bits of the second type. The method may further comprise: the interleaved systematic bits are inserted into a circular buffer, followed by the interleaved and interleaved parity bits of the first type and parity bits of the second type. Further, the method may comprise: transmitting the bits inserted into the circular buffer.

Another aspect relates to a wireless communications apparatus. The wireless communication apparatus may include: a memory holding instructions related to: identifying systematic bits, first parity bits and second parity bits from at least one encoded block output from an encoder; collecting the identified systematic bits; interleaving the collected systematic bits together to generate a randomized sequence of systematic bits; collecting the identified parity bits of the first type; interleaving the collected first type of parity bits together to generate a randomized sequence of first type of parity bits; collecting the identified parity bits of the second type; interleaving the collected second type of parity bits together to generate a randomized sequence of second type of parity bits; interleaving the randomized sequence of the first type of parity bits and the randomized sequence of the second type of parity bits to generate an interleaved sequence of the first type of parity bits and the second type of parity bits; inserting a randomized sequence of systematic bits into a circular buffer followed by an interleaved sequence of first parity bits and second parity bits; and transmitting the bits inserted into the circular buffer. Further, the wireless communication apparatus may include: a processor coupled to the memory and configured to execute instructions retained in the memory.

Another aspect relates to a wireless communications apparatus that enables employing rate matching in a wireless communication environment. The wireless communication apparatus may include: means for interleaving systematic bits collected from at least one encoded block output from the encoder. Further, the wireless communication apparatus may include: means for interleaving parity bits of a first type collected from the at least one encoded block. Further, the wireless communication apparatus may include: means for interleaving parity bits of a second type collected from the at least one encoded block. Further, the wireless communication apparatus may include: means for interleaving the interleaved parity bits of the first type with the interleaved parity bits of the second type.

Another aspect relates to a machine-readable medium having stored thereon machine-executable instructions for: identifying systematic bits, first parity bits and second parity bits from at least one encoded block output from an encoder; combining the identified systematic bits into a first set, the identified first parity bits into a second set and the identified second parity bits into a third set; interleaving the collected systematic bits together to generate a randomized sequence of systematic bits; interleaving the collected first type of parity bits together to generate a randomized sequence of first type of parity bits; interleaving the collected second type of parity bits together to generate a randomized sequence of second type of parity bits; interleaving the randomized sequence of the first type of parity bits and the randomized sequence of the second type of parity bits in an alternating manner to generate an interleaved sequence of the first type of parity bits and the second type of parity bits; inserting a randomized sequence of systematic bits into a circular buffer followed by an interleaved sequence of first parity bits and second parity bits; and transmitting the bits inserted into the circular buffer.

According to another aspect, an apparatus in a wireless communication system may comprise: a processor, wherein the processor is operable to divide the systematic bits, the first parity bits, and the second parity bits into different groups. Further, the processor may be configured to interleave the systematic bits, the first type of parity bits, and the second type of parity bits in each of the different groups, respectively. Further, the processor may be configured to interleave the interleaved parity bits of the first type with the interleaved parity bits of the second type. The processor may be further configured to insert the interleaved systematic bits into a circular buffer followed by the interleaved and interleaved parity bits of the first type and parity bits of the second type. Further, the processor may be configured to transmit the bits inserted into the circular buffer.

To the accomplishment of the foregoing and related ends, the one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the described embodiments are intended to include all such aspects and their equivalents.

Drawings

Fig. 1 is an illustration of a wireless communication system in accordance with various aspects described herein.

Fig. 2 is an illustration of an example system that facilitates performing rate matching utilizing a circular buffer based algorithm in a wireless communication environment.

Fig. 3 is an exemplary diagram of using a circular buffer based rate matching algorithm.

Fig. 4 is an illustration of an example methodology that facilitates rate matching in a wireless communication environment.

Fig. 5 is an illustration of an example methodology that facilitates preferentially processing systematic bits in connection with circular buffer based rate matching in a wireless communication environment.

Fig. 6 is an illustration of an example methodology that facilitates employing rate matching using a circular buffer in a wireless communication environment.

Fig. 7 is an illustration of an example access terminal that facilitates performing circular buffer based rate matching in a wireless communication system.

Fig. 8 is an illustration of an example system that facilitates performing circular buffer based rate matching in a wireless communication environment.

Fig. 9 is an illustration of an example wireless network environment that can be employed in conjunction with the various systems and methods described herein.

Fig. 10 is an illustration of an example system that enables employing rate matching in a wireless communication environment.

Detailed Description

Various embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that such embodiment(s) may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between 2 or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).

Moreover, various embodiments are described herein in connection with an access terminal. An access terminal can also be called a system, subscriber unit, subscriber station, mobile, remote station, remote terminal, mobile device, user terminal, wireless communication device, user agent, user device, or User Equipment (UE). An access terminal may be a cellular telephone, a cordless telephone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device having wireless communication capabilities, a computing device, or other processing device connected to a wireless modem. Furthermore, various embodiments are described herein in connection with a base station. A base station may be utilized for communicating with mobile device(s) and may also be referred to as an access point, node B, eNodeB, or some other terminology.

Moreover, various aspects or features of the invention may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips, etc.), optical disks (e.g., Compact Disk (CD), Digital Versatile Disk (DVD), etc.), smart cards, and flash memory devices (e.g., EPROM, card, stick, key drive, etc.). In addition, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media capable of storing, containing, and/or carrying instruction(s) and/or data.

Referring now to fig. 1, a wireless communication system 100 is shown in accordance with various embodiments described herein. System 100 comprises a base station 102 that can include multiple antenna groups. For example, one antenna group can include antennas 104 and 106, another group can include antennas 108 and 110, and an additional group can include antennas 112 and 114. 2 antennas are shown for each antenna group, however, more or fewer antennas may be utilized for each group. Base station 102 can additionally include a transmitter chain and a receiver chain, each of which can be implemented as a plurality of components associated with signal transmission and reception (e.g., processors, modulators, multiplexers, demodulators, demultiplexers, antennas, etc.), as will be appreciated by one skilled in the art.

Base station 102 may communicate with one or more access terminals (e.g., access terminal 116 and access terminal 122); however, it is to be appreciated that base station 102 can communicate with substantially any number of access terminals similar to access terminals 116 and 122. The access terminals 116 and 122 can be, for example, cellular phones, smart phones, laptops, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other suitable device for communicating over the wireless communication system 100. As depicted, access terminal 116 is in communication with antennas 112 and 114, where antennas 112 and 114 transmit information to access terminal 116 over forward link 118 and receive information from access terminal 116 over reverse link 120. In addition, access terminal 122 is in communication with antennas 104 and 106, where antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 over reverse link 126. In a Frequency Division Duplex (FDD) system, forward link 118 can utilize a different frequency band than that used by reverse link 120, and forward link 124 can employ a different frequency band than that employed by reverse link 126, for example. Further, in a Time Division Duplex (TDD) system, forward link 118 and reverse link 120 can utilize a common frequency band and forward link 124 and reverse link 126 can utilize a common frequency band.

Each group of antennas and/or the area in which they are designed to communicate is referred to as a sector of base station 102. For example, antenna groups can be designed to communicate to access terminals in a sector of the areas covered by base station 102. In communication over forward links 118 and 124, the transmitting antennas of base station 102 can utilize beamforming to improve signal-to-noise ratio of forward links 118 and 124 for access terminals 116 and 122. Moreover, while base station 102 utilizes beamforming to transmit to access terminals 116 and 122 scattered randomly through an associated coverage, mobile devices in neighboring cells can be subject to less interference as compared to a base station transmitting through a single antenna to all its access terminals.

Base station 102, access terminal 116, and/or access terminal 122 can be a transmitting wireless communication device and/or a receiving wireless communication device at a given time. When sending data, the sending wireless communication device may encode the data for transmission. In particular, a transmitting wireless communication device may have (e.g., generate, obtain, save in memory, etc.) a certain number of information bits to be transmitted over a channel to a receiving wireless communication device. Such information bits may be contained in a transport block (or multiple transport blocks) of data, which may be segmented to produce multiple code blocks. Further, the transmitting wireless communication apparatus can encode each code block using a turbo code encoder (not shown). the turbo code encoder may output an encoded block for each code block inputted. The encoded blocks output by the turbo code encoder may each include 3 elements: systematic bits, first parity bits, and second parity bits.

The transmitting wireless communication device may use a simplified circular buffer-based rate matching algorithm (e.g., even when there are multiple code blocks and transport blocks) as compared to conventional techniques. In particular, circular buffer based rate matching may be achieved by the transmitting wireless communication device collecting systematic bits from all encoded blocks generated by a transport block. In addition, the collected systematic bits can be interleaved together to generate a first set of bits that are transmitted over the channel. In addition, the parity bits of the first type and the parity bits of the second type may be collected from all encoded blocks generated by the transport block. After collection, the parity bits of the first type may be interleaved together. Further, after collection, the parity bits of the second type may be interleaved together. The interleaved first type of parity bits and the interleaved second type of parity bits may then be interleaved together in an alternating manner to generate a second set of bits that are transmitted over the channel. The first set of bits and the second set of bits may be mapped to surround the circular buffer; however, the invention is not so limited, as any type of mapping is contemplated. The transmitting wireless communication device may then transmit bits from the first group (e.g., systematic bits) over the channel. After transmission of the first set of bits, the transmitting wireless communication device may transmit bits from the second set on the channel.

By separating the systematic bits from the first and second parity bits, the cyclic buffer based rate matching allows the systematic bits to be transmitted before the parity bits are sent. Thus, under high code rate conditions where a large number of systematic bits are to be transmitted in a given time period, the circular buffer based rate matching may result in improved performance compared to conventional techniques (e.g., R99 rate matching, R5 rate matching, R6 rate matching, etc.), while under low code rate conditions, the circular buffer based rate matching may have substantially the same performance as conventional rate matching techniques. Specifically, under high code rate conditions, the transmitting wireless communication apparatus is unable to transmit all bits of the encoded block. Thus, puncturing (e.g., deleting) of bits may be performed for rate matching purposes to reduce the number of bits used for communication. In association with puncturing of bits, the transmitting wireless communication apparatus preferentially selects systematic bits for transmission; thus, all systematic bits from the coded block are transmitted via the channel if possible; and a subset of the first type of parity bits and the second type of parity bits may be transmitted over the channel if additional bits may be transmitted. Furthermore, when a low code rate is used, all systematic bits, all first type parity bits and second type parity bits from the encoded block may be transmitted over the channel.

Turning now to fig. 2, illustrated is a system 200 that facilitates performing rate matching utilizing a circular buffer based algorithm in a wireless communication environment. System 200 includes a wireless communication device 202 that is shown transmitting data via a channel. Although shown as transmitting data, wireless communication device 202 can also receive data via a channel (e.g., wireless communication device 202 can simultaneously transmit and receive data, wireless communication device 202 can transmit and receive data at different times, a combination thereof, etc.). Wireless communication device 202 can be, for example, a base station (e.g., base station 102 of fig. 1, etc.), an access terminal (e.g., access terminal 116 of fig. 1, access terminal 122 of fig. 1, etc.), and/or the like.

Wireless communication device 202 can include a turbo code encoder 204 (e.g., encoder, etc.) that encodes data to be transmitted from wireless communication device 202. turbo code encoder 204 utilizes high performance error correction codes to optimize information transmission over a limited bandwidth connection link in the presence of data-corrupting noise. The input to the turbo code encoder 204 may be one or more code blocks. For example, the transport block may be divided into M code blocks (e.g., code block 0, code block 1,. or code block M-1), where M may be substantially any integer, and these M code blocks may be used as inputs to the turbo code encoder 204. turbo code encoder 204 may output M encoded blocks (e.g., encoded block 0, encoded block 1,.., encoded block M-1) based on the input M code blocks. Further, each of the M encoded blocks output by turbo code encoder 204 may correspond to a respective input one of the M code blocks (e.g., encoded block 0 may be generated based on code block 0, encoded block 1 may be generated based on code block 1, and encoded block M-1 may be generated based on code block M-1).

The M encoded blocks output by turbo code encoder 204 may each include three elements: systematic bits, first parity bits, and second parity bits. An example is provided below relating to one of the M coding blocks, it being understood that the other coding blocks are substantially similar. The systematic bits of the encoded block may comprise payload data. The first parity bits of the encoded block may comprise parity bits for the payload data; these parity bits may be generated by the turbo code encoder 204 using a recursive systematic convolutional code (RSC code). Further, the parity bits of the second type of the encoded block may comprise parity bits of a known arrangement for the payload data; the RSC code may be used by the turbo code encoder 204 to generate these parity bits.

The turbo code used by turbo code encoder 204 may have 1/3turbo encoding functions. Thus, an input of X bits (e.g., X bits contained in M code blocks) to turbo code encoder 204 may generate an output of approximately 3X bits (e.g., approximately 3X bits in M code blocks, 3X +12 bits, etc.). However, wireless communication device 202 is not able to transmit these 3X bits over the channel. Thus, wireless communication device 202 can use rate matching to down-convert from these 3X bits to a smaller number of bits for transmission over the channel.

It is to be appreciated that the turbo code encoder 204 can obtain any number of code blocks as inputs. For example, a larger number of code blocks may generate a larger systematic bit stream, a larger first type of parity bit stream, and a larger second type of parity bit stream. Regardless of the size of each of these streams output from turbo code encoder 204, wireless communication device 202 may process these outputs according to the following.

The wireless communication apparatus 202 can also include a bit type separator (type separator)206 that separates the bits output by the turbo code encoder 204 into different sets. The bit type separator 206 may distinguish the type of each bit output by the turbo code encoder 204; accordingly, the bit type separator 206 may determine whether the bit is a systematic bit, a first type of parity bit, or a second type of parity bit. For example, the bit-type separator 206 can utilize a priori information of the operation of the turbo code encoder 204 to interpret the type of each bit; according to this example, the turbo code encoder 204 may output the systematic bits, the first type of parity bits, and the second type of parity bits in a predetermined order known to the bit type separator 206. Thus, bit type separator 206 may use this information to identify systematic bits, first parity bits, and second parity bits. Upon identifying the bit type, bit type separator 206 may assemble the systematic bits into a first group, the first type of parity bits into a second group, and the second type of parity bits into a third group.

Further, wireless communication device 202 can include an interleaver 208 that interleaves bits for transmission. The interleaver 208 may randomly arrange the bits interleaved together; thus, interleaver 208 may output the Y bits input into interleaver 208 in the first sequence as a randomized second sequence of Y bits, where Y may be any integer. For example, interleaving may prevent transmission from burst errors. By way of example, interleaver 208 may be a Quadratic Permutation Polynomial (QPP) interleaver; however, the present invention is not limited thereto. The systematic bits that are grouped in the first group by the bit type separator 206 may be interleaved together by an interleaver 208 to arrange the bits in a non-contiguous manner. The interleaved systematic bits in the random sequence are designated as a first set of bits for transmission over the system. The interleaver 208 may also interleave the first parity bits of the second group of the set of bit type separators 206 together. In addition, interleaver 208 may also interleave the second parity bits of the second type in the third group, which are collected by bit type separator 206. Although one interleaver 208 is shown, it is understood that wireless communication apparatus 202 can include more than one interleaver, each of which can be substantially similar to interleaver 208 (e.g., one interleaver can interleave systematic bits, while a second interleaver can interleave first and second parity bits, a first interleaver can interleave systematic bits, a second interleaver can interleave first parity bits, a third interleaver can interleave second parity bits, etc.).

Wireless communication apparatus 202 can also include an interleaver (interleaver) 210 that interleaves the interleaved parity bits of the first type with the interleaved parity bits of the second type. Interleaver 210 creates a second set of bits for transmission over the channel based on the interleaved first type of parity bits and the interleaved second type of parity bits. The interleaver 210 organizes the interleaved first type parity bits and the interleaved second type parity bits according to a specific order; that is, the interleaver 210 alternates the interleaved first type of parity bits and the interleaved second type of parity bits. Thus, the output of interleaver 210 (e.g., the second set of bits transmitted over the channel) may be a sequence of interleaved parity bits of the first type and interleaved parity bits of the second type (e.g., every other bit is a parity bit of the first type, every other bit is a parity bit of the second type, etc.). The use of interleaver 210 causes the parity bits output by turbo code encoder 204 to be processed differently than the systematic bits output by turbo code encoder 204.

Wireless communication apparatus 202 may also include a mapper 212 and a transmitter 214. Mapper 212 may insert the first set of bits for transmission generated by interleaver 208 and the second set of bits for transmission output by interleaver 210 into a circular buffer. For example, the circular buffer may be a fixed size buffer. Thus, mapper 212 may first wrap bits from a first group (e.g., interleaved systematic bits) around a circular buffer. Mapper 212 may then wrap bits from a second group (e.g., interleaved parity bits of the first type and interleaved parity bits of the second type interleaved in an alternating manner) around the circular buffer. Although the use of a circular buffer is described, it is understood that mapper 212 may use a mapping of any bit in the first and second sets. Further, transmitter 214 may then transmit the bits in the circular buffer over the channel. Transmitter 214 may transmit the bits in the circular buffer (or any other mapping used by mapper 212), for example, to a different wireless communication device (not shown).

The circular buffer based rate matching described herein may involve the use of one interleaver (e.g., for evolved universal terrestrial radio access (E-UTRA)) during hybrid automatic repeat request (HARQ) bit insertion into the buffer. Conventional rate matching techniques, in contrast, typically use an additional channel interleaver, which increases the complexity associated with such techniques.

The following examples are provided for the purpose of illustration, it being understood that the invention is not limited thereto. According to this example, wireless communication device 202 can input 1000 bits (e.g., from code blocks 0 through M-1, etc.) to turbo code encoder 204. turbo code encoder 204 can process these 1000 bits and output approximately 3000 bits. The 3000 bits may include 1000 systematic bits, 1000 first type parity bits, and 1000 second type parity bits. Bit type separator 206 may identify the type of each of the 3000 bits and group 1000 systematic bits, 1000 first type parity bits, and 1000 second type parity bits into separate sets. In addition, interleaver 208 may randomly interleave the 1000 systematic bits together to generate a first set of bits for transmission. In addition, the interleaver 208 may interleave the 1000 first parity bits together. In addition, the interleaver 208 may interleave 1000 second parity bits together. Thereafter, interleaver 210 may combine the randomly interleaved 1000 first type parity bits and the randomly interleaved 1000 second type parity bits (e.g., first type parity bits, second type parity bits, etc.) in an alternating manner to generate a second set of bits for transmission, wherein the second set of bits comprises 2000 bits. In addition, mapper 212 may insert bits in a circular buffer. According to an example, 2000 bits may be sent by wireless communication device 202 (e.g., 2000 bits may be inserted into a circular buffer). Thus, mapper 212 may insert 1000 interleaved systematic bits from the first group into a circular buffer (e.g., mapper 212 may start at a particular location in the circular buffer and increment a sequence of 1000 interleaved systematic bits clockwise (or counterclockwise), etc.). Further, mapper 212 may insert the first 1000 bits from the 2000 bits contained in the second group into the circular buffer (e.g., mapper 212 may continue to add a sequence of 1000 parity bits into the circular buffer from the end of the interleaved sequence of systematic bits in a similar manner, and so on); thus, the remaining 1000 bits need not be inserted into the circular buffer by mapper 212 (e.g., because the circular buffer is full). Further, the transmitter 214 may transmit the 2000 bits contained in the circular buffer over the channel. By utilizing system 200, a total of 1000 systematic bits can be transmitted by transmitter 214 since systematic bits can be treated preferentially over parity bits (e.g., a system can be considered more important than parity bits). In addition, 500 first type parity bits and 500 second type parity bits may be transmitted through the remaining resources (e.g., equal weights may be provided for both the first type parity bits and the second type parity bits, etc.). Although the above describes using equal weights for the first and second parity bits, it is understood that any unequal weight may be used between the first and second parity bits.

Further, system 200 supports transmitting multiple transport blocks. Therefore, if there are a plurality of transport blocks, rate matching can be achieved on a per transport block basis.

Referring to fig. 3, an exemplary diagram 300 of using a circular buffer based rate matching algorithm is shown. At 302, transport blocks may be input. The transport block may be divided into M code blocks (e.g., code block 0304, code block 1306,.. code block M-1308), where M may be any integer. The M code blocks may be input into the turbo encoder 310 to generate M encoded blocks (e.g., encoded block 0312, encoded block 1314. Each of the encoded blocks 312 and 316 may be generated from a respective one of the code blocks 304 and 308. Each of the encoding blocks 312 and 316 generated from the turbo encoder 310 may include systematic bits, first type parity bits, and second type parity bits. Thus, the coding block 0312 may include systematic bits 0318, first parity bits 0320 and second parity bits 0322; the coding block 1314 may include systematic bits 1324, first parity bits 1326, and second parity bits 1328; the encoded block M-1316 may include systematic bits M-1330, parity bits of a first type M-1332, and parity bits of a second type M-1334.

Each type of these bits can then be identified and grouped. Thus, systematic bits 0318, systematic bits 1324. The first parity bits 0320, 1326, 1332 may be identified as first parity bits and grouped into a second group. Further, the second parity bits 0322, 1328, M-1334 may be identified as second parity bits and combined into a third group.

Systematic bits 318, 324, and 330 may be input into an interleaver 336 to randomize their sequence. In addition, the parity bits 320, 326, and 332 of the first type may be input into an interleaver 338 to randomize the sequence thereof. In addition, the second parity bits 322, 328, and 334 may be input to an interleaver 340 to randomize their sequence. As shown, separate interleavers 336, 338, and 340 may be used for systematic bits 318, 324, 330, first parity bits 320, 326, 332, and second parity bits 322, 328, 334. According to another example (not shown), a common interleaver may be used for the systematic bits 318, 324, 330, the first parity bits 320, 326, 332, and the second parity bits 322, 328, 334. According to another example, interleaver 336 may interleave systematic bits 318, 324, and 330, while different interleavers (not shown) may interleave first parity bits 320, 326, and 332 together and may interleave second parity bits 322, 328, and 334 together (e.g., the interleaving of the first parity bits and the second parity bits may be independent of each other).

The output of interleaver 336 may be a randomized sequence of systematic bits 342. In addition, the outputs of interleavers 338 and 340 may be interleaved together in an alternating manner to generate a sequence 344 of first and second parity bits. Thereafter, the sequence of systematic bits 342 and the sequence of first and second parity bits 344 may be inserted into a circular buffer 346. For example, the systematic bit sequence 342 can be first inserted into the circular buffer 346, and then the sequence 344 of the first parity bits and the second parity bits can be inserted into the circular buffer 346 using any remaining space. Thus, the filling of the circular buffer 346 may start at a particular location with the systematic bit sequence 342 and proceed clockwise (or counterclockwise) to fill the first sector 348 of the circular buffer 346. If the systematic bit sequence 342 can be completely inserted into the circular buffer 346, the insertion of the sequence of first and second parity bits 344 into the remaining sectors 350 and 352 of the circular buffer 346 can begin. Although shown as separate from each other, it is understood that the sectors 350 and 352 may be substantially similar to each other and/or may be combined into one common sector (not shown) of the circular buffer 346. The sequences 344 of first and second parity bits may continue to be inserted around the circular buffer 346 until the end of each sequence 344 is reached or the buffer 346 has no remaining space available.

Referring to fig. 4-6, methodologies are illustrated that facilitate circular buffer based rate matching in a wireless communication environment. While, for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more embodiments, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more embodiments.

Referring to fig. 4, illustrated is a methodology 400 that facilitates rate matching in a wireless communication environment. At 402, systematic bits, first type parity bits, and second type parity bits from an encoder (e.g., a turbo encoder, etc.) may be grouped into different groups. For example, a transport block may be divided into multiple code blocks. A turbo code may be applied to each of the plurality of code blocks to generate a plurality of encoded blocks. The encoded blocks output by the turbo code may each include systematic bits, first type parity bits, and second type parity bits. Further, each of these bit types may be organized such that the bits are divided into different groups. At 404, the systematic bits, the first type of parity bits, and the second type of parity bits are interleaved in respective different groups. The systematic bits can be interleaved together to randomize the ordering of the systematic bits; the first type of parity bits may be interleaved together to randomize the ordering of the first type of parity bits; the second type of parity bits may be interleaved together to randomize the ordering of the second type of parity bits; thus, 3 randomized orderings (e.g., one for each systematic bit, first parity bit, and second parity bit, respectively) may be generated. At 406, the interleaved parity bits of the first type may be interleaved with the interleaved parity bits of the second type. For example, the randomized first type of parity bits and the randomized second type of parity bits can be combined in an alternating manner, where each bit in the interleaved output alternates between either the first type of parity bits or the second type of parity bits. According to another example, the randomized first parity bits and the randomized second parity bits can be combined using any different predefined pattern. At 408, the interleaved systematic bits can be inserted into a circular buffer followed by the interleaved and interleaved parity bits of the first type and parity bits of the second type. Thus, the interleaved systematic bits can be preferentially selected among the entries contained in the circular buffer. Furthermore, after all systematic bits are inserted into the circular buffer, the interleaved parity bits of the first type and parity bits of the second type can be incorporated into the circular buffer using any available resources. At 410, the bits inserted into the circular buffer are transmitted. Thus, for example, if all of the systematic bits and a portion of the first and second parity bits are incorporated into the circular buffer, then these incorporated bits may be transmitted via the channel while the remaining portion of the first and second parity bits may not be transmitted; however, if all the systematic and all the first and second parity bits are incorporated in the circular buffer, all these bits can be transmitted via the channel.

Turning to fig. 5, illustrated is a methodology 500 that facilitates preferentially processing systematic bits in connection with circular buffer based rate matching in a wireless communication environment. At 502, systematic bits can be identified from at least one encoded block output from an encoder (e.g., a turbo encoder, etc.). For example, the systematic bits can be identified using a priori information of the format of the encoded blocks generated from the encoder. At 504, the identified systematic bits may be collected. At 506, the collected systematic bits can be interleaved together to generate a randomized sequence of systematic bits. At 508, the randomized sequence of systematic bits can be transmitted prior to transmitting the parity bits included in the at least one encoded block output by the encoder. For example, the parity bits may include a first type of parity bit and a second type of parity bit. For example, a randomized sequence of systematic bits can be inserted into the circular buffer prior to incorporating the parity bits.

Referring now to fig. 6, illustrated is a methodology 600 that facilitates employing rate matching utilizing a circular buffer in a wireless communication environment. At 602, parity bits of a first type and parity bits of a second type may be identified from at least one encoded block output from an encoder (e.g., a turbo encoder, etc.). For example, the first type of parity bits and the second type of parity bits may be identified using a priori information of the format of the encoded block generated from the encoder. At 604, the identified first type of parity bits may be combined into a first set and the identified second type of parity bits may be combined into a second set. At 606, the collected first type of parity bits may be interleaved together to generate a randomized sequence of first type of parity bits. At 608, the collected second type of parity bits may be interleaved together to generate a randomized sequence of second type of parity bits. At 610, the randomized sequence of first type of parity bits and the randomized sequence of second type of parity bits can be interleaved in an alternating manner to generate an interleaved sequence of first type of parity bits and second type of parity bits. According to another example, the randomized sequence of the first type of parity bits and the randomized sequence of the second type of parity bits can be combined using any different predefined pattern. At 612, at least a portion of the interleaved sequence of the first type of parity bits and the second type of parity bits may be transmitted using available resources after transmitting the complete sequence of systematic bits contained in the at least one encoded block output by the encoder.

It can be appreciated that, in accordance with one or more aspects described herein, inferences can be made regarding utilizing circular buffer based rate matching. As used herein, the term to "infer" or "inference" refers generally to the process of reasoning about or inferring states of the system, environment, and/or user from a set of observations as captured via events and/or data. Inference can be employed to identify a specific context or action, or can generate a probability distribution over states, for example. Such inference can be probabilistic-that is, the computation of a probability distribution over states of interest based on a consideration of data and events. Inference can also refer to techniques employed for composing higher-level events from a set of events and/or data. Such inference results in the construction of new events or actions from a set of observed events and/or stored event data, whether or not the events are correlated in close temporal proximity, and whether the events and data come from one or several event and data sources.

According to an example, one or more of the methods described above can include making inferences pertaining to interpreting a bit type (e.g., systematic, first parity, second parity). By way of another example, inferences can be made regarding determining how to combine (e.g., interleave) the first type of parity bit and the second type of parity bit; for example, each parity bit type may be assigned a different weight based on such inference. It will be appreciated that the above-described examples are exemplary in nature and are not intended to limit the number of inferences that can be made or the manner in which such inferences are made in conjunction with the various embodiments and/or methods described herein.

Fig. 7 is an illustration of an access terminal 700 that facilitates performing circular buffer based rate matching in a wireless communication system. Access terminal 700 comprises a receiver 702 that receives a signal from, for instance, a receive antenna (not shown), performs typical actions thereon (e.g., filters, amplifies, downconverts, etc.) the received signal, and digitizes the conditioned signal to obtain samples. Receiver 702 can be, for example, an MMSE receiver, and can comprise a demodulator 704 that can demodulate received symbols and provide them to a processor 706 for channel estimation. Processor 706 can be a processor dedicated to analyzing information received by receiver 702 and/or generating information for transmission by a transmitter 716, a processor that controls one or more components of access terminal 700, and/or a controller that both analyzes information received by receiver 702, generates information for transmission by transmitter 716, and controls one or more components of access terminal 700.

The access terminal 700 can additionally comprise memory 708 that is operatively coupled to the processor 706 and that stores the following data: data to be transmitted, data received, and any other suitable information related to performing the various actions and functions described herein. Memory 708 may additionally store protocols and/or algorithms associated with circular buffer based rate matching.

It will be appreciated that the data store (e.g., memory 708) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, the non-volatile memory may include: read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable PROM (EEPROM), or flash memory. The volatile memory may include: random Access Memory (RAM), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as Synchronous RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct bus RAM (DRRAM). The memory 708 of the subject systems and methods is intended to comprise, without being limited to, these and any other suitable types of memory.

Receiver 702 is also operatively coupled to interleaver 710 and/or interleaver 712, which may be substantially similar to interleaver 208 of fig. 2 and interleaver 210 of fig. 2. Further, although not shown, it is understood that access terminal 700 can comprise: a turbo code encoder substantially similar to turbo code encoder 204 of fig. 2; a bit-type separator substantially similar to the bit-type separator 206 of fig. 2; and/or a mapper substantially similar to mapper 212 of fig. 2. Interleaver 710 may interleave the systematic bits contained in the coded block together to generate a first randomized sequence of systematic bits. Thereafter, the first randomized sequence of systematic bits can be mapped to (e.g., inserted into, etc.) a circular buffer. In addition, the interleaver 710 may interleave the first type of parity bits together and may interleave the second type of parity bits together. Thereafter, the interleaver 712 can create a second randomized sequence comprising interleaved first type parity bits and second type parity bits interleaved with each other in an alternating manner. In addition, a second randomized sequence of interleaved and interleaved first and second parity bits can be incorporated into the circular buffer such that bits from the first randomized sequence are transmitted first followed by bits from the second randomized sequence. Access terminal 700 further comprises a modulator 714 and a transmitter 716, where transmitter 716 is utilized to transmit a signal to, for instance, a base station, another access terminal, etc. Although shown as being separate from the processor 706, it is to be understood that the interleaver 710, interleaver 712, and/or modulator 714 can be part of the processor 706 or multiple processors (not shown).

Fig. 8 is an illustration of a system 800 that facilitates performing circular buffer based rate matching in a wireless communication environment. System 800 includes a base station 802 (e.g., an access point) having a receiver 810 that receives signals from one or more access terminals 804 via a plurality of receive antennas 806 and a transmitter 824 that transmits signals to the one or more access terminals 804 via a transmit antenna 808. Receiver 810 can receive information from receive antennas 806 and is operatively associated with a demodulator 812 that demodulates received information. Demodulated symbols can be analyzed by a processor 814 that can be similar to the processor described with respect to fig. 7, which can be coupled to a memory 816 that can store data to be transmitted to or received from access terminal 804 (or a disparate base station (not shown)), and/or any other suitable information related to performing the various acts and functions described herein. Processor 814 is further coupled to an interleaver 818 that generates a randomized sequence of systematic bits, a randomized sequence of first parity bits, and a randomized sequence of second parity bits. For example, systematic bits, parity bits of a first type, and parity bits of a second type may be included in at least one encoded block output by a turbo code encoder.

Interleaver 818 is operatively coupled to an interleaver 820 that combines the randomized sequence of the first type of parity bits and the randomized sequence of the second type of parity bits to generate an interleaved randomized sequence of the first type of parity bits and the second type of parity bits. For example, interleaver 820 may alternate the first type of parity bits and the second type of parity bits in the output sequence of first type of parity bits and second type of parity bits generated therefrom. Further, although not shown, it is understood that base station 802 may include: a turbo code encoder substantially similar to turbo code encoder 204 of fig. 2; a bit-type separator substantially similar to the bit-type separator 206 of fig. 2; and/or a mapper substantially similar to mapper 212 of fig. 2. Interleaver 818 and interleaver 820 (and/or a mapper (not shown)) may provide data to be sent to a modulator 822. For example, the data to be transmitted may be bits surrounding a circular buffer. According to this example, the randomized sequence of systematic bits can first wrap around the circular buffer, and then the interleaved randomized sequence of first and second parity bits can wrap around the circular buffer. Thus, depending on resource availability, some or all of the systematic bits may be transmitted. In addition, if all of the systematic bits are transmitted, a part or all of the first type parity bits and the second type parity bits may be transmitted. A modulator 822 can multiplex the frame for transmission by a transmitter 826 through antenna 808 to access terminals 804. Although shown as being separate from the processor 814, it is to be understood that interleaver 818, interleaver 820, and/or modulator 822 can be part of processor 814 or a number of processors (not shown).

Fig. 9 illustrates an exemplary wireless communication system 900. The wireless communication system 900 depicts one base station 910 and one access terminal 950 for sake of brevity. However, it is to be appreciated that system 900 can include more than one base station and/or more than one access terminal, wherein additional base stations and/or access terminals can be substantially similar or different from example base station 910 and access terminal 950 described below. Moreover, it is to be appreciated that base station 910 and/or access terminal 950 can employ the systems (fig. 1-2, 7-8, and 10) and/or methods (fig. 4-6) described herein to facilitate wireless communication there between.

At base station 910, traffic data for a number of data streams is provided from a data source 912 to a Transmit (TX) data processor 914. According to an example, each data stream can be transmitted over a respective antenna. TX data processor 914 formats, codes, and interleaves the traffic data stream based on a particular coding scheme selected for that data stream to provide coded data.

The coded data for each data stream can be multiplexed with pilot data using Orthogonal Frequency Division Multiplexing (OFDM) techniques. Additionally or alternatively, the pilot symbols may be Frequency Division Multiplexed (FDM), Time Division Multiplexed (TDM), or Code Division Multiplexed (CDM). The pilot data is typically a known data pattern that is processed in a known manner and can be used at access terminal 950 to estimate channel response. The multiplexed pilot and coded data for each data stream can be modulated (e.g., symbol mapped) based on a particular modulation scheme (e.g., binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), M-phase-shift keying (M-PSK), M-quadrature amplitude modulation (M-QAM), etc.) selected for that data stream to provide modulation symbols. The data rate, coding, and modulation for each data stream can be determined by instructions performed or provided by processor 930.

Modulation symbols for the data streams can be provided to a TX MIMO processor 920, which can also process the modulation symbols (e.g., for OFDM). TX MIMO processor 920 then forwards to N_TTransmitters (TMTR)922a through 922t provide N_TThe stream of symbols is modulated. In various embodiments, the TXMIMO processor 920 applies beamforming weights to the symbols of the data streams and to the antenna from which the symbol is being transmitted.

Each transmitter 922 receives and processes a respective symbol stream to provide one or more analog signals, and further conditions (e.g., amplifies, filters, and upconverts) the analog signals to provide a modulated signal suitable for transmission over the MIMO channel. In addition, from N respectively_TN transmitted from transmitters 922a through 922t by antennas 924a through 924t_TThe signal is modulated.

At access terminal 950, over N_RAntennas 952a through 952r receive the transmitted modulated signals and provide a received signal from each antenna 952 to a respective receiver (RCVR)954a through 954 r. Each receiver 954 conditions (e.g., filters, amplifies, and downconverts) a respective signal, digitizes the conditioned signal to provide samples, and further processes the samples to provide a corresponding "received" symbol stream.

RX data processor 960 may select from N_RReceiver 954 receives N_RIndividual symbol streams and processing N based on particular receiver processing techniques_RA received symbol stream to provide N_TA "detected" symbol stream. RX data processor 960 can demodulate, deinterleave, and decode each detected symbol stream to recover the traffic data for the data stream. The processing by RX data processor 960 is complementary to that performed by TX MIMO processor 920 and TX data processor 914 at base station 910.

Processor 970 can periodically determine which available technologies to utilize as described above. Further, processor 970 can formulate a reverse link message comprising a matrix index portion and a rank value portion.

The reverse link message may comprise various information regarding the communication link and/or the received data stream. The reverse link message can be processed by a TX data processor 938, modulated by a modulator 980, conditioned by transmitters 954a through 954r, and transmitted back to base station 910, where TX data processor 938 also receives traffic data for a number of data streams from a data source 936.

At base station 910, the modulated signals from access terminal 950 are received by antennas 924, conditioned by receivers 922, demodulated by a demodulator 940, and processed by a RX data processor 942 to extract the reverse link message transmitted by access terminal 950. Further, processor 930 can process the extracted message to determine which precoding matrix to use for determining the beamforming weights.

Processors 930 and 970 can direct (e.g., control, coordinate, manage, etc.) operation at base station 910 and access terminal 950, respectively. Respective processors 930 and 970 can be associated with memory 932 and 972 that store program codes and data. Processors 930 and 970 can also perform computations to derive frequency and impulse response estimates for the uplink and downlink, respectively.

In an aspect, logical channels may be divided into control channels and traffic channels. The logical control channels include: broadcast Control Channel (BCCH), which is DL channel for broadcasting system control information. Further, the logical control channels may include: a Paging Control Channel (PCCH), which is a DL channel for transmitting paging information. Further, the logical control channels may include: multicast Control Channel (MCCH), which is a point-to-multipoint DL channel used for transmitting Multimedia Broadcast and Multicast Service (MBMS) scheduling and control information for one or several MTCHs. Typically, this channel is only used by UEs receiving MBMS (e.g. old MCCH + MSCH) after the Radio Resource Control (RRC) connection is established. Further, the logical control channels may include: dedicated Control Channel (DCCH), which is a point-to-point bi-directional channel that transmits dedicated control information and is used by UEs having an RRC connection. In an aspect, the logical traffic channels may include a Dedicated Traffic Channel (DTCH), which is a point-to-point bi-directional channel dedicated to one UE for transmitting user information. Further, the logical traffic channels may include a Multicast Traffic Channel (MTCH), which is a point-to-multipoint DL channel for transmitting traffic data.

In an aspect, the transport channels are divided into DL and UL. The DL transport channel includes: a Broadcast Channel (BCH), a downlink shared data channel (DL-SDCH) and a Paging Channel (PCH). The PCH may be used to support UE power saving (e.g., indication by the network of a Discontinuous Reception (DRX) cycle to the UE, etc.) by broadcasting over the entire cell and mapping to physical layer (PHY) resources for other control/traffic channels. The UL transport channels include a Random Access Channel (RACH), a request channel (REQCH), an uplink shared data channel (UL-SDCH), and a plurality of PHY channels.

The PHY channels include a set of DL channels and UL channels. For example, DL PHY channels include: such as a common pilot channel (CPICH), Synchronization Channel (SCH), Common Control Channel (CCCH), Shared DL Control Channel (SDCCH), Multicast Control Channel (MCCH). -, Shared UL Allocation Channel (SUACH), acknowledgement channel (ACKCH), DL physical shared data channel (DL-PSDCH), UL Power Control Channel (UPCCH), Paging Indicator Channel (PICH), and/or Load Indicator Channel (LICH). By way of another example, the UL PHY channels include: such as a Physical Random Access Channel (PRACH), a Channel Quality Indication Channel (CQICH), an acknowledgement channel (ACKCH), an Antenna Subset Indication Channel (ASICH), a shared request channel (SREQCH), an UL physical shared data channel (UL-PSDCH), and/or a broadband pilot channel (BPICH).

It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.

When the embodiments are implemented in software, firmware, middleware or microcode, program code or code segments, they may be stored in a machine-readable medium, such as a storage component. A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted using any suitable means including memory sharing, message passing, token passing, network transmission, etc.

For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in memory units and executed by processors. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

Referring to fig. 10, illustrated is a system 1000 that enables employing rate matching in a wireless communication environment. For example, system 1000 can reside at least partially within a base station. According to another example, system 1000 can reside at least partially within an access terminal. It is to be appreciated that system 1000 can be represented as including functional blocks, which can be functional blocks that represent functions implemented by a processor, software, or combination thereof (e.g., firmware). System 1000 includes a logical grouping 1002 of electrical components that can act in conjunction. For instance, logical grouping 1002 can include an electrical component for interleaving systematic bits collected from at least one encoded block output by an encoder 1004. Moreover, logical grouping 1002 can include an electrical component for interleaving parity bits of a first type collected from at least one encoded block 1006. Moreover, logical grouping 1002 can comprise an electrical component for interleaving parity bits of a second type collected from at least one encoded block 1008. Logical grouping 1002 can also include an electrical component for interleaving the interleaved first type of parity bits with the interleaved second type of parity bits 1010. For example, the interleaved systematic bits may first wrap around the circular buffer, and the interleaved parity bits of the first type and parity bits of the second type may then wrap around the circular buffer. According to this example, bits surrounding the circular buffer may be transmitted via the channel, and the remaining bits not contained in the circular buffer may not be transmitted. Additionally, system 1000 can include a memory 1012 that retains instructions for executing functions associated with electrical components 1004, 1006, 1008, and 1010. While shown as being external to memory 1012, it is to be understood that one or more of electrical components 1004, 1006, 1008, and 1010 can exist within memory 1012.

What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described in this application are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim.

Claims

1. A method that facilitates rate matching in a wireless communication environment, comprising:

dividing the systematic bits, the first type of parity bits, and the second type of parity bits from the encoder into different groups;

interleaving the systematic bits, the first parity bits, and the second parity bits in each of the different groups, respectively;

interleaving the interleaved first parity bits with the interleaved second parity bits;

inserting the interleaved systematic bits into a circular buffer, followed by interleaving and interleaving the first type of parity bits and the second type of parity bits;

transmitting the bits inserted into the circular buffer.

2. The method of claim 1, further comprising:

applying a turbo code to at least one code block to generate at least one coded block, wherein the at least one coded block comprises the systematic bits, the first type of parity bits and the second type of parity bits to be separated.

3. The method of claim 2, further comprising:

identifying a type of each bit in the at least one encoded block, wherein the type is one of systematic, first type parity, or second type parity.

4. The method of claim 1, further comprising:

interleaving the systematic bits together to randomize an ordering of the systematic bits;

interleaving the first type of parity bits together to randomize an ordering of the first type of parity bits;

interleaving the second type of parity bits together to randomize an ordering of the second type of parity bits.

5. The method of claim 1, interleaving the interleaved parity bits of the first type with the interleaved parity bits of the second type further comprising:

the randomly ordered first type of parity bits are combined with the randomly ordered second type of parity bits in an alternating manner, wherein each bit in the sequence of interleaved and interleaved first type of parity bits and second type of parity bits alternates between the first type of parity bits and the second type of parity bits.

6. The method of claim 1, interleaving the interleaved parity bits of the first type with the interleaved parity bits of the second type further comprising:

the randomly ordered first parity bits are combined with the randomly ordered second parity bits according to a predefined pattern.

7. The method of claim 1, further comprising:

inserting all of the interleaved systematic bits into the circular buffer before inserting a first bit of the interleaved and interleaved parity bits of the first type and the parity bits of the second type.

8. A wireless communications apparatus, comprising:

a memory for holding instructions related to:

identifying systematic bits, first parity bits and second parity bits from at least one encoded block output from an encoder;

collecting the identified systematic bits;

interleaving the collected systematic bits together to generate a randomized sequence of systematic bits;

collecting the identified parity bits of the first type;

interleaving the collected first type of parity bits together to generate a randomized sequence of first type of parity bits;

collecting the identified parity bits of the second type;

interleaving the collected second type of parity bits together to generate a randomized sequence of second type of parity bits;

interleaving the randomized sequence of the first type of parity bits and the randomized sequence of the second type of parity bits to generate an interleaved sequence of first type of parity bits and second type of parity bits;

inserting a randomized sequence of said systematic bits into a circular buffer followed by an interleaved sequence of said first type of parity bits and said second type of parity bits;

transmitting the bits inserted into the circular buffer;

a processor, coupled to the memory, to execute the instructions retained in the memory.

9. The wireless communications apparatus of claim 8, wherein the memory further retains instructions related to: interleaving the randomized sequence of the first type of parity bits and the randomized sequence of the second type of parity bits in an alternating manner to generate an interleaved sequence of the first type of parity bits and the second type of parity bits.

10. The wireless communications apparatus of claim 8, wherein the memory further retains instructions related to: after transmitting all bits in the randomized sequence of systematic bits, at least a portion of the interleaved sequence of first and second parity bits is transmitted using available resources.

11. The wireless communications apparatus of claim 8, wherein the memory further retains instructions related to: transmitting the randomized sequence of systematic bits before transmitting the first bit in the interleaved sequence of first and second parity bits.

12. The wireless communications apparatus of claim 8, wherein the memory further retains instructions related to: applying a turbo code to at least one code block to generate the at least one coded block, wherein the at least one coded block comprises the systematic bits, the first type of parity bits and the second type of parity bits to be separated.

13. The wireless communications apparatus of claim 12, wherein the memory further retains instructions related to: identifying a type of each bit in the at least one encoded block, wherein the type is one of systematic, first type parity, or second type parity.

14. The wireless communications apparatus of claim 8, wherein the memory further retains instructions related to: inserting all bits of the randomized sequence of systematic bits into the circular buffer prior to inserting a first bit of the interleaved sequence of first and second parity bits into the circular buffer, wherein the insertion of the systematic bits and the first and second parity bits is dependent on available space in the circular buffer.

15. The wireless communications apparatus of claim 14, wherein the memory further retains instructions related to: transmitting the bits inserted into the circular buffer; disabling transmission of bits that could not be inserted into the circular buffer.

16. A wireless communications apparatus that enables employing rate matching in a wireless communication environment, comprising:

means for interleaving systematic bits collected from at least one coded block output from the encoder;

means for interleaving parity bits of a first type collected from the at least one encoded block;

means for interleaving parity bits of a second type collected from the at least one encoded block;

means for interleaving the interleaved parity bits of the first type with the interleaved parity bits of the second type.

17. The wireless communications apparatus of claim 16, further comprising:

means for identifying a type of each bit in the at least one encoded block, wherein the type is one of systematic, first type parity, or second type parity;

means for dividing each bit into a respective set according to the identified type.

18. The wireless communications apparatus of claim 16, further comprising:

means for generating the at least one encoded block from the input at least one code block.

19. The wireless communications apparatus of claim 16, further comprising:

means for incorporating the interleaved systematic bits into a circular buffer;

means for incorporating the interleaved and interleaved parity bits of the first type and parity bits of the second type into the circular buffer after incorporating the interleaved systematic bits into the circular buffer.

20. The wireless communications apparatus of claim 19, further comprising:

means for transmitting the bits incorporated in the circular buffer over a channel.

21. The wireless communications apparatus of claim 16, further comprising:

means for interleaving the interleaved first type of parity bits and the interleaved second type of parity bits in an alternating manner, wherein each bit in a sequence of interleaved and interleaved first type of parity bits and second type of parity bits alternates between the first type of parity bits and the second type of parity bits.

22. The wireless communications apparatus of claim 16, further comprising:

means for interleaving the interleaved parity bits of the first type and the interleaved parity bits of the second type according to a predefined pattern.

23. A machine-readable medium having stored thereon machine-executable instructions for:

combining the identified systematic bits into a first set, combining the identified second parity bits into a second set, and combining the identified second parity bits into a third set;

interleaving the randomized sequence of the first type of parity bits and the randomized sequence of the second type of parity bits in an alternating manner to generate an interleaved sequence of the first type of parity bits and the second type of parity bits;

transmitting the bits inserted into the circular buffer.

24. The machine-readable medium of claim 23, the machine-executable instructions further comprise:

transmitting the randomized sequence of systematic bits before transmitting bits from the interleaved sequence of the first type of parity bits and the second type of parity bits.

25. The machine-readable medium of claim 23, the machine-executable instructions further comprise:

after transmitting the ensemble of the randomized sequence of systematic bits, at least a portion of the interleaved sequence of first and second parity bits is transmitted using available resources.

26. The machine-readable medium of claim 23, the machine-executable instructions further comprise:

applying a turbo code to at least one code block to generate the at least one coded block, wherein the at least one coded block comprises the systematic bits, the first type of parity bits and the second type of parity bits to be separated.

27. The machine-readable medium of claim 26, the machine-executable instructions further comprise:

28. The machine-readable medium of claim 23, the machine-executable instructions further comprise:

inserting the whole of the randomized sequence of systematic bits into the circular buffer prior to inserting a first bit of the interleaved sequence of first and second parity bits, wherein the insertion of the systematic bits and the first and second parity bits is dependent on available space in the circular buffer.

29. The machine-readable medium of claim 28, the machine-executable instructions further comprise:

transmitting the bits inserted into the circular buffer;

disabling transmission of bits that could not be inserted into the circular buffer.

30. An apparatus in a wireless communication system, comprising:

a processor to:

dividing the systematic bits, the first parity bits and the second parity bits into different groups;

interleaving the interleaved first type of parity bits with the interleaved second type of parity bits;

transmitting the bits inserted into the circular buffer.