HK1140066B - Convolutional turbo coding method and apparatus for implementing the coding method - Google Patents

Description

Convolutional Turbo coding method and equipment for realizing coding method

Technical Field

The invention relates to a coding method in wireless mobile communication, in particular to a convolutional Turbo coding method and equipment for realizing the method.

Background

Mobile Wi MAX (World wide Interoperability for Microwave Access) is a broadband Access technology that uses wireless instead of wired implementation of "last kilometer". The mobile broadband access system integrates mobile equipment and a fixed broadband network, and provides convenient and high-speed mobile broadband connection by adopting a broadband wireless access technology and a flexible and variable network structure in a large range. The Wi MAX technique is based on the IEEE802.16 series of standards proposed for the microwave and millimeter wave bands, and is a mobile Wi MAX standard that was introduced after the 802.16d fixed Wi MAX standard. The aim is to support the mobility characteristics of broadband access on the basis of the research of fixed wireless access standards. Convolutional Turbo Codes (CTCs) are a class of Turbo codes that are encoded using several convolutional schemes. Convolutional Turbo codes are included in the 802.16 and DVB-RCS standards due to their high performance error correction characteristics.

Fig. 1 is a block diagram illustrating a CTC encoder according to the related art. The encoder shown in fig. 1 may include 1/3CTC encoder 101, interleaver 102, and puncturer 103. As shown in fig. 1, input information bits are first input 1/3CTC encoder 101. Here, the number of bits of information and check bits output after being encoded by the 1/3CTC encoder 101 is 3 times the number of bits of information. The encoded data is then interleaved by interleaver 102. The puncturer 103 then punctures the interleaved data according to the required transmission rate, i.e., selects the data bits to be transmitted, resulting in a coded bit sequence, thereby completing the encoding process.

Specifically, in the 1/3CTC encoder 101, a duo binary Recursive Systematic convolutional code (duo binary Recursive Systematic convolutional code) is used as its component code (coherent code). As shown in fig. 1, 1/3CTC encoder 101 may include CTC interleaver 105 and constituent encoder 104, where inputs a and B of CTC interleaver 105 represent input information bits, which need to be performed twiceAnd (5) encoding. First, information bits A, B are directly subjected to duo-binary cyclic recursive systematic convolutional encoding, resulting in a group of information bits A_iAnd B_iSimultaneously inputting the data into the convolutional encoder for encoding to obtain a check sequence Y₁，W₁. Then, the information bits A and B are interleaved by the CTC interleaver 105, and then the interleaved sequence is subjected to second component coding, so that the interleaved information bits A_jAnd B_jSimultaneously inputting the data into a convolutional encoder of a duo-binary cyclic recursive system to obtain a check sequence Y₂And W₂. Each coding block input to the encoder contains k information bits or N pairs of information bits, i.e., k is 2 × N, where k is a multiple of 8, N is a multiple of 4, and 32 ≦ N ≦ 4096.

As shown in block 106, the interleaver 102 may include a symbol segmentation (symbol segmentation) module, a sub-block interleaving (sub-block interleaving) module, and a symbol grouping (symbol grouping) module. The bits generated after encoding are distributed by the symbol partitioning module to six sub-blocks, which in turn are A, B, Y as described above₁、Y₂、W₁And W₂. And interleaving the six sub-blocks in each sub-block through a sub-block interleaving module, wherein the interleaving sequence adopted by each sub-block is the same. Let A, B, Y₁、Y₂、W₁And W₂The bit sequences obtained after the six blocks are respectively interleaved by sub-blocks are recorded as A ', B ' and Y '₁、Y’₂、W’₁And W'₂Then there is

A’，B’，Y’₁，Y’₂，W’₁，W’₂＝A’₀，A’₁，......，A’_N-1；B’₀，B’₁，......，B’_N-1；Y’_1，0，Y’_1，1，......，Y’_1，N-1；Y’_2，0，Y’_2，1，......，Y’_2，N-1；W’_1，0，W’_1，1，......，W’_1，N-1；W’_2，0，W’_2，1，......，W’_2，N-1。

Fig. 2 shows a block diagram of an implementation of a sub-block interleaving module implementing sub-block interleaving according to the prior art. As shown in fig. 2, the output of each sub-block interleave is assembled onto a series of sequences. Outputting A sub-block and B sub-block and then alternately outputting Y by using the symbol grouping module 106 of FIG. 1₁And Y₂Two sub-blocks and W₁And W₂Two sub-blocks. Then after symbol grouping, the output sequence is A'₀，A’₁，......，A’_N-1；B’₀，B’₁，......，B’_N-1；Y’_1，0，Y’_2，0，Y’_1，1，Y’_2，1，......，Y’_1，N-1，Y’_2，N-1；W’_1，0，W’_2，0，W’_1，1，W’_2，1，......，W’_1，N-1，W’_2，N-1。

In conventional convolutional turbo code design, the performance of bit reliability in high order modulation is not considered. Here, reliability refers to an average distance between a constellation point including a certain mapped bit of 0 and a constellation point including the mapped bit of 1 in a modulation constellation. The greater the distance, the higher the reliability of the mapped bit.

In a mobile communication system, in order to increase a data transmission rate without increasing a bandwidth, a scheme of M-order quadrature amplitude modulation M-QAM) is generally adopted. But the high order modulation is itself an unequal error protection modulation, and the Bit Error Rate (BER) performance of the individual bits mapped onto the M-QAM symbols is different for M > 4. The energy of the points located in the inner periphery of the constellation diagram is small, and the symbols are easy to fade, and the reliability of the bits forming the symbols is poor. In contrast, the bit reliabilities constituting the peripheral points are better.

Fig. 3 shows a schematic illustration of the above-described situation in the prior art. Wherein the mapping order of the bits is i₁i₂q₁q₂，i₁Taking 0 and 1 corresponds to the right and left half planes respectivelyConstellation point of i₂Taking 0 and 1 corresponds to the constellation points in the middle and on both sides, respectively. Thus, i₁The average distance between the constellation point taking 1 and the constellation point taking 0 is larger than i₂Then at the receiving end i₁Is more reliable than i₂The reliability of (2).

Fig. 4 shows a block diagram of an implementation of a duobinary cyclic recursive systematic convolutional code in a constituent encoder in an 1/3 convolutional turbo code according to the prior art. As shown in fig. 4, when convolutional turbo coding is performed, a bit a is input_i(401) And an input bit B_i(402) As a set of inputs to the 1/3CTC encoder, check bits Y_iAnd W_iEmbodying the information bit A_iAnd information bit B_iThe union information of (1). In such duobinary encoding, bit A_iAnd bit B_iAre to be regarded as a whole and treated as a group unit. In conventional convolutional turbo code design, if bit a_iIs mapped to a bit of high reliability, bit B_iAre also mapped to bits of high reliability. If bit A_iMapped to a bit of low reliability, bit B_iAnd also to bits of low reliability. We call that the information bits in the a sequence and the information bits in the B sequence simultaneously input to the constituent encoder constitute one bit group. Therefore, if from (A)_i，B_i) From the perspective of the formed group units, the bit reliabilities of different group units are uneven, and some group units have high reliability and some group units have low reliability.

The conventional method has a problem in that A is not considered_iAnd B_iThe bit mapping is performed jointly, and the reliable characteristic of the high-order modulation bits is not considered when the mapping is performed.

Disclosure of Invention

The invention provides a convolutional Turbo coding method, which comprises the following steps:

information bits A and B are encoded using a component encoderEncoding and outputting check sequence Y₁，W₁；

Interweaving the information bits A and B by using a CTC interweaver to obtain information bits C and D, and then coding the information bits C and D obtained after interweaving by using a CTC component coder to obtain a check sequence Y₂And W₂；

Information bits A and B, check sequence Y₁And W₁Check sequence Y₂And W₂Interleaving is performed separately, wherein for the bit group formed by information bits A and B, the sequence Y₁And W₁Formed bit group and formed by sequence Y₂And W₂At least one of the formed bit groups, wherein the bits are alternately mapped to the bits of the constellation points with high reliability and low reliability;

and perforating the interleaving result to obtain a coded bit sequence.

According to another aspect of the present invention, there is provided a convolutional Turbo encoding device including:

a component encoder for encoding the information bits A and B and outputting a check sequence Y₁，W₁；

A CTC interleaver for interleaving the information bits A and B to obtain new information bits C and D, and then coding the interleaved information bits C and D by using a CTC component coder to obtain a check sequence Y₂And W₂；

An interleaver for interleaving the information bits A and B and the check sequence Y₁And W₁Check sequence Y₂And W₂Interleaving is performed separately, wherein for the bit group formed by information bits A and B, the sequence Y₁And W₁Formed bit group, formed by sequence Y₂And W₂At least one of the formed bit groups, wherein the bits are alternately mapped to the bits of the constellation points with high reliability and low reliability;

and the puncher is used for punching the output sequence of the interleaver to obtain the coded bit sequence.

By using the invention, A_iAnd B_iThe bit mapping is carried out jointly, and meanwhile, the reliable characteristic of high-order modulation bits is considered during mapping, so that the reliability of coding is improved.

Drawings

FIG. 1 illustrates a functional block diagram of a prior art implementation of a convolutional turbo code;

FIG. 2 shows a prior art interleaver implementation;

FIG. 3 shows a high order modulation bit map reliability diagram;

FIG. 4 shows a schematic diagram of the operation of a constituent encoder;

FIG. 5 shows a schematic illustration of a remapping structure according to a first embodiment of the invention;

FIG. 6 shows a schematic illustration of a remapping structure according to a second embodiment of the invention;

fig. 7 shows a schematic illustration of a remapping structure according to a third embodiment of the invention.

Detailed Description

The present invention is primarily an improvement to the symbol grouping module of the interleaver 102 of the convolutional Turbo code shown in figure 1. Here, first, the outputs of the subblock interleave modules in the interleaver are set to the sequences A ', B ', Y '₁、Y’₂、W’₁And W'₂。

According to the invention, the A 'sequence is first mapped and then the corresponding bit in the B' sequence, which is input to the encoder simultaneously with each bit in A ', is found, corresponding to A'_iAre simultaneously input to CTC encoder bit to be recorded as B'_j"B" to be weighed'_jIs A’_iThe group unit of (1) corresponds to a bit. Then mapping the B 'sequence if A'_iMapping to high reliability bit, then its group unit corresponds to bit B'_jShould map to low reliability bits; if A'_iMapping to low reliability bit, then its group unit corresponds to bit B'_jShould map to high reliability bits.

Furthermore, according to the invention, Y 'may be initially paired'₁Sequence was mapped and then found with Y'₁Encoder W 'with each bit output simultaneously'₁Corresponding bit in the sequence, and Y'_1，iChecking bits of CTC encoder output simultaneously are recorded as W'_1，jIs called W'_1，jIs Y'_1，iThe group unit of (1) corresponds to a bit. Then to W'₁Sequence is mapped if Y'_1，iMapping to high reliability bit, then its group unit corresponds to bit W'_1，jShould map to low reliability bits; if Y'_1，iMapping to low reliability bit, then its group unit corresponds to bit W'_1，jShould map to high reliability bits. We call component encoder output simultaneously Y'₁Check bit sum W 'in sequence'₁The information bits in the sequence constitute a group of bits.

Furthermore, according to the present invention, Y 'may be initially treated'₂Sequence was mapped and then found with Y'₂Encoder W 'with each bit output simultaneously'₂Corresponding bit in the sequence, and Y'_2，iChecking bits of CTC encoder output simultaneously are recorded as W'_2，jIs called W'_2，jIs Y'_2，iThe group unit of (1) corresponds to a bit. Then to W'₂Sequence is mapped if Y'_2，iMapping to high reliability bit, then its group unit corresponds to bit W'_2，jShould map to low reliability bits; if Y'_2，iMapping to low reliability bit, then its group unit corresponds to bit W'_2，jShould map to high reliability bits. We call component encoder output simultaneously Y'₂Check bit sum W 'in sequence'₂The information bits in the sequence constitute a group of bits.

The above three schemes can be implemented separately, or any two of the schemes can be executed in combination, or the three schemes can be executed in combination, and all of them belong to the protection scope of the present invention. According to the simulation result, the performance gain is minimum only by adopting the scheme 2 or the scheme 3, if the performance gain is slightly larger by adopting the scheme 2 and the scheme 3, the performance is better than that by adopting the scheme 2 and the scheme 3 if only adopting the scheme 1, and the best performance is generally obtained if all the three schemes are adopted.

A schematic diagram of sub-block interleaving according to the present invention based on the 802.16e implementation standard is shown in fig. 5. In FIG. 5, the output of the sub-block interleaving module at the interleaver is the sequence A ', B ', Y '₁，Y’₂，W’₁，W’₂. Here, A ', B ', Y '₁，Y’₂，W’₁，W’₂Is specifically arranged as A'₀，A’₁，......，A’_N-1；B’₀，B’₁，......，B’_N-1；Y’_1，0，Y’_1，1，......，Y’_1，N-1；Y’_2，0，Y’_2，1，......，Y’_2，N-1；W’_1，0，W’_1，1，......，W’_1，N-1；W’_2，0，W’_{2， 1}，......，W’_2，N-1。

In a first embodiment, the a' sequence is first mapped, as shown in block 501 in fig. 5. Based on 802.16e, and A'_iCorresponding bits simultaneously input into the CTC encoder B 'are B'_i. Then mapping the B 'sequence if A'_iMapping to high reliability bit, then its group unit corresponds to bit B'_iShould map to low reliability bits; if A'_iMapping to low reliability bit, then its group unit corresponds to bit B'_iShould map to high reliability bits.

Of course, they can also be divided intoIs not to consist of sequence Y'₁And W'₁Bit group consisting of and sequence Y'₂And W'₂The constructed bit groups perform the above-described operations.

In a second embodiment, as shown in fig. 6. Firstly to Y'₁Sequences are mapped to Y 'in 802.16 e'_1，iCheck bit of CTC encoder output simultaneously is W'_1，i. Then to W'₁Sequence is mapped if Y'_1，iMapping to high reliability bit, then its group unit corresponds to bit W'_1，iShould map to low reliability bits; if Y'_1，iMapping to low reliability bit, then its group unit corresponds to bit W'_1，iShould map to high reliability bits.

Then, to Y'₂Sequences were mapped, based on 802.16e, with Y'_2，iCheck bit of CTC encoder output simultaneously is W'_2，iThen to W'₂Sequence is mapped if Y'_2，iMapping to high reliability bit, then its group unit corresponds to bit W'_2，iShould map to low reliability bits; if Y'_2，iMapping to low reliability bit, then its group unit corresponds to bit W'_2，iShould map to high reliability bits.

Of course, the operation of alternating mapping may be performed on the bits in the bit group consisting of the a 'sequence and the B "sequence first, and then on the bits of the sequence Y'₁And W'₁Bit group consisting of sequence Y'₂And W'₂The constructed bit groups perform an operation of alternating mapping.

In fig. 6, the high reliability bits are represented by the bits indicated by the arrows. If the high reliability bits are odd bits and the low reliability bits are even bits as defined in FIG. 6, then sequence A 'is output'₀，A’₁，......，A’_N-1；B’₀，B’₁，......，B’_N-2，B’_N-1；Y’_1，0，Y’_2，0，Y’_1，1，Y’_2，1，......，Y’_1，N-1，Y’_2，N-1；W ’_2，0，W’_1，0，W ’_2，1，W’_1，j，......，W’_2，N-1，W’_1，N-1As a result of interleaving.

In a third embodiment, the above two schemes are combined. As shown in FIG. 7, A 'sequences may be first mapped with A'_iCorresponding bits simultaneously input into the CTC encoder B 'are B'_iThen, the B' sequence is mapped. If A'_iMapping to high reliability bit, then its group unit corresponds to bit B'_iShould map to low reliability bits; if A'_iMapping to low reliability bit, then its group unit corresponds to bit B'_iShould map to high reliability bits. Furthermore, as shown in FIG. 7, to Y'₁Sequences are mapped to Y 'in 802.16 e'_1，iCheck bit of CTC encoder output simultaneously is W'_1，iThen to W'₁The sequences are mapped. If Y'_1，iMapping to high reliability bit, then its group unit corresponds to bit W'_1，iShould map to low reliability bits; if Y'_1，iMapping to low reliability bit, then its group unit corresponds to bit W'_1，iShould map to high reliability bits. Then, to Y'₂Sequences are mapped to Y 'in 802.16 e'_2，iCheck bit of CTC encoder output simultaneously is W'_2，iThen to W'₂Sequence is mapped if Y'_2，iMapping to high reliability bit, then its group unit corresponds to bit W'_2，iShould map to low reliability bits; if Y'_2，iMapping to low reliability bit, then its group unit corresponds to bit W'_2，iShould map to high reliability bits.

In fig. 7, the high reliability bits are represented by the bits indicated by arrows. If the high reliability bits are odd bits and the low reliability bits are even bits as defined in FIG. 7, the output sequence is A'₀，B’₀，A’₁，B’₁......，A’_N-2，B’_N-2，A’_N-1，B’_N-1；Y’_1，0，Y’_2，0，Y’_1，1，Y’_2，1，......，Y’_1，N-1，Y’_2，N-1；W’_2，0，W’_1，0，W ’_2，1，W’_1，1，......，W’_2，N-1，W’_1，N-1。

Claims (6)

1. A convolutional Turbo coding method, comprising the steps of:

coding information bits A and B by using a component coder, and outputting a check sequence Y₁，W₁；

Interweaving the information bits A and B by using a CTC interweaver to obtain information bits C and D, and then coding the information bits C and D obtained after interweaving by using a CTC component coder to obtain a check sequence Y₂And W₂；

Information bits A and B, check sequence Y₁And W₁And checkingSequence Y₂And W₂Interleaving is performed separately, wherein for a bit group consisting of two sequences obtained by interleaving information bits A and B, a sequence Y₁And W₁Bit group formed by two sequences obtained after interleaving and sequence Y₂And W₂At least one of bit groups formed by two sequences obtained after interleaving, wherein one of the bits in one sequence of the at least one bit group and the corresponding bit in the other sequence is mapped to one of the bits of the high-reliability constellation point and the bits of the low-reliability constellation point, and the other of the bits in one sequence of the at least one bit group and the corresponding bit in the other sequence is mapped to the other of the bits of the high-reliability constellation point and the bits of the low-reliability constellation point;

and perforating the interleaving result to obtain a coded bit sequence.

2. A convolutional Turbo encoding device comprising:

a component encoder for encoding the information bits A and B and outputting a check sequence Y₁，W₁；

A CTC interleaver for interleaving the information bits A and B to obtain new information bits C and D, and then coding the interleaved information bits C and D by using a CTC component coder to obtain a check sequence Y₂And W₂；

An interleaver for interleaving the information bits A and B and the check sequence Y₁And W₁Check sequence Y₂And W₂Interleaving is performed separately, wherein for a bit group consisting of two sequences obtained by interleaving information bits A and B, a sequence Y₁And W₁Bit group formed by two sequences obtained after interleaving, sequence Y₂And W₂At least one of bit groups formed by two sequences obtained after interleaving is used for mapping the bit in one sequence of the at least one bit group and one bit in the corresponding bit in the other sequence to the bit of the constellation point with high reliability and the bit with low reliabilityOne of the bits of the constellation point and the other of the bits of one sequence of the at least one group of bits and the corresponding bits of the other sequence is mapped onto the other of the bits of the constellation point of high reliability and the bits of the constellation point of low reliability;

and the puncher is used for punching the output sequence of the interleaver to obtain the coded bit sequence.

3. A convolutional Turbo coding method, comprising the steps of:

coding information bits A and B by using a component coder, and outputting a check sequence Y₁，W₁；

Interweaving the information bits A and B by using a CTC interweaver to obtain information bits C and D, and then coding the information bits C and D obtained after interweaving by using a CTC component coder to obtain a check sequence Y₂And W₂；

Information bits A and B, check sequence Y₁And W₁Check sequence Y₂And W₂Are interleaved separately if Y₁The interleaved resulting sequence is mapped to high reliability bits, W₁The sequence obtained after interleaving is mapped to low reliability bits if Y₁The resulting interleaved sequence is mapped to low reliability bits, then W₁The sequence obtained after interleaving should be mapped to high reliability bits; if Y is₂The interleaved sequence is mapped to high reliability bits, then W₂Mapping the sequence obtained after interleaving to low-reliability bits; if Y is₂The resulting interleaved sequence is mapped to low reliability bits, then W₂Mapping the sequence obtained after interleaving to a high-reliability bit;

and perforating the interleaving result to obtain a coded bit sequence.

4. A convolutional Turbo encoding device comprising:

a component encoder for encoding the information bits A and B and outputting a check sequence Y₁，W₁；

CTC crossingThe interleaver interleaves the information bits A and B to obtain new information bits C and D, and then encodes the interleaved information bits C and D by using a CTC component encoder to obtain a check sequence Y₂And W₂；

An interleaver for interleaving the information bits A and B and the check sequence Y₁And W₁Check sequence Y₂And W₂Are interleaved separately if Y₁The interleaved resulting sequence is mapped to high reliability bits, W₁The interleaved resulting sequence is mapped to low reliability bits if Y₁The interleaved resulting sequence is mapped to low reliability bits, then W₁The interleaved sequence should be mapped to high reliability bits; if Y is₂The resulting interleaved sequence is mapped to high reliability bits, then W₂Mapping the interleaved sequence to low reliability bits; if Y is₂The interleaved resulting sequence is mapped to low reliability bits, then W₂Mapping the interleaved sequence to a high reliability bit;

and the puncher is used for punching the output sequence of the interleaver to obtain the coded bit sequence.

5. A convolutional Turbo coding method, comprising the steps of:

coding information bits A and B by using a component coder, and outputting a check sequence Y₁，W₁；

Interweaving the information bits A and B by using a CTC interweaver to obtain information bits C and D, and then coding the information bits C and D obtained after interweaving by using a CTC component coder to obtain a check sequence Y₂And W₂；

Information bits A and B, check sequence Y₁And W₁Check sequence Y₂And W₂Respectively interweaving to output sequence A'₀，A’₁，......，A’_N-1；B’₀，B’₁，......，B’_N-2，B’_N-1；Y’_1，0，Y’_2，0，Y’_1，1，Y’_2，1，......，Y’_1，N-1，Y’_2，N-1；W’_2，0，W’_1，0，W’_2，1，W’_1，1，......，W’_2，N-1，W’_1，N-1Is an interleaving result;

and perforating the interleaving result to obtain a coded bit sequence.

6. A convolutional Turbo encoding device comprising:

a component encoder for encoding the information bits A and B and outputting a check sequence Y₁，W₁；

A CTC interleaver for interleaving the information bits A and B to obtain new information bits C and D, and then coding the interleaved information bits C and D by using a CTC component coder to obtain a check sequence Y₂And W₂；

An interleaver for interleaving the information bits A and B and the check sequence Y₁And W₁Check sequence Y₂And W₂Respectively interweaving to output sequence A'₀，A’₁，......，A’_N-1；B’₀，B’₁，......，B’_N-2，B’_N-1；Y’_1，0，Y’_2，0，Y’_1，1，Y’_2，1，......，Y’_1，N-1，Y’_2，N-1；W’_2，0，W’_1，0，W’_2，1，W’_1，1，......，W’_2，N-1，W’_1，N-1；

And the puncher is used for punching the output sequence of the interleaver to obtain the coded bit sequence.