KR102743028B1 - Bicm reception device using non-uniform 16-symbol signal constellation for low density parity check codeword with 4/15 code rate, and method using the same - Google Patents

Abstract

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. A modulator using a non-uniform 16-symbol signal constellation according to one embodiment of the present invention includes a memory that receives a codeword corresponding to an LDPC code having a code rate of 4/15; and a processor that maps the codeword to 16 symbols of a non-uniform 16-symbol signal constellation in units of 4 bits.

Description

{BICM RECEPTION DEVICE USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW DENSITY PARITY CHECK CODEWORD WITH 4/15 CODE RATE, AND METHOD USING THE SAME}

The present invention relates to symbol mapping using non-uniform signal constellation, and more particularly to a modulator for transmitting error-correcting encoded data in a digital broadcasting channel.

BICM (Bit-Interleaved Coded Modulation) is a bandwidth-efficient transmission technology that combines an error-correction coder, a bit-by-bit interleaver, and a high-order modulator.

BICM can provide excellent performance with a simple structure by using LDPC (Low-Density Parity Check) coder or turbo coder as an error correction coder. In addition, BICM provides a high level of flexibility because the modulation order, error correction code length, and code rate can be selected in various ways. Due to these advantages, BICM is not only being used in broadcasting standards such as DVB-T2 and DVB-NGH, but is also likely to be used in other next-generation broadcasting systems.

Despite these advantages, BICM has a significant gap with the Shannon limit in terms of capacity. To reduce this gap with the Shannon limit, modulation using better signal characteristics is essential.

The purpose of the present invention is to provide a modulator and modulation method using an unequal signal constellation that is more efficient than an equal signal constellation for transmitting error correction encoded data in a broadcasting system channel.

In addition, an object of the present invention is to provide a modulator and a modulation method for non-uniform 16-symbol mapping, which are optimized for an LDPC encoder with a code rate of 4/15 and can be applied to next-generation broadcasting systems such as ATSC 3.0.

According to the present invention, a modulator using an unequal 16-symbol signal constellation to achieve the above-mentioned object includes a memory for receiving a codeword corresponding to an LDPC code having a code rate of 4/15; and a processor for mapping the codeword to one of 16 symbols of the unequal 16-symbol signal constellation in units of 4 bits.

At this time, the 16 symbols may include a first group of four symbols in the first quadrant with non-uniform distances between the symbols, a second group of four symbols symmetrical with respect to the imaginary axis with respect to the four symbols of the first group, a third group of four symbols symmetrical with respect to the origin with respect to the four symbols of the first group, and a fourth group symmetrical with respect to the real axis with respect to the four symbols of the first group.

At this time, the vector corresponding to the four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group may be w, the vector corresponding to the four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) of the second group may be -conj(w) (conj(w) is a function that outputs the complex conjugate of all elements of w), the vector corresponding to the four symbols (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) of the third group may be -w, and the vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group may be conj(w).

At this time, two of the four symbols of the first group may be symmetrical in the magnitude of the real component and the magnitude of the imaginary component.

At this time, the four symbols of the first group are w ₀ , w ₁ , w _{2 ,} and w ₃ , and |real(w ₀ )| = |imaginary(w ₁ )| (real(i) is a function that outputs the real component of i, imaginary(i) is a function that outputs the imaginary component of i, and i is any complex number), and |real(w ₁ )| = |imaginary(w ₀ )|, |real(w ₂ )| = |imaginary(w ₃ )|, and |real(w ₃ )| = |imaginary(w ₂ )|.

At this time, the above 16 symbols can be defined as shown in the table below.

[graph]

In addition, a modulation method using an unequal 16-symbol signal constellation according to the present invention includes the steps of: receiving a codeword corresponding to an LDPC code having a code rate of 4/15; mapping the codeword to one of 16 symbols of the unequal 16-symbol signal constellation in units of 4 bits; and adjusting at least one of the amplitude and phase of a carrier corresponding to the mapping.

In addition, the BICM device according to the present invention includes an error correction encoder that outputs an LDPC codeword having a code rate of 4/15; a bit interleaver that interleaves the LDPC codeword into bit group units having a size corresponding to a parallel factor of the LDPC codeword and outputs an interleaved codeword; and a modulator that maps the interleaved codeword into 16 symbols of an unequal 16-symbol signal constellation in units of 4 bits.

According to the present invention, by intentionally distorting a signal constellation for transmitting error correction encoded data in a next-generation broadcasting system, significantly improved performance can be obtained compared to a uniform signal constellation.

In addition, the present invention provides an unequal 16-symbol signal constellation that is optimized for an LDPC encoder with a code rate of 4/15 and can be applied to next-generation broadcasting systems such as ATSC 3.0.

FIG. 1 is a block diagram showing a broadcast signal transmission/reception system according to one embodiment of the present invention.
FIG. 2 is a flowchart illustrating a broadcast signal transmission/reception method according to one embodiment of the present invention.
FIG. 3 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
Figure 4 is a diagram showing bit groups of an LDPC codeword whose length is 64800.
Figure 5 is a diagram showing bit groups of an LDPC codeword with a length of 16200.
Figure 6 is a diagram showing interleaving of bit groups according to an interleaving sequence.
Figure 7 is a diagram showing the signal characteristics of 16-QAM.
Figure 8 is a diagram showing an unequal 16-symbol signal constellation optimized for an LDPC code with a code rate of 4/15.
Figure 9 is a diagram showing the performance of the uniform signal constellation shown in Figure 7 and the unequal signal constellation shown in Figure 8 for an LDPC code with a code rate of 4/15.
FIG. 10 is a block diagram showing a modulator using a 16-symbol unequal signal constellation according to an embodiment of the present invention.
FIG. 11 is a flowchart illustrating a modulation method using a 16-symbol unequal signal constellation according to an embodiment of the present invention.

The present invention will be described in detail with reference to the attached drawings as follows. Herein, repeated descriptions, well-known functions that may unnecessarily obscure the gist of the present invention, and detailed descriptions of configurations are omitted. The embodiments of the present invention are provided to more completely explain the present invention to those with average knowledge in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for a clearer description.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a block diagram showing a broadcast signal transmission/reception system according to one embodiment of the present invention.

Referring to FIG. 1, it can be seen that a BICM device (10) and a BICM receiving device (30) communicate via a wireless channel (20).

The BICM device (10) encodes k-bit information bits (11) in an error correction encoder (13) to generate an n-bit codeword. At this time, the error correction encoder (13) may be an LDPC encoder or a turbo encoder, etc.

The codeword is interleaved by a bit interleaver (14) to generate an interleaved codeword.

At this time, interleaving can be performed in bit group units. At this time, the error correction encoder (13) can be an LDPC encoder with a length of 16200 and a code rate of 4/15, and a codeword with a length of 16200 can be divided into a total of 45 bit groups, and each of the bit groups can include 360 bits, which is a parallel factor of the LDPC codeword.

At this time, interleaving can be performed in bit group units corresponding to the interleaving sequence described later.

At this time, the bit interleaver (14) effectively disperses clustering errors occurring in the channel to prevent performance degradation of the error correction code. At this time, the bit interleaver (14) can be individually designed according to the length and code rate of the error correction code, and the modulation order.

The interleaved codeword is modulated by a modulator (15) and transmitted through an antenna (17).

At this time, the modulator (15) is a concept that includes a symbol mapping device. At this time, the modulator (15) may be a symbol mapping device that performs 16-symbol mapping that maps codes to 16 constellations.

At this time, the modulator (15) may be a uniform modulator such as a QAM (Quadrature Amplitude Modulation) modulator, or may be a non-uniform modulator.

In particular, the modulator (15) may be a symbol mapping device that performs NUC (Non-Uniform Constellation) symbol mapping having 16 constellations. That is, the modulator (15) may map an interleaved codeword into 16 symbols of a non-uniform 16-symbol signal constellation in 4-bit units.

A signal transmitted through a wireless channel (20) is received through an antenna (31) of a BICM receiving device (30), and the BICM receiving device (30) undergoes a reverse process of the process that occurred in the BICM device (10). That is, the received data is demodulated by a demodulator (33), deinterleaved by a bit deinterleaver (34), and decoded by an error correction decoder (35) to finally restore the information bits.

The above-described transmission/reception process has been described within the minimum scope necessary to explain the features of the present invention, and it is obvious to those skilled in the art that many processes necessary for data transmission may be added in addition to the above-described process.

FIG. 2 is a flowchart illustrating a broadcast signal transmission/reception method according to one embodiment of the present invention.

Referring to FIG. 2, a broadcast signal transmission/reception method according to one embodiment of the present invention first performs error correction encoding on input bits (information bits) (S210).

That is, step (S210) encodes k-bit information bits in an error correction encoder to generate an n-bit codeword.

At this time, step (S210) can be performed like the LDPC encoding method described later.

In addition, the broadcast signal transmission/reception method interleaves n-bit codewords into bit group units to generate interleaved codewords (S220).

At this time, the n-bit codeword can be an LDPC codeword with a length of 16200 and a code rate of 4/15, and the codeword with a length of 16200 can be divided into a total of 45 bit groups, and each of the bit groups can include 360 bits corresponding to a parallel factor of the LDPC codeword.

At this time, interleaving can be performed in bit group units corresponding to the interleaving sequence described later.

Additionally, the broadcast signal transmission/reception method modulates encoded data (S230).

That is, step (S230) modulates the interleaved codeword by a modulator.

At this time, the modulator is a concept that includes a symbol mapping device. At this time, the modulator may be a symbol mapping device that performs 16-symbol mapping that maps codes to 16 constellations.

At this time, the modulator may be a uniform modulator such as a QAM (Quadrature Amplitude Modulation) modulator, or a non-uniform modulator.

In particular, the modulator may be a symbol mapping device that performs NUC (Non-Uniform Constellation) symbol mapping having 16 constellations. That is, the modulator may map an interleaved codeword into 16 symbols of a non-uniform 16-symbol signal constellation in units of 4 bits.

Additionally, the broadcast signal transmission/reception method transmits modulated data (S240).

That is, step (S240) transmits the modulated codeword through a wireless channel via an antenna.

Additionally, the broadcast signal transmission/reception method demodulates the received data (S250).

That is, step (S250) receives a signal transmitted through a wireless channel via an antenna of the receiver and demodulates the received data using a demodulator.

In addition, the broadcast signal transmission/reception method deinterleaves the demodulated data (S260). At this time, the deinterleaving of step (S260) may correspond to the reverse process of step (S220).

In addition, the broadcast signal transmission/reception method performs error correction decoding on the deinterleaved codeword (S270).

That is, step (S270) performs error correction decoding through the error correction decoder of the receiver to ultimately restore the information bits.

At this time, step (S270) may correspond to the reverse process of the LDPC encoding method described later.

LDPC (Low Density Parity Check) codes are known as codes that approach the Shannon limit in AWGN (Additive White Gaussian Noise) channels, and have advantages such as asymptotically better performance than turbo codes and parallelizable decoding.

In general, LDPC codes are defined by randomly generated low-density PCM (Parity Check Matrix). However, randomly generated LDPC codes not only require a lot of memory to store PCM, but also take a lot of time to access the memory. To solve this problem, quasi-cyclic LDPC (QC-LDPC) codes have been proposed, and QC-LDPC codes composed of zero matrix or Circulant Permutation Matrix (CPM) are defined by PCM, which is expressed by the following mathematical expression 1.

[Mathematical Formula 1]

Here, J is a CPM of size L x L and is given by the following mathematical expression 2. In the following, L can be 360.

[Mathematical formula 2]

Also, J ⁱ is the L x L identity matrix I(=J ⁰ ) shifted to the right i(0=i<L) times, and J ^∞ is the L x L zero matrix. Therefore, in QC-LDPC codes, only the exponent i needs to be stored to store J ⁱ , so the memory required to store PCM is greatly reduced.

FIG. 3 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of matrices A and C are g x K and (N-K-g) x (K+g), respectively, and they consist of a zero matrix and a CPM of size L x L. In addition, matrix z is a zero matrix of size g x (N-K-g), matrix D is an identity matrix of size (N-K-g) x (N-K-g), and matrix B is a dual diagonal matrix of size g x g. In this case, matrix B may be a matrix in which all elements other than the diagonal elements and the neighboring elements below the diagonal are 0, or may be defined as in Mathematical Formula 3 below.

[Mathematical Formula 3]

Here, I _LxL is the identity matrix of size L x L.

That is, matrix B may be a general (bit-wise) double diagonal matrix, or may be a block-wise double diagonal matrix having the identity matrix as a block as expressed in the mathematical expression 3 above. The general (bit-wise) double diagonal matrix is disclosed in detail in Korean Patent Publication No. 2007-0058438, etc.

In particular, if the matrix B is a general (bit-wise) double diagonal matrix, it is obvious to those skilled in the art that the PCM structured as shown in Fig. 3 including such matrix B can be converted into a quasi-cyclic one by applying row permutation or column permutation.

Here, N represents the length of the codeword and K represents the length of the information.

In the present invention, a newly designed QC-LDPC code is proposed, which has a code rate of 4/15 and a codeword length of 16200, as shown in Table 1 below. That is, an LDPC code is proposed, which receives information of length 4320 and generates an LDPC codeword of length 16200.

Table 1 shows the sizes of the A, B, C, D, and Z matrices of the QC-LDPC code of the present invention.

The newly designed LDPC code can be represented in the form of a sequence, and the sequence and the matrix (parity bit check matrix) have an equivalent relationship, and the sequence can be expressed as shown in the table below.

[table]

Row 1: 19 585 710 3241 3276 3648 6345 9224 9890 10841

Row 2: 181 494 894 2562 3201 4382 5130 5308 6493 10135

Row 3: 150 569 919 1427 2347 4475 7857 8904 9903

Row 4: 1005 1018 1025 2933 3280 3946 4049 4166 5209

Row 5: 420 554 778 6908 7959 8344 8462 10912 11099

Row 6: 231 506 859 4478 4957 7664 7731 7908 8980

Row 7: 179 537 979 3717 5092 6315 6883 9353 9935

Row 8: 147 205 830 3609 3720 4667 7441 10196 11809

Row 9: 60 1021 1061 1554 4918 5690 6184 7986 11296

Row 10: 145 719 768 2290 2919 7272 8561 9145 10233

Row 11: 388 590 852 1579 1698 1974 9747 10192 10255

Row 12: 231 343 485 1546 3155 4829 7710 10394 11336

Row 13: 4381 5398 5987 9123 10365 11018 11153

Row 14: 2381 5196 6613 6844 7357 8732 11082

Row 15: 1730 4599 5693 6318 7626 9231 10663

LDPC codes written in a sequence form are widely used in the DVB standard.

According to one embodiment of the present invention, an LDPC code expressed in a sequence form is encoded as follows. Assume an information block S=(s ₀ , s ₁ , ..., s _K-1 ) whose information size is K. An LDPC encoder uses the information block S whose size is K to create a codeword whose size is N = K + M ₁ + M _{2 .} generates. Here, M ₁ =g, M ₂ =NKg. Also, M ₁ is the size of the parity corresponding to the dual diagonal matrix B, and M ₂ is the size of the parity corresponding to the identity matrix D. The encoding process is as follows.

-Initialization:

[Mathematical Formula 4]

-first accumulates at the parity bit addresses specified in the first row of the sequence of the above table. For example, the accumulation process in an LDPC code with a length of 16200 and a code rate of 4/15 is as follows.

Addition here( ) occurs in GF(2).

-The next L-1 bits of information, i.e. For the fields, the parity bit addresses calculated in the following mathematical expression 5 are accumulated.

[Mathematical Formula 5]

Here, x is the first bit The parity bit addresses corresponding to Q ₁ = M ₁ /L, Q ₂ = M ₂ /L, L = 360. In addition, Q ₁ and Q ₂ are defined in Table 2 below. For example, an LDPC code with a length of 16200 and a code rate of 4/15 is M ₁ = 1080, Q ₁ = 3, M ₂ = 10800, Q ₂ = 30, L = 360, so the second bit For this, the following operation is performed using the above mathematical expression 5.

Table 2 shows the sizes of M ₁ , M ₂ , Q ₁ , and Q ₂ of the designed QC-LDPC code.

-Next from 360 new]

Information bits are calculated and accumulated by using the second row of the above sequence and the addresses of the parity bit accumulators from the above mathematical expression 5.

- In a similar manner, for all groups consisting of new L information bits, the addresses of the parity bit accumulators are calculated and accumulated from the above equation (5) using the new row of the above sequences.

- at After all information bits up to are used, the operation of the following mathematical expression 6 is performed sequentially starting from i = 1.

[Mathematical Formula 6]

-Next, by performing parity interleaving as in the following mathematical expression 7, parity generation corresponding to the double diagonal matrix B is completed.

[Mathematical formula 7]

K bits of information ( ) is used to generate parities corresponding to the double diagonal matrix B, then M ₁ generated parities ( ) is used to generate a parity corresponding to the identity matrix D.

- at For all groups consisting of L bits up to , the addresses of the parity bit accumulators are calculated using the new row of the above sequences (starting from the row immediately following the last row used when generating the parity corresponding to the double diagonal matrix B) and the above mathematical expression 5, and related operations are performed.

- at After all bits up to are used, parity interleaving as in mathematical expression 8 below is performed, and parity generation corresponding to the identity matrix D is completed.

[Mathematical formula 8]

Figure 4 is a diagram showing bit groups of an LDPC codeword with a length of 64800.

Referring to Figure 4, it can be seen that the LDPC codeword with a length of 64800 is divided into 180 bit groups ( ^0th group to ^179th group).

At this time, 360 can be the parallel factor (PF) of the LDPC codeword. That is, since the PF is 360, the LDPC codeword with a length of 64800 is divided into 180 bit groups as shown in Fig. 4, and each bit group contains 360 bits.

Figure 5 is a diagram showing bit groups of an LDPC codeword with a length of 16200.

Referring to Figure 5, it can be seen that the LDPC codeword with a length of 16200 is divided into 45 bit groups ( ^0th group to ^44th group).

At this time, 360 can be the parallel factor (PF) of the LDPC codeword. That is, since the PF is 360, the LDPC codeword with a length of 16200 is divided into 45 bit groups as shown in Fig. 5, and each bit group contains 360 bits.

Figure 6 is a diagram showing interleaving of bit groups according to an interleaving sequence.

Referring to Fig. 6, it can be seen that interleaving is performed by changing the order of bit groups according to the designed interleaving sequence.

For example, suppose the interleaving sequence for an LDPC codeword of length 16200 is as follows.

Interleaving sequence = {24 34 15 11 2 28 17 25 5 38 19 13 6 39 1 14 33 37 29 12 42 31 30 32 36 40 26 35 44 4 16 8 20 43 21 7 0 18 23 3 10 41 9 27 22}

Then, the order of bit groups of the LDPC codeword as shown in Fig. 4 is changed as shown in Fig. 6 by the interleaving sequence.

That is, the LDPC codeword (610) and the interleaved codeword (620) each include 45 bit groups, and the 24th bit group of the LDPC codeword (610) becomes the 0th bit group of the interleaved LDPC codeword (620) by the interleaving sequence, the 34th bit group of the LDPC codeword (610) becomes the 1st bit group of the interleaved LDPC codeword (620), the 15th bit group of the LDPC codeword (610) becomes the 2nd bit group of the interleaved LDPC codeword (620), the 11th bit group of the LDPC codeword (610) becomes the 3rd bit group of the interleaved LDPC codeword (620), and the 2nd bit group of the LDPC codeword (610) becomes the 4th bit group of the interleaved LDPC codeword (620). You can see that it is possible.

LDPC codeword of length N _ldpc is split into N _group = N _ldpc / 360 bit groups. In this case, N _ldpc can be 16200.

[Mathematical formula 9]

Here, X _j represents the jth bit group, and each X _j consists of 360 bits.

The LDPC codeword divided into bit groups is interleaved as shown in the following mathematical expression 10.

[Mathematical Formula 10]

Here, Y _j represents the jth interleaved bit group, and π( j ) is the permutation order for bit group unit interleaving. The permutation order corresponds to the interleaving sequence of the following mathematical expression 11.

[Mathematical Formula 11]

Interleaving sequence

={34 3 19 35 25 2 17 36 26 38 0 40 27 10 7 43 21 28 15 6 1 37 18 30 32 33 29 22 12 13 5 23 44 14 4 31 20 39 42 11 9 16 41 8 24}

That is, when each of the codeword and the interleaved codeword includes 45 bit groups from the 0th bit group to the 44th bit group, the interleaving sequence of mathematical expression 11 means that the 34th bit group of the codeword becomes the 0th bit group of the interleaved codeword, the 3rd bit group of the codeword becomes the 1st bit group of the interleaved codeword, the 19th bit group of the codeword becomes the 2nd bit group of the interleaved codeword, the 35th bit group of the codeword becomes the 3rd bit group of the interleaved codeword, ..., the 8th bit group of the codeword becomes the 43rd bit group of the interleaved codeword, and the 24th bit group of the codeword becomes the 44th bit group of the interleaved codeword.

In particular, the interleaving sequence represented in mathematical expression 11 is optimized when 16-symbol mapping (specifically, NUC symbol mapping) is used and an LDPC encoder with a length of 16200 and a code rate of 4/15 is used.

Typically, uniform QAM (Quadrature Amplitude Modulation) is used to transmit error-correcting encoded data in broadcasting and communication systems.

Figure 7 is a diagram showing the signal characteristics of 16-QAM.

Referring to Figure 7, it can be seen that 16 symbols of the signal properties of 16-QAM to which 4 bits are mapped are uniformly distributed.

In Fig. 7, gray mapping is applied to the bit-string mapping between each symbol, but other types of bit-string mapping can also be used.

The uniform 16-QAM illustrated in Fig. 7 has a constant distance between constellation points. This uniform QAM has the advantage of being able to be used regardless of the code rate of the error correction code, but it cannot help but show lower performance than the non-uniform signal constellation specialized for a specific code rate. Theoretically, it is known that in an AWGN (Addictive White Gaussian Noise) channel environment, when the amplitude of the channel input signal (transmission signal) and the amplitude of the channel itself simultaneously follow a Gaussian distribution, the capacity, which is the mutual information between the transmission signal and the reception signal, is maximized. Based on this theoretical background, better performance can be obtained than the uniform constellation through intentional distortion of the signal constellation.

The design of the unequal signal constellation can use symmetrical design techniques.

That is, in the case of 16-QAM, the four signal constellation symbols of the first quadrant are designed first, and then the signal constellation symbols for the remaining three quadrants can be designed symmetrically.

For example, if the vector of four signal constellation symbols in the first quadrant is w=( _w0 , _w1 , _w2 , _w3 ), the vector of signal constellation symbols for the remaining quadrants can be determined as follows.

- Quadrant 1: (w ₀ , w ₁ , w ₂ , w ₃ ) = w

- 2nd quadrant: (w ₄ , w ₅ , w ₆ , w ₇ ) = -conj(w)

- 3rd quadrant: (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) = -w

- Quadrant 4: (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) = conj(w)

Here, conj(w) can be a function that outputs the complex conjugate of all elements of w.

Of course, the vectors of signal constellation symbols can be determined in various other ways.

A symbol w _i can have a bit-string mapping value corresponding to the decimal value i. For example, w ₃ = 3 ₍₁₀₎ = 0010 ₍₂₎ .

When designing an unequal signal constellation, using symmetric design techniques has the advantage of greatly reducing complexity.

To further reduce the design complexity, we can assume that the real and imaginary amplitudes of vector w corresponding to the four signal constellation symbols in the first quadrant are symmetric. That is, two of the four symbols in the first quadrant can have symmetrical real component and imaginary component amplitudes.

In this case, instead of designing four complex numbers, we design four PAM (Pulse Amplitude Modulation) points. At this time, we can set the smallest PAM value to 1, find the remaining three PAM values, and then normalize the power. As a result, by utilizing the symmetry mentioned above, we can generate a total of 16 signal constellations by designing three PAM values.

In general, to design L = M ² signal constellations, you only need to design M-1 PAM values.

When M-1 PAM values are obtained, the obtained M-1 PAM values and the smallest PAM value are power normalized, and the result is defined as PAM_norm = [P ₁ P ₂ ... P _M ]. When obtaining w using PAM_norm , it can be expressed as follows by using the assumption that the real and imaginary PAM values are symmetric.

|real(w ₀ )| = |imaginary(w ₁ )|

|real(w ₁ )| = |imaginary(w ₀ )|

|real(w ₂ )| = |imaginary(w ₃ )|

|real(w ₃ )| = |imaginary(w ₂ )|

(real(i) is a function that outputs the real component of i, imaginary(i) is a function that outputs the imaginary component of i, and i is any complex number)

That is, if the real values of the vector w corresponding to the first-quadrant symbols are defined, all imaginary values of w are also defined accordingly. In the case of 16-QAM having a total of 4 symbols in the first quadrant, there are a total of 4! (factorial) = 4 X 3 X 2 X 1 = 24 combination methods, as shown in Table 3 below. Table 3 below shows 24 ways to obtain w, a vector corresponding to the first-quadrant symbols.

method _{Real of w 0 Imaginary of w 0 Real of w 1 Imaginary of w 1 Real of w 2 Imaginary of w 2 Real of w 3 Imaginary of w 3} 1 P ₁ P ₂ P ₂ P ₁ P ₃ P ₄ P ₄ P ₃ 2 P ₁ P ₂ P ₂ P ₁ P ₄ P ₃ P ₃ P ₄ 3 P ₁ P ₃ P ₃ P ₁ P ₂ P ₄ P ₄ P ₂ 4 P ₁ P ₃ P ₃ P ₁ P ₄ P ₂ P ₂ P ₄ 5 P ₁ P ₄ P ₄ P ₁ P ₂ P ₃ P ₃ P ₂ 6 P ₁ P ₄ P ₄ P ₁ P ₃ P ₂ P ₂ P ₃ 7 P ₂ P ₁ P ₁ P ₂ P ₃ P ₄ P ₄ P ₃ 8 P ₂ P ₁ P ₁ P ₂ P ₄ P ₃ P ₃ P ₄ 9 P ₂ P ₃ P ₃ P ₂ P ₁ P ₄ P ₄ P ₁ 10 P ₂ P ₃ P ₃ P ₂ P ₄ P ₁ P ₁ P ₄ 11 P ₂ P ₄ P ₄ P ₂ P ₁ P ₃ P ₃ P ₁ 12 P ₂ P ₄ P ₄ P ₂ P ₃ P ₁ P ₁ P ₃ 13 P ₃ P ₁ P ₁ P ₃ P ₂ P ₄ P ₄ P ₂ 14 P ₃ P ₁ P ₁ P ₃ P ₄ P ₂ P ₂ P ₄ 15 P ₃ P ₂ P ₂ P ₃ P ₁ P ₄ P ₄ P ₁ 16 P ₃ P ₂ P ₂ P ₃ P ₄ P ₁ P ₁ P ₄ 17 P ₃ P ₄ P ₄ P ₃ P ₁ P ₂ P ₂ P ₁ 18 P ₃ P ₄ P ₄ P ₃ P ₂ P ₁ P ₁ P ₂ 19 P ₄ P ₁ P ₁ P ₄ P ₂ P ₃ P ₃ P ₂ 20 P ₄ P ₁ P ₁ P ₄ P ₃ P ₂ P ₂ P ₃ 21 P ₄ P ₂ P ₂ P ₄ P ₁ P ₃ P ₃ P ₁ 22 P ₄ P ₂ P ₂ P ₄ P ₃ P ₁ P ₁ P ₃ 23 P ₄ P ₃ P ₃ P ₄ P ₁ P ₂ P ₂ P ₁ 24 P ₄ P ₃ P ₃ P ₄ P ₂ P ₁ P ₁ P ₂

For example, the optimal PAM_norm value designed for an LDPC code with a code rate of 4/15 can be [0.3412 0.5241 0.5797 1.1282]. At this time, if the obtained PAM_norm is converted into a vector w corresponding to the 1st quadrant symbols using Method 1 of Table 3, w = [0.3412 + 0.5241i 0.5241 + 0.3412i 0.5797 + 1.1282i 1.1282 + 0.5797i] can be obtained. Table 4 below shows 16 symbols of an unequal 16-symbol signal constellation optimized for an LDPC code with a code rate of 4/15. In general, since an error correction code has different operating SNR and error correction capability depending on the code rate, the vector w value optimized for each code rate must be used in order to maximize the performance of BICM. If an unequal signal constellation optimized for a specific code rate is used for a different code rate, it can significantly degrade the performance of BICM, so it is important to use an unequal signal constellation that matches the code rate of the LDPC code.

W Constellation 0 0.3412 + 0.5241i 1 0.5241 + 0.3412i 2 0.5797 + 1.1282i 3 1.1282 + 0.5797i 4 -0.3412 + 0.5241i 5 -0.5241 + 0.3412i 6 -0.5797 + 1.1282i 7 -1.1282 + 0.5797i 8 0.3412 - 0.5241i 9 0.5241 - 0.3412i 10 0.5797 - 1.1282i 11 1.1282 - 0.5797i 12 -0.3412 - 0.5241i 13 -0.5241 - 0.3412i 14 -0.5797 - 1.1282i 15 -1.1282 - 0.5797i

Fig. 8 is a diagram showing a non-uniform 16-symbol signal constellation optimized for an LDPC code with a code rate of 4/15. Referring to Fig. 8, it can be seen that 16 symbols of the 16-symbol non-uniform signal constellation to which 4 bits are mapped are non-uniformly distributed. Fig. 8 shows a non-uniform 16-symbol signal constellation calculated based on the designed w. In this case, the bit strings of each symbol shown in Fig. 8 are expressed based on gray mapping, but other types of bit string mapping can also be applied.

Figure 9 is a diagram showing the performance of the uniform signal constellation shown in Figure 7 and the unequal signal constellation shown in Figure 8 for an LDPC code with a code rate of 4/15.

Referring to FIG. 9, it can be seen that the BER (Bit Error Rate) and FER (Frame Error Rate) of the non-uniform signal constellation and the uniform 16-QAM according to the present invention are illustrated. In FIG. 9, the non-uniform signal constellation shows significantly better performance than the uniform 16-QAM.

FIG. 10 is a block diagram showing a modulator using a 16-symbol unequal signal constellation according to an embodiment of the present invention.

Referring to FIG. 10, a 16-symbol unequal signal constellation according to an embodiment of the present invention includes memories (1010, 1030) and a processor (1020). At this time, the modulator illustrated in FIG. 10 may correspond to the modulator (15) illustrated in FIG. 1.

The memory (1010) receives a codeword corresponding to an LDPC code having a code rate of 4/15.

At this time, the codeword may be an error-correcting LDPC codeword or an interleaved LDPC codeword.

The processor (1020) maps the codeword to 16 symbols of an unequal 16-symbol signal constellation in 4-bit units.

At this time, the processor (1020) may adjust at least one of the amplitude and phase of the carrier corresponding to the symbol mapping.

At this time, the 16 symbols may include a first group of four symbols in the first quadrant with non-uniform distances between the symbols, a second group of four symbols symmetrical with respect to the imaginary axis with respect to the four symbols of the first group, a third group of four symbols symmetrical with respect to the origin with respect to the four symbols of the first group, and a fourth group symmetrical with respect to the real axis with respect to the four symbols of the first group.

At this time, the vector corresponding to the four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group may be w, the vector corresponding to the four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) of the second group may be -conj(w) (conj(w) is a function that outputs the complex conjugate of all elements of w), the vector corresponding to the four symbols (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) of the third group may be -w, and the vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group may be conj(w).

At this time, two of the four symbols of the first group may be symmetrical in the magnitude of the real component and the magnitude of the imaginary component.

At this time, the four symbols of the first group are w ₀ , w ₁ , w _{2 ,} and w ₃ , and |real(w ₀ )| = |imaginary(w ₁ )| (real(i) is a function that outputs the real component of i, imaginary(i) is a function that outputs the imaginary component of i, and i is any complex number), and |real(w ₁ )| = |imaginary(w ₀ )|, |real(w ₂ )| = |imaginary(w ₃ )|, and |real(w ₃ )| = |imaginary(w ₂ )|.

At this time, the above 16 symbols can be defined as in Table 4 above.

The memory (1030) can store additional information necessary for the operation of the processor (1020). For example, the memory (1030) can store carrier frequency, amplitude, etc.

The memory (1010) and the memory (1030) may correspond to various hardware for storing a set of bits, or may correspond to a data structure such as an array, a list, a stack, or a queue.

At this time, the memory (1010) and the memory (1030) may not be physically separate devices, but may correspond to different addresses of a single device. That is, the memory (1010) and the memory (1030) may not be physically separated, but may be separated only logically.

FIG. 11 is a flowchart illustrating a modulation method using a 16-symbol unequal signal constellation according to an embodiment of the present invention.

Referring to FIG. 11, a modulation method using a 16-symbol unequal signal constellation according to an embodiment of the present invention first receives a codeword corresponding to an LDPC code having a code rate of 4/15 (S1110).

At this time, the codeword may be an error-correcting LDPC codeword, or may be an interleaved LDPC codeword. That is, step (S1110) may receive the codeword directly from the LDPC encoder, or may receive the codeword through a bit interleaver in the middle.

In addition, a modulation method using a 16-symbol non-uniform signal constellation according to one embodiment of the present invention maps the codeword to 16 symbols of a non-uniform 16-symbol signal constellation in 4-bit units (S1120).

At this time, the 16 symbols may include a first group of four symbols in the first quadrant with non-uniform distances between the symbols, a second group of four symbols symmetrical with respect to the imaginary axis with respect to the four symbols of the first group, a third group of four symbols symmetrical with respect to the origin with respect to the four symbols of the first group, and a fourth group symmetrical with respect to the real axis with respect to the four symbols of the first group.

At this time, the vector corresponding to the four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group may be w, the vector corresponding to the four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) of the second group may be -conj(w) (conj(w) is a function that outputs the complex conjugate of all elements of w), the vector corresponding to the four symbols (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) of the third group may be -w, and the vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group may be conj(w).

At this time, two of the four symbols of the first group may be symmetrical in the magnitude of the real component and the magnitude of the imaginary component.

At this time, the four symbols of the first group are w ₀ , w ₁ , w _{2 ,} and w ₃ , and |real(w ₀ )| = |imaginary(w ₁ )| (real(i) is a function that outputs the real component of i, imaginary(i) is a function that outputs the imaginary component of i, and i is any complex number), and |real(w ₁ )| = |imaginary(w ₀ )|, |real(w ₂ )| = |imaginary(w ₃ )|, and |real(w ₃ )| = |imaginary(w ₂ )|.

At this time, the above 16 symbols can be defined as in Table 4 above.

In addition, a modulation method using a 16-symbol unequal signal constellation according to one embodiment of the present invention adjusts at least one of the amplitude and phase of a carrier corresponding to the mapping (S1130).

The error correction encoder (13) illustrated in Fig. 1 may also be implemented with a structure similar to that in Fig. 10.

That is, the error correction encoder may include memories and a processor. At this time, the first memory may be a memory for storing an LDPC codeword having a length of 16200 and a code rate of 4/15, and the second memory may be a memory initialized to 0.

The memories may correspond to λ _i (i=0, 1, ..., N-1) and P _j (j=0, 1, ..., M ₁ +M ₂ -1), respectively.

The processor can perform accumulation on the memory using a sequence corresponding to a parity check matrix to generate the LDPC codeword corresponding to the information bits.

At this time, accumulation can be performed on parity bit addresses that are updated using the sequence of the above table.

At this time, the LDPC codeword may include a systematic part (λ ₀ , λ ₁ , ..., λ _{K-1 ) corresponding to the information bits and having a length of 4320 (= K), a first parity part (λ K , λ K+1 , ..., λ K + M1-1} ) corresponding to a double diagonal matrix included in the parity check matrix and having a length of 1080 (= M ₁ = g), and a second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _{K +M1+M2-1} ) corresponding to an identity matrix included in the parity check matrix and having a length of 10800 (= M ₂ ).

At this time, the sequence can have as many rows as the number obtained by adding the value obtained by dividing 4320, which is the length of the systematic part, by 360, which is the CPM size (L) corresponding to the parity check matrix, to the value obtained by dividing 1080, which is the length of the first parity part (M ₁ ), by 360 (4320/360+1080/360=15).

As mentioned above, the sequence can be represented by the above table.

At this time, the second memory can have a size corresponding to the sum (M ₁ +M ₂ ) of the length of the first parity part (M ₁ ) and the length of the second parity part (M ₂ ).

At this time, the parity bit addresses can be updated based on the result of comparing each of the previous parity bit addresses (x) indicated in each row of the above sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses can be updated by the above mathematical expression 5. At this time, x is a previous parity bit address, m is an information bit index, which is an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ can be M ₁ /L, M ₁ can be the size of the first parity part, Q ₂ can be M ₂ /L, M ₂ can be the size of the second parity part.

At this time, the above accumulation can be performed by changing the rows of the sequence in units of CPM size L=360 of the above parity check matrix as described above.

At this time, the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) can be generated by performing parity interleaving using the first memory and the second memory as explained through the mathematical expression 7 above.

At this time, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _{K +M1+M2-1} ) can be generated by performing parity interleaving using the first memory and the second memory after the generation of the first parity part (λ _K , λ _{K+ 1} , ..., λ K _+M1-1 ) is completed as described through the mathematical expression 8 above, and after the accumulation performed using the first parity part (λ K , λ K+1 , ..., λ _K+M1-1 ) and the sequence is completed.

The bit interleaver (14) illustrated in Fig. 1 can also be implemented with a structure similar to Fig. 10.

That is, the first memory can store an LDPC codeword having a length of 16200 and a code rate of 4/15. The processor can interleave the LDPC codeword in bit group units corresponding to a parallel factor of the LDPC codeword to generate an interleaved codeword. At this time, the parallel factor can be 360. At this time, the bit group can include 360 bits. At this time, the LDPC codeword can be divided into 45 bit groups as in the mathematical expression 9.

At this time, interleaving can be performed using the mathematical expression 10 using the permutation order.

At this time, the permutation order may correspond to the interleaving sequence expressed by the above mathematical expression 11.

The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

At this time, the modulator may be a symbol mapping device that performs NUC (Non-Uniform Constellation) symbol mapping as described through FIG. 10.

As described above, the modulator, modulation method, and BICM device using the unequal 16-symbol signal constellation according to the present invention are not limited to the configuration and method of the embodiments described above, and the embodiments may be configured by selectively combining all or part of the embodiments so that various modifications can be made.

1010, 1030: Memory
1020: Processor

Claims (7)

delete A demodulator that performs demodulation corresponding to the nonuniform 16-symbol mapping;
A bit deinterleaver that performs group-based deinterleaving after the above demodulation to generate deinterleaved values corresponding to an LDPC codeword with a code rate of 4/15; and
An LDPC decoder is included to restore information bits by performing LDPC decoding corresponding to the above deinterleaved values,
A BICM (Bit Interleaved and Coded Modulation) receiving device characterized in that the above unequal 16-symbol mapping corresponds to 16 symbols defined as shown in the table below.
[graph]
In claim 2,
A BICM receiving device characterized in that the 16 symbols have non-uniform distances between symbols and include a first group of four symbols in the first quadrant, a second group of four symbols symmetrical with respect to the imaginary axis with respect to the four symbols of the first group, a third group of four symbols symmetrical with respect to the origin with respect to the four symbols of the first group, and a fourth group symmetrical with respect to the real axis with respect to the four symbols of the first group. In claim 3,
A BICM receiving device, characterized in that a vector corresponding to the four symbols (w ₀ , w ₁ , w ₂ , w ₃ ) of the first group is w, a vector corresponding to the four symbols (w ₄ , w ₅ , w ₆ , w ₇ ) of the second group is -conj(w) (conj(w) is a function that outputs the complex conjugate of all elements of w), a vector corresponding to the four symbols (w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ) of the third group is -w, and a vector corresponding to the four symbols (w ₈ , w ₉ , w ₁₀ , w ₁₁ ) of the fourth group is conj(w). In claim 4,
A BICM receiving device, characterized in that two of the four symbols of the first group are symmetrical in terms of the amplitude of their real components and the amplitude of their imaginary components. In claim 5,
A BICM receiving device, characterized in that the four symbols of the first group are w ₀ , w ₁ , w _{2 ,} and w ₃ , and |real(w ₀ )| = |imaginary(w ₁ )| (real(i) is a function that outputs the real component of i, imaginary(i) is a function that outputs the imaginary component of i, and i is any complex number), and |real(w ₁ )| = |imaginary(w ₀ )|, |real(w ₂ )| = |imaginary(w ₃ )|, and |real(w ₃ )| = |imaginary(w ₂ )|. A step of performing demodulation corresponding to the non-uniform 16-symbol mapping;
A step of performing group-based deinterleaving after the above demodulation to generate deinterleaved values corresponding to an LDPC codeword having a code rate of 4/15; and
A step of restoring information bits by performing LDPC decoding corresponding to the above deinterleaved values,
A BICM (Bit Interleaved and Coded Modulation) receiving method characterized in that the above unequal 16-symbol mapping corresponds to 16 symbols defined as shown in the table below.
[graph]