HK1033731B - Apparatus for synchronizing a compressed video signal receiving system - Google Patents

Description

Apparatus for synchronizing compressed video signal receiving system

The present patent application is a divisional application of a patent application having an application date of 12/5 in 1994, application No. 94105749.6 entitled "method and apparatus for providing a compressed video signal".

Technical Field

The invention relates to a method and a device for providing a clock signal at a signal decompression device, which clock signal is frequency-locked to a clock signal of a device for encoding.

Background

The compressed video signal generation and transmission system may operate at several synchronous levels or, more appropriately, at several asynchronous states. For example, the actual compression means will be synchronized, at least in part, to the vertical frame rate of the source video signal, and may also be synchronized to the color sub-carriers. Once the video signal is compressed and formed into a particular signal protocol (e.g., MPEG1), it may be further processed into transport packets for transmission. The transport packets may be time division multiplexed with packets from other video or data sources. The packetization and multiplexing may be performed synchronously with the compression operation or asynchronously. These transport packets (whether multiplexed or not) may then be sent to a modem for data transmission. The modem may or may not operate synchronously with the system described above.

At the receiver of the compressed signal of the full multiplex transmission, it is generally necessary for the individual subsystems to operate synchronously with the inverse function of the counterpart of their systematic encoding ends. Synchronous operation in this case may generally refer to operation of each subsystem at very close proximity to the same frequency of its counterpart subsystem. The decompressor should provide the video signal at the frame rate of the video signal source used to provide it at the compressor and be synchronized with the associated audio signal. Synchronization of the video/audio decompression portion of the system may be achieved by inserting presentation time samples in the video/audio signal being compressed at the encoder, such samples indicating the correlation multiple of the generation/reproduction of the respective signal segments. Such presentation time references (RTR's) can be used to compare the timing of the associated audio and video signals for synchronization purposes and for proper programming and continuity.

The receiver modem must of course operate at exactly the same frequency as the transmit modulation decoder. The receiver modem typically has a phase locked loop responsive to the transmit carrier frequency to generate a synchronized clock signal.

The synchronization of multiplexing and or transmitting data packetizing means tends to be more complex for two reasons. First, the multiplexed data may arrive discretely; second, to minimize manufacturing costs, rate buffering is typically employed between the modem and the decompressor, and measures must be taken to ensure that its rate buffering neither overflows nor underflows, with the constraint of keeping the buffer as small as possible, at virtually the minimum manufacturing cost.

Disclosure of Invention

The present invention relates to a system and apparatus for establishing synchronization for an intermediate layer of a transmission or multiplexing signal such as a multi-layer compressed video signal by inserting different time codes or count values in the compressed video signal. In one embodiment of the encoding end of the system, a modulo-K counter is clocked in response to a system clock and embeds selected ones of the count values provided by the counter in the transport layer signal according to a predetermined protocol. Another measure is to include a value representing the pre-compressed count value when the pre-compressed video signal is introduced into the signal. In another embodiment, in a signaling storage unit in which compressed video signals may be queued, provision is made to measure the time over which the signal is extended by counting clock pulses at the system clock frequency, and to access and refresh the difference count value in the transmitted packet with the delayed measurement value. In an embodiment at the receiving end of the counter system, a counter similar to the one at the encoding end of the system provides a count value in response to a controlled receiver clock signal and samples the count value at a time related to the arrival of the count value embedded in the transport layer. The transmit count and the difference count are accessed from the received transport layer and used in conjunction with the receiver count to generate a signal to control the receiver clock signal.

An apparatus according to the present invention for synchronizing at least a portion of a compressed video signal receiving system that processes compressed signals occurring in transport packets of a compressed video signal, wherein each identifiable one of said transport packets includes a program clock reference having a count value periodically derived from a counter for modulo-K counting pulses of an encoding system clock, where K is a positive integer, and said transport packets include a difference count value associated with the program clock reference of data of the compressed signal multiplexed with said compressed video signal and a delay caused by the transport packet, said apparatus comprising: a source of the transmission data packet, the transmission data packet having the count value and a difference count value; a voltage controlled oscillator providing a receiver system clock in response to a control signal E; a receiver counter for modulo-K counting of pulses of the receiver system clock; an auxiliary data packet detector and latch for indicating auxiliary transport data packets containing a program clock reference and for latching the current count value of said receiver counter, respectively; a reverse transport processor for recovering a count value and a difference count value from the transport data packets and combining them to form a corrected program clock reference, a clock controller for generating the control signal E for controlling the voltage controlled oscillator in response to a continuously stored count value output by the receiver counter and corresponding to the count value and difference count value from the transport data packets, and a low pass filter for generating a low pass filtered control signal for the voltage controlled oscillator.

In the device according to the invention the means for combining the count value with the difference count value is an adder.

In the apparatus according to the invention, said identifiable data packets comprise header data indicating that each of said transmission data packets comprises said count value, and the means responsive to the occurrence of a transmission data packet comprising said count value comprises a matched filter for detecting said header data.

A method according to the present invention for synchronizing at least a portion of a compressed video signal receiving system, the method processing compressed signals occurring in transport packets of a compressed video signal, each transport packet having provisions for including side information, the side information may include a clock reference and another clock reference, the another clock reference being associated with a clock reference of another compressed video signal, each transport packet further including first and second flags for indicating whether the clock reference and the another clock reference are present, the method comprising the steps of:

providing transport packets of a compressed video signal;

providing a receiving system clock whose timing is responsive to a control signal E;

counting pulses of the receiving system clock;

detecting whether said first and second flag bits are present and, if said flag bits are detected, determining whether said clock reference and said further clock reference are present; and

generating said control signal E in response to said presented clock reference and said further clock reference.

A method according to the present invention for synchronizing at least a part of a compressed video signal reception system, the method processing compressed signals occurring in transport packets of a compressed video signal, a plurality of said transport packets having provisions for including side information, which may include a clock reference and another clock reference, and said transport packets including first and second flag bits indicating whether said clock reference and said another clock reference are present or absent, said method comprising the steps of:

providing transmission data packets of a compressed video signal;

providing a receiver system clock whose timing is variable in response to a control signal E;

generating a receiver clock reference by counting pulses of the receiver system clock;

detecting the presence of the first and second flag bits and whether the flag bit is detected;

determining the presence or absence of the clock reference and the another clock reference; and

the control signal E is generated in dependence on the clock reference and the receiver clock reference being present.

Drawings

Fig. 1 is a block diagram of a compressed video encoding/decoding system employing a clock recovery apparatus of the present invention.

Fig. 2 is a block diagram of a signal multiplexing apparatus useful for representing the formation of multiplexed data from different signal sources.

FIGS. 3 and 5 are two other clock recovery arrangements for transmitted compressed video signal data

A block diagram of an embodiment.

Fig. 4 is a block diagram of a signal multiplexing apparatus including a system for enhancing a timing reference contained within a multiplexed signal.

Fig. 6 and 7 are diagrammatic representations of a transmission data block and an auxiliary signal transmission data block.

Fig. 8 is a flowchart of the operation of the transport processor in fig. 2.

Detailed Description

Fig. 1 shows an exemplary system to which the present invention is applicable, which belongs to a compressed digital video signal transmission apparatus. In the present system, a video signal from a video source 10 is provided to a compressor 11 which comprises a motion compensated predictive coder using a discrete cosine transform. The compressed video signal is supplied from the compressor 11 to the formatter 12. The formatter 12 arranges the compressed video signal and other auxiliary data according to a certain signal protocol, for example a standard MPEG as proposed by the international organization for standardization. The normalized signal is sent to the transmit processor 13 which divides the signal into data packets and adds some other data to provide noise immunity for transmission purposes. Transmission data packets, which typically occur at non-uniform rates, are applied to a rate buffer 14 which conducts at a relatively constant rate to provide output data for efficient use of a relatively narrow bandwidth transmission channel. The buffered data is applied to a modem 15 which performs signal transmission.

The system clock 22 provides clocking signals to operate most of the devices including at least the transport processor. The clock will operate at a fixed frequency, for example 27 MHz. However, as shown therein, it is used to generate timing information. The clock of the system is fed to the clock input of a counter 23 which can be set, for example, modulo 2³⁰Is counted. The count value output by the counter is fed to two latches 24 and 25. The latch 24 is set by the video signal source to latch the count values as they occur at various frame intervals. These count values are used toRepresentative of the presentation time samples (PTR's) and included in the compressed video signal data stream by formatter 12 and used by the receiver to provide lip-synchronization (lip-synchronization) of the associated audio and video information. The latch 25 is set by the transmission processor 13 (or the system controller 21) to latch the count value according to a predetermined procedure. These count values are used as a representation of the program clock references (PCR's) and are embedded as auxiliary data in each auxiliary transport packet.

System controller 21 is a variable state machine programmed to coordinate the various processing units. It should be noted that the system controller 21, compressor 11 and transport processor 13 may or may not be synchronized via a common clocking means, as long as proper interactive communication is provided between the processing units.

The units 16-26 in fig. 1 comprise the receiving end of the transmission system, wherein the modem 16 performs the inverse function of the modem 15. Data from the modem 16 is sent to a reverse transport processor 18 which formats the compressed video signal to a rate buffer 17 according to the system specifications, and then the rate buffer 17 provides the compressed video signal to a decompressor 19 which generates an uncompressed video signal in response to the compressed video signal for display on a device 20 or storage in a suitable device.

The inverse transport processor 18 also provides the PCR's from the auxiliary transport data and control signals to the system clock generator 27. A clock generator responsive to these signals generates a system clock signal that is at least synchronized with the transport processor operation. The system clock signal is fed to the receiver system controller 26 to control the timing of the appropriate processing unit.

Referring to fig. 2, there is shown an apparatus that may be included, for example, in a transmission modem 15. The modem may receive data from a plurality of signal sources, the data being all data to be transmitted on a common transmission channel. This can be achieved by time division multiplexing of the various signals from the various signal sources. Furthermore, multiplexing may be done in layers. For example, the video programs Pi may be generated in different studios and coupled to the first multiplexer 55. These programs are time-division multiplexed and provided as a source signal S1 in accordance with well-known techniques.

The signal S1 is fed to the second multiplexer 56, as well as source signals Si from other sources, where the signals Si are time division multiplexed in accordance with well known techniques and predetermined protocols. Finally, there may be other forms of multiplexing within each program itself. The multiplexing thus performed may take the form of commercial programs inserted into the program content or stored programs inserted between the base segments of the live programming. In these latter two cases, it is assumed that the commercial or stored program has been pre-encoded with PTR's and PTC's, respectively. In this case, the PTR's and PCR's of the stored program would then be independent of the real-time PTR's and PCR's of the live program. As for PTR's, they cause particularly no problems since the video signal will include parameters for instructions to the decompressor to restart the new signal. Conversely, due to the lack of correlation between the stored and real-time PCR's, the PCR's may be completely interrupted, thereby desynchronizing the rate buffer reverse transport processor unit of the receiver system.

It is assumed in fig. 2 that the transport processor 53 comprises multiplexing means operationally similar to the respective first and second multiplexers 55 and 56.

There are additional problems in multiplexing systems. In order for each multiplexing device not to lose data, it is necessary to provide a programmed buffering of the signals in the multiplexer if the data arrives simultaneously from multiple signal sources. These buffers will be delayed by T ± δ T, where δ T represents an unstable component. Assume that the program passes through the multiplexer 100 times (an exaggerated number for practical problems) and that each multiplexing adds a delay of 1 second ± 1 microsecond. The final delay result is a delay of 100 seconds ± 100 microseconds. This 100 second in time is not a problem for the decompressor, since the compressed video signal and thus the PTR's already experience the same delay. This 100 microsecond unstable component must be dealt with otherwise the decoder's buffer may overflow or underflow.

Fig. 3 shows a first embodiment of a receiver clock generator. In this embodiment, the transmit processor may be placed before the rate buffer 17 in the signal path to eliminate variable delays that may be incurred in the receiver rate buffer. Data from the receiver modem is sent to the reverse transport processor 32 and an auxiliary packet detector 31. The reverse transport processor 32 separates transport header data from the payload of each transport packet. In response to the transmission header data, the reverse transport processor 32 passes the video signal payload (also shown as traffic data 1) to, for example, a decompression device (not shown) and the auxiliary data (shown as traffic data 2) to an appropriate auxiliary data processing unit (not shown). PTR's placed in the helper data are routed and stored in memory 34.

The auxiliary packet detector 31, which may be a matched filter, identifies codewords indicating auxiliary transmission packets containing PCRs, generates a control pulse upon the occurrence of a transmission packet containing such data. This control pulse is used to store the count value currently being counted by the local counter 36 in the latch 35. The local counter 36 is used to count pulses generated by, for example, a voltage controlled oscillator 37. This counter 36 is designed to have the same modulo counting number as its corresponding counter in the encoder (counter 23).

The compression oscillator 37 is controlled by a low pass filtered error signal provided by a clock controller 39. The error signal is generated as follows. The PCR arriving at time n is designated PCRn and the count value currently latched in latch 35 is designated Ln. The clock controller reads successive values of PCR's and T's and forms an error signal E proportional to the difference:

e → | PCRn-1| - | Ln-1| the error signal E is used to adjust the voltage controlled oscillator 37 to a frequency tending to equalize the difference. The error signal generated by the clock controller 39 may be in the form of a pulse width modulated signal which may be provided as an analog error signal by the analog component implemented in the low pass filter 38.

The constraint of the system is that the counters at both ends of the system count the same frequency or even multiple frequencies. This requires that the defined frequency of the voltage controlled oscillator be a frequency that is fairly close to the frequency of the encoder system clock.

The foregoing scheme provides fairly fast synchronization but introduces long term errors. This long term error LTE is proportional to the following difference:

LET→|Ln-Lo|-|PCRn-PCRo|

where PCRo and Lo may be, for example, the first occurrence of a PCR and the corresponding latched value of the receiver counter. By definition, the error signals E and LTE will change in discrete steps. Thus, once the system is "synchronized," the error signal will dither by one unit around the zero point. The best synchronization method is to use the error signal E to initially control the voltage controlled oscillator until a unit of high frequency jitter occurs in the error signal E and then switch to using the long term error signal LTE to control the voltage controlled oscillator.

In order to adjust the delay T + -deltat introduced during the multiplexing, the transport processor at the encoder generates an auxiliary field in the auxiliary transport packet, which contains information about the variable delay. Procedures are developed to modify this variable delay information at different multiplex locations. Referring to fig. 6 and 7, fig. 6 shows a type of transport packet similar to that used in a high definition television system developed by the advanced television research association. The transmission data contains a prefix which has, among other things, a global identifier to indicate which service the payload contained in the data packet relates to. The field CC is one continuous detection that is included for error detection purposes. The HD field is a service description header that illustratively defines the payload. For example, if a particular service is indicated to provide a television program, each payload of the transport data packets for that service type may contain audio data, video data or associated ancillary data. The HD field thus indicates the type of particular payload for a particular packet.

Fig. 7 shows a transmission data packet containing auxiliary data. The amount of data contained in each data set and the current system requirements, the payload of an ancillary transmission packet may include one or more ancillary data sets. In the transport packet shown in fig. 7, there are two auxiliary data groups containing data about the program clock references AUX1 and AUX 2. The auxiliary data set AUX1 includes data about variable delays, while the data set AUX2 includes the PCR itself. Each data set comprises an ancillary data set prefix and a data block of ancillary data. The prefix includes field MF, CFF, AFID, and AFS. The field MF is a 1-bit field that indicates whether the data in the packet is correctable (1 being correctable and 0 being not). The CFF is a 1-bit field that indicates whether ancillary data is defined for the data set. The AFID is a 6-bit field indicating the type of auxiliary data contained in the data set, such as time code, scrambling key, copyright, etc. The AFS is an 8-bit field defining the number of bytes of auxiliary data contained in the data set.

The AUX1 data group is shown as being correctable and the AUX2 data group is shown as being uncorrectable. The AUX2 data is shown as PCR data, i.e. a program clock reference. The AUX1 data is indicated as DPCR data, which is an abbreviation used for differential program clock reference herein. The PCR data is obtained under the control of a programmer controlling the transport processor in the encoder. The acquisition of DPCR data will be explained with reference to the description of figure 4.

The device of fig. 4 is a typical device that is part of a multiplexer circuit shown in fig. 2. Associated with each input bus is a buffer 67, which may be of the FIFO type. When program data arrives and its multiplexer is currently accessing a different input bus, the data is stored therein. Subsequently, the program data is read out from the buffer 67 in accordance with the program of the multiplexer.

Each transmission packet of program data includes an auxiliary data set containing PCR and DPCR data. It should be noted that the value of the PCR data is determined with respect to the timing of the transmitted data packet containing the auxiliary timing information. When the PCR data is output by the multiplexer, it may be erroneous due to any delay incurred by contention for the signals in the multiplexing process. The delay time T ± δ T taken through the buffer is used to modify the DPCR data to subsequently correct for such errors. An auxiliary data packet detector 61 arranged to detect the presence of transport data packets containing DPCR data is connected to the program data input bus. This detector function resets and starts a counter 62 to count the counting pulses of the local clock 60. The local clock 60 may be a crystal oscillator having a clock frequency very close to the encoder system clock frequency, or may be a frequency that is locked to the encoder clock frequency whenever the apparatus of fig. 3 or 5 is operating. Another auxiliary data packet detector 63 is coupled to the output bus of buffer 67 for storing the current count value output by counter 62 in latch 68 when an auxiliary data packet containing DPCR data emerges from the buffer. The output of the counter at this point will appear as a count of a few units of the clock frequency period, i.e. the transit time of the buffer through a particular data packet. It should be noted that the auxiliary packet detector must be used to detect and respond to each occurrence of a packet if it is possible that multiple auxiliary packets may occur adjacent to one another such that more than one packet may pass to the buffer 67 simultaneously.

The auxiliary data packet detector 61 also provides a control signal that is used to set the latch 64 to store the DPCR value contained in the auxiliary data packet. This value is fed to an input port of an adder 65 and the local count value stored in latch 68 is added to a second input of the adder 65. Adder 65 adds the DPCR data from the current auxiliary data packet to the local count value to provide a refreshed DPCR value DPCR'. The program data from buffer 67 and the output of adder 65 are coupled to input ports of a 2-to-1 multiplexer 66. The multiplexer 66 is set by the auxiliary packet detector 63 so as to normally transmit the program data. However, when DPCR data contained in the program data emerges from the buffer, the multiplexer 66 is set to transfer the refreshed DPCR' data from the adder, and then switches back to transfer the data from the buffer 67.

When the multiplexer 66 is set to transmit data from the adder, the output signal from the adder corresponds to the sum of the DPCR data included in the auxiliary data packet and the count value in the counter 62 when the DPCR data emerges from the buffer. Therefore, the data substitution for the DPCR data by the multiplexer 66 precedes the DPCR data correction for its transmission time in the buffer 67. It should be noted that it is provided that the auxiliary data packet detector is programmed to change the program data only in dependence of the appropriate modification flag MF with the auxiliary data set.

Returning again to fig. 2, the transport processor 53 will create DPCR auxiliary data sets and typically insert a zero value as DPCR data corresponding to the new program. However, it is contemplated that stored data from the data storage medium 51 may be inserted into the live data base and that the stored data may be previously encoded using PCR and DPCR codes. When the transport processor 53 inserts the stored data between base sections of live data, it accesses the PCR code of the stored data and subtracts the PCR value from the current count value presented by the counter 23 and/or latch 25. The transport processor then adds this difference to the DPCR value in the secondary packet storing the data. The new DPCR value inserted in the stored data between live data now contains a reference to the current time. This process is illustrated in the flow chart of fig. 8, which has been described in itself.

The use of DPCR data in the receiver is illustrated in fig. 5. In fig. 5, elements of the reverse transport processor 32 that have the same reference number as elements in fig. 3 have been modified to include similar elements and perform similar functions. The improvement involves the inclusion of an adder 45 for summing the corresponding PCR and DPCR values achieved in the associated auxiliary data set. The sum value provided by the adder corresponding to the original PCR value is increased by any delay introduced, such as during multiplexing. These sum values are placed in memory 46 from which clock controller 39 can obtain the sum values as values for the corrected PCR for synchronization of the system clock.

Claims (3)

1. An apparatus for synchronizing at least a portion of a compressed video signal receiving system that processes compressed signals occurring in transport packets of a compressed video signal, wherein each identifiable one of said transport packets includes a program clock reference having a count value periodically derived from a counter for modulo-K counting pulses of an encoding system clock, where K is a positive integer, and said transport packets include a difference count value associated with the program clock reference of data of the compressed signals multiplexed with said compressed video signal and a delay caused by the transport packets, said apparatus comprising:

a source of the transmission data packet, the transmission data packet having the count value and a difference count value;

a voltage controlled oscillator (37) providing a receiver system clock in response to a control signal E;

a receiver counter (36) for modulo-K counting of pulses of the receiver system clock;

-an auxiliary data packet detector (31) and a latch (35) for indicating auxiliary transport data packets containing a program clock reference and for latching a current count value of said receiver counter, respectively;

a reverse transport processor (32) for recovering a count value and a difference count value from the transport data packets and combining them to form a corrected program clock reference, a clock controller (39) for generating the control signal E for controlling the voltage controlled oscillator in response to successively stored count values output by the receiver counter and corresponding to the count value and difference count value from the transport data packets, and a low pass filter (38) for generating a low pass filtered control signal for the voltage controlled oscillator.

2. The apparatus of claim 1 wherein the means for combining the count value with the difference count value is an adder.

3. The apparatus of claim 1 wherein said identifiable packets include header data indicating that each of said transmitted packets includes said count value, and wherein said means responsive to the occurrence of a transmitted packet including said count value includes a matched filter for detecting said header data.