HK1031951A - Dram cell having reduced transfer device leakage and process of manufacture - Google Patents

Description

DRAM cell with reduced transfer device leakage and process for making same

The present invention relates generally to semiconductor devices, and more particularly to field effect transistors with reduced off-current (Ioff) and low source-to-drain leakage.

Dynamic Random Access Memory (DRAM) cells typically have a transfer device and a capacitor. The DRAM cell is so named because it can only temporarily hold information on the order of milliseconds, even if power is continuously applied. Therefore, the cells must be read and refreshed at periodic intervals. Although the storage time initially appears short, in practice it is long enough to allow many storage operations between refresh cycles. The advantages of cost per bit, device density, and flexibility of use (i.e., both read and write operations are possible) make DRAM cells the most widely used semiconductor memory at the present time.

In general, the integrated circuit technology of DRAM cells is based on the ability to form a large number of transfer devices in a single silicon substrate. One type of transfer device is a Field Effect Transistor (FET). There are now mainly two types of FETs: metal oxide semiconductor field effect transistors or MOSFETs (also known as insulated gate FETs or IGFETs), and junction-gate field effect transistors or JFETs.

The FET has a control gate and source and drain regions formed in the substrate. The source and drain regions are conventionally formed by implanting ions or dopants such as boron into the surface of the semiconductor substrate. The semiconductor substrate is typically made of single crystal silicon containing heavily doped p + shallow wells formed by ion implantation. A control gate is formed on a dielectric insulator deposited over the region between the source and drain regions. As a voltage is applied to the control gate, the movable charged particles in the substrate form a conductive channel in the region between the source and drain regions. Thus, in the FET, a channel is introduced into the surface of the silicon region between the source and drain regions, and charge tunneling in the channel between the source and drain regions is controlled by a gate electrode provided on the channel. Once the channel is formed, the transistor is "on" and current flows between the source and drain regions.

The number of integrated circuits fabricated on a wafer has increased dramatically year by year. It is well known that the size of each integrated circuit chip can be successfully minimized by improving the technology of integrated circuit fabrication. One approach is to shorten the channel length in the FET. Unfortunately, the shorter channel in FETs has serious drawbacks.

One disadvantage is the need to suppress the leakage current from the capacitor through the gate when the gate is turned off, known as the off-current (I)_off). Current leakage results in a reduction in hold time. As the channel length decreases in DRAM cells, control of gate leakage becomes more difficult. Furthermore, new generations of DRAM products will likely require lower power supplies and longer refresh cycles.

Reduce I_offA common approach is to increase the doping concentration in shallow wells formed in the silicon substrate. If a gate electrode is usedWhen a material is used as a gate electrode of an FET, for example, a p-type polysilicon gate is used as an n-channel FET, a work function difference between a semiconductor substrate and polysilicon is large, thereby a threshold voltage (V)_t) And decreases. Therefore, the channel region is generally ion-implanted with an impurity such as boron having the same conductivity type as the substrate, thereby regularly raising the threshold voltage. Unfortunately, by increasing the doping concentration in the well, storage node leakage, field enhanced junction leakage, and gate induced drain leakage are all exacerbated.

Further, as the channel becomes shorter, the electric field in the channel increases. The mobility of carriers in the channel increases with increasing electric field until a saturation value is reached. If the electric field is continuously increased, the amount of carriers is multiplied in the region close to the drain region. This condition generates substrate current, resulting in parasitic bipolar junction transistors.

Manufacturing defects of conventional FETs in DRAM cells indicate that there is still a need to reduce leakage current from the capacitor through the gate when the transistor is off and junction leakage between the shallow well and source drain regions. In order to overcome the defects of the conventional manufacturing process, a new process is provided. It is an object of the present invention to provide a method of reducing the I of a transistor device_offWhile maintaining a low source-drain junction leakage manufacturing process.

To achieve these and other objects and in view of its purposes, the present invention provides a process for manufacturing a transfer device for a DRAM cell having a capacitor. The boron ion concentration in the channel of the transfer device is higher than that of the drain and source regions. This configuration increases the threshold voltage and decreases I in DRAM cells fabricated by the process_off。

In one embodiment, a transfer device for a DRAM cell is fabricated by the following steps. First, a semiconductor substrate having a source region, a drain region, and a channel region is formed. Next, boron ions are implanted into the silicon substrate. During the implant, the channel receives the highest dose of boron ions, thereby increasing the threshold voltage and decreasing the I in the DRAM cell_off。

In another embodiment, a transfer device for a DRAM cell is fabricated by the following steps. First, a semiconductor substrate having a source region, a drain region, and a channel region is formed. Next, boron ions are implanted into the silicon substrate, forming a portion in the substrate where surface boron is concentrated. After this step, a sacrificial layer is formed on the source and drain regions. Next, boron ions are removed from at least a portion of the source and drain regions, whereby the channel has a higher concentration of boron ions than the source and drain regions, thereby increasing the threshold voltage and decreasing I in the DRAM cell_off。

It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures:

FIG. 1A shows a schematic representation of a FET electrically connected to a trench capacitor;

FIG. 1B shows a schematic representation of a FET electrically connected to a stacked capacitor;

FIG. 2 shows a schematic representation of a silicon substrate with a source region precursor and a drain region precursor;

FIG. 3 shows a schematic representation of the silicon substrate of FIG. 2 with a mask partially formed over the substrate;

FIG. 4 shows a schematic representation of the silicon substrate of FIG. 3 receiving a boron ion implant;

FIG. 5 shows a schematic representation of the silicon substrate of FIG. 2 receiving a boron ion implant;

FIG. 6 shows a schematic representation of the silicon substrate of FIG. 5 with boron ion regions;

FIG. 7 shows a schematic representation of the silicon substrate of FIG. 6 with a gate portion formed on the substrate;

FIG. 8 shows a schematic representation of the silicon substrate of FIG. 7 with oxide layers and nitride sidewalls;

FIG. 9 shows a schematic representation of the silicon substrate of FIG. 8 with portions of the silicon exposed;

FIG. 10 shows a schematic representation of the silicon substrate of FIG. 9 with a sacrificial layer partially formed over the substrate;

FIG. 11 shows a schematic representation of the silicon substrate of FIG. 10 with portions of the concentrated boron region out-diffused into the sacrificial layer;

FIG. 12 shows a schematic representation of the silicon substrate of FIG. 9 with a polysilicon layer formed over the substrate;

FIG. 13 shows a schematic representation of shallow boron distribution in an NFET after two different boron ion implantations;

FIG. 14 shows a schematic representation of source and drain regions in an NFET after two different boron ion implantations; and

fig. 15 shows a schematic representation of boron profiles for three NFET device regions with and without sacrificial layers.

The present invention is described below with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. These figures are illustrative, not limiting, and are included to facilitate the description of the process of the present invention.

Two basic non-planar capacitor designs are currently in use: trench capacitors (shown in fig. 1A) and stacked capacitors (shown in fig. 1B). In conventional trench capacitor DRAM cells, charge is stored substantially in the vertical direction. The DRAM cell of fig. 1A includes a silicon substrate 1 having an n-well 10 and a p-well 11, a Field Effect Transistor (FET)12 formed in the p-well, a trench-type storage capacitor 20, and a buried strap 22. FET12 includes a source region 14, a drain region 16, a gate 18, and a channel 19 adjacent and generally underlying gate 18. The trench storage capacitor 20 is electrically connected to the FET12 through the buried strap 22.

The stacked capacitor stores charge horizontally as shown in fig. 1B. The DRAM cell in fig. 18B includes a silicon substrate 1 and a FET12 formed in the silicon substrate, FET12 includes a source region 14, a drain region 16, a gate 18, and a channel 19 disposed under the gate. Multilayer capacitor 4 includes upper conductive layer 5, insulating layer 6, lower conductive layer 7, dielectric layer 8, and insulating film 9.

It should be understood by those skilled in the art that although only one DRAM cell is shown in fig. 1A and 1B, multiple DRAM cells are typically formed. Further, the present invention can be used to manufacture the trench type capacitor 20 and the stacked type capacitor 4.

It has been found that by heavily doping the channel 19 of the transfer device (i.e., FET), the threshold voltage is increased. Furthermore, it has been found that reducing the boron concentration in the source and drain regions reduces junction leakage around the buried strap and thus reduces leakage current (I) from the storage capacitor when the transistor is off_off). As shown in fig. 2, the process of the present invention begins by providing a silicon substrate 1 having a source region precursor 13 (source region) and a drain region precursor 15 (drain region).

In the first embodiment, a mask 24 having the structures of the gate electrode 18 is formed on the source region 13 and the drain region 15, as shown in fig. 3. In this embodiment, boron ions are implanted only into the region that will ultimately belong to the gate 18. Mask 24 masks at least a portion of the boron ion implantation, limiting implantation into source region 13 and drain region 15, as discussed below. Mask 24 is formed using techniques that are well known in the art and not material to the present invention. If the gate 18 is formed by a positive resist, then preferably the mask 24 is a positive resist. Further, if the gate 18 is formed by a negative resist, it is preferable that the mask 24 is a negative resist.

After forming the mask 24, it is preferable to apply an energy of 1 to 20KeV and 1 to 10X 10¹²/cm²Is performed with boron (B) ion implantation into the surface of the substrate 1 as shown in fig. 4. The implantation of boron ions creates a shallow well region in the portion of the substrate 1 between the source region 13 and the drain region 15 that ultimately belongs to the gate 18. At the position ofThe boron ion implantation into the region of the buried strap 22 is at least partially masked during this step, thereby reducing buried strap junction leakage. After ion implantation, conventional DRAM steps are performed to obtain a complete DRAM cell.

A second embodiment of the present invention is described below. First, a silicon substrate 1 having a source region 13 and a drain region 15 is provided, as shown in fig. 2. Next, as shown in FIG. 5, the energy of 1 to 20KeV and the energy of 1 to 10X 10 are preferably used¹²/cm²Is performed with boron ion implantation to the surface of the substrate 1. The ion implantation produces shallow boron concentrations 28 at the surface of the substrate 1 as shown in fig. 6.

The next step in the process is to form a gate 18 on the silicon substrate 1 between the source region 13 and the drain region 15, as shown in figure 7. The gate 18 is formed using conventional methods well known in the art and not material to the present invention.

Next, as shown in fig. 8, an oxide layer 29 is grown on the surface of substrate 1 along the sidewalls of gate 18 and over source region 13 and drain region 15, also over a portion of concentrated boron region 28. Thereafter, nitride spacers 30 are formed on the oxide layer 29. The nitride spacers 30 are formed using conventional methods such as Chemical Vapor Deposition (CVD) followed by dry etching.

A masking process is then performed in which the DRAM array is exposed or opened while the external support circuitry is covered. A bump mask (not shown) is formed on the external supporting circuit using a conventional technique such as coating a resist and forming a resist pattern by photolithography. However, no bump mask is formed on the DRAM array. Next, the portion of the oxide layer 29 not underlying the nitride spacer 30 is removed by etching, preferably by Chemical Downstream Etching (CDE) or Reactive Ion Etching (RIE). As shown in fig. 9, the etching step produces exposed portions 13a and 15a over the source region 13 and the drain region 15, respectively, of the substrate 1, i.e., over the concentrated boron portions 28. After the etching step, the block-shaped mask is removed.

Next, a sacrificial layer 34 is formed on the exposed portions 13a and 15 a. Preferably, sacrificial oxide layer 34 is polysilicon or oxide. Followed by a Rapid Thermal Oxidation (RTO) of 1, 000 ℃ or higher. RTO causes implanted boron ions to diffuse from the boron-rich portions 28 on the source and drain regions into the sacrificial oxide layer 34, as shown in fig. 11. Since this step is performed after the gate 18 is formed, the channel region is not generally affected.

In a preferred embodiment, as shown in fig. 12, a thin polysilicon layer 36 of about 50 to 100  a is deposited over the source region 13, drain region 15, gate 18, and nitride spacers 30 prior to forming the sacrificial oxide layer 34. The polysilicon layer 36 is then subjected to RTO at a temperature of 1,000 c or higher to cause boron ions to out-diffuse from the concentrated boron portions 28 on the source and drain regions into the polysilicon layer 36. The polysilicon layer 36 is preferably removed by a wet etch process, such as an HF etch.

After the boron ions are out-diffused, a normal DRAM process is performed as described above. Preferably, the sacrificial layer 34 serves as a shield oxide layer in a subsequent step of implanting phosphorus ions. This step is conventionally performed as in normal DRAM fabrication.

The following examples will more clearly demonstrate the overall nature of the invention. These examples illustrate but do not limit the invention.

Example 1

5.5X 10 with energy of 10KeV in NFET¹²/cm²And 4.0X 10¹²/cm²The boron ion implantation. The shallow boron profile of these implants is shown in fig. 13. FIG. 14 shows a graph of 5.5X 10¹²/cm²And 4.0X 10¹²/cm²With two different shallow p-well implant doses for leakage current (I) of the source and drain regions of the NFET_leak) Curve (c) of (d). As shown in fig. 14, the leakage depends mainly on the boron concentration near the substrate surface. Reducing the boron ion dose by thirty percent reduces the face leakage by at least one order of magnitude.

Example 2

Shown in FIG. 15 is an energy of 14.5X 10 at 10KeV¹²/cm²The shallow well boron implant dose simulation boron profile in three regions of the NFET. Simulations were performed using TSUPREM-4. There are three sets of curves, pairsCorresponding to the source and drain regions, the Lightly Doped Drain (LDD), and the channel region. The boron ion concentration is shown as a function of the distance from the top of the gate oxide into the silicon substrate. Each set of curves consists of two curves showing boron profiles with and without a sacrificial layer outdiffusion process.

The effect of boron ion out-diffusion into the sacrificial layer is evident as shown by the two lowest curves, where the boron concentration near the surface is reduced by a factor of three compared to the process without out-diffusion. Boron extraction in the LDD region is also evident, but at a much lower level. In the channel region, the boron profile is hardly changed after boron out-diffusion into the sacrificial layer. These results show that boron outdiffusion into the sacrificial layer satisfies the requirement that the boron concentration in the channel region be higher than the boron concentration in the source and drain regions.

Although illustrated and described herein with reference to specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention.

Claims (20)

1. A process for fabricating a transfer device for a DRAM cell having a capacitor, a threshold voltage, and an off current, the process comprising the steps of:

(a) forming a silicon substrate having a source region, a drain region, and a channel region; and

(b) boron ions are implanted into the silicon substrate, the step of implanting maximizing the boron ion concentration in the channel region, thereby increasing the threshold voltage of the DRAM cell and reducing the off-current.

2. The process of claim 1, wherein the capacitor is one of a trench capacitor and a stacked capacitor.

3. The process of claim 1 wherein the DRAM cell has a buried strap, the capacitor is a trench capacitor, and the capacitor is connected to the transfer device through the buried strap.

4. The process of claim 1, further comprising the step of forming a mask over the source and drain regions prior to step (b).

5. The process of claim 1 wherein the implanting step comprises implanting 1 x 10 at an energy of 1KeV to 20KeV¹²/cm²To 10X 10¹²/cm²Boron ions of (2).

6. A process for manufacturing a transfer device for a DRAM cell, the DRAM cell having a capacitor, support circuitry, a threshold voltage and an off current, the transfer device having a source region, a drain region, a gate and a channel region, the process comprising the steps of:

(a) forming a silicon substrate having a source region and a drain region;

(b) implanting boron ions into the silicon substrate to form a surface concentrated boron portion in the substrate;

(c) forming a sacrificial layer on the source region and the drain region; and

(d) boron ions are removed from at least a portion of the source and drain regions, whereby the boron ion concentration of the channel is higher than the boron ion concentration of the source and drain regions, thereby increasing the threshold voltage of the DRAM cell and reducing the off-current.

7. The process of claim 6, wherein the capacitor is one of a trench capacitor and a stacked capacitor.

8. The process of claim 6 wherein the DRAM cell has a buried strap, the capacitor is a trench capacitor, and the capacitor is connected to the transfer device through the buried strap.

9. The process of claim 6 wherein the implanting step comprises implanting 1 x 10 at an energy of 1KeV to 20KeV¹²/cm²To 10X 10¹²/cm²Boron ions of (2).

10. The process of claim 6, further comprising the step (b1) of forming a gate on the substrate between steps (b) and (c), the gate having sidewalls.

11. The process of claim 10, further comprising, between step (b1) and step (c) of forming the gate, the steps of:

forming an oxide layer on the gate sidewall;

(ii) forming a nitride layer on the oxide layer;

(iii) forming a block mask over the support circuitry leaving an opening over the transfer device; and

(iv) removing the exposed portion of the oxide layer to expose the exposed portion of the substrate.

12. The process of claim 6, wherein step (d) comprises outdiffusing boron ions into the sacrificial layer from boron-concentrated portions adjacent to the source and drain regions.

13. The process of claim 6, wherein the sacrificial layer is polysilicon.

14. The process of claim 6, wherein the sacrificial layer is an oxide.

15. The process according to claim 12, wherein in step (ii) boron ions are outdiffused by rapid thermal oxidation.

16. A DRAM cell includes a transfer device, a threshold voltage, and an off-current, wherein the transfer device includes source and drain regions each having a boron ion concentration, a gate, and a channel disposed adjacent to the gate and having a boron ion concentration higher than the boron ion concentration of the source and drain regions, thereby increasing the threshold voltage of the DRAM cell and reducing the off-current.

17. The DRAM cell of claim 16 further comprising a capacitor.

18. The DRAM cell of claim 17 wherein the capacitor is one of a trench capacitor and a stacked capacitor.

19. The DRAM cell of claim 16 further comprising a capacitor and a buried strap.

20. The DRAM cell of claim 19 wherein the capacitor is a trench capacitor, the capacitor being connected to the transfer device by buried strap.