HK1028701B - Power source and ground planes for printed circuit boards - Google Patents

Description

Power and ground core layer of printed circuit board

This application is related to a copending patent application entitled "LOW CTE POWER AND GROUND PLANES" filed on 7.4.1999 by Japp et al, serial No. 09/288051, which is incorporated herein by reference.

Technical Field

The present invention relates generally to the field of computer manufacturing, and more particularly to reducing delamination and cathode/anode filament growth of circuit boards used in computers.

Background

Computers and similar electronic devices are widely available in people's daily lives. Many commercial, banking, and government agencies rely on computers to engage in their daily activities. Most of the whole society needs computers to perform their economic, social and communication activities reliably and stably. Computers are today required to run longer and to be down time shorter than ever before.

Because computers are so needed, computer designers have placed more emphasis on their reliability. Many systems today do not allow for significant downtime to replace failed components that make up a computer system. If each component is designed to have a longer life and be more reliable, then each computer that consists of only those components will have a longer life and be more reliable.

The reproduction of component reliability is also applicable to Printed Circuit Boards (PCBs). Most components in a computer system are designed by placing a semiconductor package or chip on a PCB. PCBs are referred to as "printed" because the circuit traces or copper traces are laid out on the circuit board using techniques that were originally similar to the newsprint printing process. These circuit lines connect together the semiconductor packages or chips. PCBs may simply be formed as insulators having printed wiring on one or both faces thereof and having one or more components secured to one or both faces thereof. PCBs, however, have generally become more complex, generally consisting of conductive metal power and ground layers and several signal layers containing circuit lines sandwiched between several insulating layers with metal lines and pads on the top and bottom surfaces of the layers. The upper and lower conductors are connected to each other and to the internal circuit layer by Plated Through Holes (PTHs).

PCBs manufactured in this manner have become standard electronic products. Advances in manufacturing methods have made PCBs relatively inexpensive. But their simplicity makes them more reliable. However, problems associated with PCBs still exist. One of the reasons for some of these problems is water. The insulation in PCBs is permeable to water and naturally absorbs higher concentrations of water. Even if the PCB is dried when the component assembly process is completed, it may absorb water from humid air or through other processing steps after a while. Therefore, PCBs contain water, which freely permeates the insulating layer. Unfortunately, the power source and formation, which are typically constructed of copper metal, are impervious to water.

The lack of water permeability affects the PCBs and may cause failure. Water collects at the interface between the power source/formation and the insulating layer sandwiched between the power source/formation. A chip, chip-carrier package, or other component is soldered to the PCB (typically using wave soldering or infrared heating). These increases in temperature may cause water that has collected at the interface between the power source/formation and the insulation to evaporate into steam. As the water changes to steam, the volume of the water increases significantly, and this expanding water/steam mixture can cause insulation stripping. In fact, "blisters" can also occur on the surface of the insulator, leading to cracking of the insulator, wire breakage, package cracking, cracking of the PTH via, and other similar deleterious effects.

Because water "escapes" the confines of the insulator, it must diffuse through the insulator to the low water concentration zone. Such low water concentration areas are typically only present at the periphery of the PCB including the upper and lower surfaces where the stacks encounter air. Given the fact that water is present in low concentrations in air, it will take a long time for the water to diffuse through the medium to the atmosphere. Until the water is removed from the PCB, however, the water can cause bubble damage.

Another mechanism of water failure in PCBs is cathode-anode filament growth (CAF), which occurs along the glass fibers when the circuit board is shorted. This short circuit occurs when water leaches metal ions from adjacent conductors to the interface between the glass fiber and the media. Upon electrical biasing, copper ions deposit, which tends to form conductive dendrites. In the case of a solution, the material will generally ionize and thus transform to an oppositely charged metallic state. The cathode is a positively charged region and the anode is a negatively charged region. Metal dendrites generally grow between two oppositely charged local cathode/anode regions. These conductive metal dendrites can cause electrical shorts.

The use of PCBs as chip carriers has somewhat exacerbated the failure mechanism caused by water. A chip carrier is a device on which a chip is mounted and connected before being connected to a circuit board. In the past, these chip carriers were almost exclusively made of ceramics. Since ceramics are used as chip carriers, the Joint Electron Device Engineering Council (JEDEC), an entity responsible for promulgating electronic manufacturing standards, proposed test standards for chip carriers, mainly assuming that the substrate material of the base does not absorb water at all. PCBs have now begun to be used as chip carriers, and water migration and the problems associated therewith are more prevalent because of the greater water content that tends to exist in these organic materials. Chip carriers composed of organic stack materials are referred to as stacked chip carriers (LCCs).

Thus, without a way to limit failures caused by cathode/anode dendrite growth and insulator delamination in organic LCCs, PCBs and LCCs will continue to suffer from a number of failures and reliability problems.

Disclosure of Invention

According to an aspect of the present invention, there is provided a power/ground core layer for a printed circuit board, the power/ground core layer including: a first water-permeable, non-conductive layer of a first fiber stack; and a first metal sheet comprising a two-dimensional distribution of through-holes formed through the first metal sheet, wherein the first non-conductive layer is in contact with a surface of the first metal sheet, the first metal sheet is permeable to water only through its through-holes, the through-holes in the first metal sheet do not extend into the first non-conductive layer, the through-holes in the first metal sheet have a spacing therebetween, the spacing and diameter of the through-holes in the first metal sheet are sufficient to allow water in the first non-conductive layer to pass through the through-holes in the first metal sheet sufficiently quickly to prevent water in the first non-conductive layer from collecting at an interface between the first non-conductive layer and the first metal sheet.

According to another aspect of the present invention, there is provided a power/ground core layer for post-production use of a printed circuit board, the power/ground core layer comprising: a first water-permeable, non-conductive layer of a first fiber stack; and a first conductive layer that does not include a metal sheet having a via formed through itself, wherein the first non-conductive layer is in contact with a surface of the first conductive layer, the first conductive layer comprising a first conductive material that is sufficiently porous to allow water in the first non-conductive layer to pass through the first conductive layer via the first conductive material sufficiently quickly to prevent water in the first non-conductive layer from collecting at an interface between the first non-conductive layer and the first conductive layer.

Accordingly, embodiments of the present invention provide power and ground layers for Printed Circuit Boards (PCBs) that include porous conductive material. The porous power and formation materials allow water and/or other solvents to pass through the power and formation, which can reduce failure of PCBs (or PCBs used as stacked chip carriers) and insulation stripping due to cathode/anode filament growth. The porous conductive material may be formed using a metal-coated cloth (e.g., polyester) or fabric (e.g., those composed of carbon/graphite or fiberglass), using a wire mesh instead of a metal sheet, using sintered metal, or by making a metal sheet porous by forming an array of pores therein. The metal mesh or fabric may be made into a woven or random paper structure. If the array of apertures is formed in a metal sheet, such an array can be formed without any additional processing steps compared to using conventional methods.

The foregoing and other advantages and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

Drawings

Preferred exemplary embodiments of the invention will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and:

FIG. 1 is a cross-sectional perspective view of a power core layer patterned in accordance with a preferred embodiment of the present invention;

FIG. 2 is a top view of a power core layer patterned in accordance with another preferred embodiment of the present invention;

FIG. 3 is a cross-sectional view of a preferred power source or formation for use in several embodiments of the present invention;

FIG. 4 is a cross-sectional view of a six-layer printed circuit board and the layers that make up the six-layer printed circuit board in accordance with a preferred embodiment of the present invention;

FIG. 5 is a process flow diagram of a method of making and using a power source or formation according to a preferred embodiment of the invention;

fig. 6 is a cross-sectional view of a six-layer printed circuit board and the layers that make up the six-layer printed circuit board.

Detailed Description

Preferred embodiments of the present invention overcome the limitations of the prior art by providing Printed Circuit Boards (PCBs) with power and ground layers that employ conductive porous materials. These materials are preferably permeable to water and other solvents. The present invention relates to the manufacture of PCBs. A brief description of the general manufacturing techniques for PCBs is given below, followed by the preferred embodiment.

For the manufacture of printed circuit boards, the starting material is generally a sheet consisting of glass fibers and epoxy resin. This is generally referred to as "prepreg" since the fibers are impregnated with resin during initial processing. The resin acts primarily as a binder, binding the fibers to the board. Instead of fiberglass cloth, compressed paper or other suitable material may be used. Thus, the substrate is a flat rigid or slightly tough dielectric material that will be fabricated into the final printed circuit. The starting material may be laminated to both sides of the board together with a thin layer of copper using a suitable adhesive. This combination is commonly referred to as a Copper Clad Laminate (CCL). These CCLs can be converted into simple double-sided boards (with double-sided copper wires) or can be circuitized and laminated with additional media to form a multilayer composite.

In most cases, small holes (typically drilled) are formed through the plates to accommodate electrical connections to the various electronic components to be mounted. The holes are typically drilled with a high speed drill and the location of the holes is shown in the drawings or depending on the design of the plate.

In order to make an electrical connection from one side of the copper stack through the aperture to the other, the plastic wall of the aperture must be made conductive. This can be accomplished by chemical processes known in the industry, such as metallization, which consist of a relatively complex series of chemical bath treatments, rinses, and activation steps to deposit a thin layer of copper on the walls of the hole.

Since the copper layer formed by the metallization process is typically too thin for forming a suitable electrical bridge between the two layers of the board, copper electroplating is used to deposit a thick copper layer in the small hole to form a suitable copper section for carrying the current. The copper plating may be followed by tin-lead or tin plating to improve solderability.

After metallization, the circuit is processed on those surfaces where a circuit pattern is desired. A circuit pattern is a circuit design that applies specification or design requirements to the metal surface of a drilled plate. Images can be formed by applying an organic photoresist blanket as a dry film. Ultraviolet (UV) light is projected onto the photoresist through a mask. The mask contains a pattern that blocks UV light. For negative tone photoresists, the areas of the photoresist not exposed to UV light will be removed in a subsequent development step. The exposed surface metal is then removed by chemical etching. Then, the remaining photoresist is stripped, leaving only the metal pattern.

Referring now to fig. 6, an example of a six-layer PCB and the layers making up the six-layer PCB is shown. In fig. 6, parts of a PCB are shown at different stages of manufacture. The six-layer PCB120 includes a "composite" formed by pressing together (referred to as "lamination") two signal core layers 101 and 130, one power core layer 111, and dielectric layers 150 and 152. The core layers are individually patterned and then pressed together to form the composite PCB. During such lamination, the dielectric will flow back into any gaps present between the core layer and the dielectric layer. After lamination, the composite is drilled, the epoxy applied to the exposed copper layer of the drilled hole is removed, the through hole is plated, and the process is performed. For simplicity, FIG. 6 shows the media recirculation zone containing air in place of the media. Further, Plated Through Holes (PTHs) are shown as solid metals, although generally cylindrical metal holes. Finally, the tooling holes (tollinghole) that will be used to align the workpiece with the stack and layers are not shown.

The signal core layer 100 includes a dielectric layer 104 sandwiched between two copper layers 102 and 105. The signal core layer 100 is an unprocessed CCL. Copper layers 102 and 105 are signal carrying layers on which copper lines are to be formed. The copper layer 102 may also have pads to which each chip or surface mount package containing the chip will be soldered. The signal core layer 101 represents the signal core layer 100 after patterning of the signal core layer 100. The signal core layer 101 includes copper layers 102 and 105 that have been patterned with circuitry, gaps for PTHs and other gaps/tooling holes and dielectric layers 104. Copper layer 102 has two lines (not numbered) and two pads 107 and 103, while copper layer 105 has five lines. Further, the copper layer 105 has a gap region 170 through which PTH passes after the signal core layer 101 is laminated into a composite, and drilling and hole plating are performed.

The power core layer 110 in fig. 6 includes a dielectric layer 114 sandwiched between two copper layers 112 and 115. Copper layers 112 and 115 may be thicker than copper layers 102 and 104 to provide additional current carrying capability. The power core layer 110 is the untreated CCL copper layer 112 that will become the power layer of the PCB, while the copper layer 115 will become the ground layer of the PCB (and vice versa). The power core layer 111 represents the power core layer 110 after the power core layer 110 has been patterned. The power core layer 111 includes patterned copper layers 112 and 115 and a dielectric layer 114. Copper layer 112 is patterned to have two gap regions 182 and 179, while copper layer 115 is patterned to have two gap regions 184 and 180. These interstitial regions will prevent the power and ground layers from contacting the PTHs that are drilled at these locations after the power core layer 111 is laminated into a composite and the holes are drilled and plated.

The completed PCB section is illustrated as a six-layer PCB section 120. Such PCBs are commonly referred to as "six-layer" boards because of the six conductive layers. The six-layer PCB section 120 is shown after the signal core layers 101 and 130, the power core layer 111, and the dielectric layers 150 and 152 are laminated to form a composite. The composite has been drilled and the coated epoxy removed from the holes. The pinholes have been plated. In addition, components are mounted on the completed PCB. For example, the J-lead package 160 may be soldered to the pads 170 and 103 of the copper layer 102 of the signal core layer 101. Signal core layer 130 is a signal core layer that is patterned similarly to signal core layer 101. The signal core layer 130 includes copper layers 132 and 135 and a dielectric layer 134. Copper layers 132 and 135 have formed a patterning line. A dielectric layer 150 has been applied between the power layer (copper layer) 112 of the power core layer 111 and the copper layer 105 of the signal core layer 101, while a dielectric layer 152 has been applied between the ground layer (copper layer) 115 of the power core layer 111 and the copper layer 132 of the signal core layer 130. Each dielectric layer 150, 152 may be comprised of more than one dielectric layer.

Several PTHs are shown in PCB 120. PTH 109 connects power layer 112 and J-lead 161, lines on patterned copper layer 105, and lines on patterned copper layer 135. The gap region 180 may prevent the PTH 109 from shorting to ground. Note that after lamination, the gap region 180 will be filled with a reflow medium, but for simplicity, it is not shown in fig. 6. PTH 108 connects signal lines on copper layers 102, 105, 132, and 135. Interstitial regions 184 and 182 may prevent PTH 108 from contacting formation 115 or power plane 112, respectively. PTH 106 connects ground layer 115 with lines or pads on copper layers 135, 132 and 102.

It should be noted that although the electrical interstitial pores allow some amount of localized water to pass through, they do not provide sufficient permeability for moisture necessary to prevent or eliminate cathode/anode filament growth effects or delamination. For example, in fig. 6, the interstitial regions 180 allow some water to pass near the regions, but the size of the regions has been exaggerated for clarity, and is small in actual LCCs. The distances and sizes between the PTHs are also exaggerated for clarity, with most areas actually being larger in distance and smaller in size. Thus, typically some small amount of moisture between the power layer and the PTH may pass through its diffusion site, but these small amounts near the PTHs are not sufficient to provide the permeability necessary to prevent or reduce cathode/anode filament growth effects or delamination.

The insulating or dielectric material used for PCBs is capable of retaining a relatively high amount of water. These materials absorb water during processing. They also have a moderate diffusion constant that allows water to pass through. In contrast, the power source and formation are typically copper, not allowing water to pass through. The metalized power and formation are the primary barriers to diffusion as water diffuses through the insulator. Water then collects at the power/formation and dielectric layer interface.

Preferred embodiments of the invention overcome the limitations of the prior art by providing power and ground layers for Printed Circuit Boards (PCBs) (or PCBs used as stacked chip carriers (LCCs)), and containing electrically conductive porous material. By providing high permeability, these power and formation materials allow water or other solvents to pass through the power/formation, thereby reducing or eliminating cathodic/anodic filament (CAF) growth and bubbles due to swollen solvent. Water is the main cause of CAF, but other solvents are known to cause peeling. Specifically, solvents that cause exfoliation or bubble effect are trichloroethylene, methylene chloride, benzyl alcohol and propylene carbonate.

The preferred embodiment includes various electrically conductive porous materials that may be used for power sources and strata of PCBs. There are many materials that meet the requirements of porous power sources and formations. For example, embodiments of the present invention may be bulk metalized (metal foil with an array of small holes, sintered/powdered metal, wire mesh, etc.) or may have a fibrous base material (metal coated carbon fibers, metal coated glass fibers, metal coated polyester, etc.) that provides enhanced electrical conductivity through metallization. Depending on the type of conductive material of the substrate used, pores with low moisture diffusion and functional electrical interstitial pores can be formed by different processes.

Before discussing the preferred embodiments, it is helpful to briefly discuss the terminology. As described in the summary section, the term "prepreg" generally includes glass fibers and epoxy resins. Because the fibers are impregnated with resin during processing, they are often referred to as "prepregs". The sheet of fibrous material containing resin is generally referred to as a "fibrous resin composite", and the sheet of fibrous material may be referred to as a "fibrous composite". Unfortunately, when one or more signal layers are laminated with one or more power/ground layers, or when power/ground layers are laminated between prepregs, it is referred to as a "composite". To avoid confusion of such composite structures with fiber composites or fiber resin composites, the fiber composites and fiber resin composites will be referred to as "fiber laminates". The term 'fiber laminate' is intended to include all types of prepregs, fiber composites, fiber resin composites, media, insulators and other materials commonly used in PCB manufacture. In addition, embodiments of the present invention may use conductive fiber laminates (e.g., prepregs impregnated with copper). It should also be noted that although the term "fiber laminate" is used herein, the term is intended to refer to all types of thermoset resins and thermoplastic polymers currently used to construct PCBs, including, but not limited to, epoxy, bismaleimide triazine epoxy, cyanide esters, polyimides, Polytrifluoroethylene (PTEE), and other fluoropolymers, and the like, whether or not they contain any fibers or fillers.

Porous metalized power and formation layers can be fabricated in many ways. The most preferred method of fabricating the porous metal power layer is to form a large number of small holes in the metal foil that is typically used in the manufacturing process for PCBs. By forming an array of holes in the metal foil, the metal foil will be relatively permeable to water. The apertures are preferably sized between 0.001 and 0.010 inches in diameter and spaced apart from one another by a maximum of 0.050 inches to provide suitable permeability to water or other solvents. The most preferred diameter is 0.002 inches, so large diameters can be formed using conventional lithography, and allow for proper power distribution even at spacings less than 0.050 inches. The smaller holes may be formed by non-standard processes such as laser drilling. Generally, the minimum spacing between the holes is dependent on the electrical design requirements for current carrying capability. While other sizes and spacings may increase the transfer of water/solvent through the power source/formation, a given spacing and size allows sufficient water transfer without significantly compromising the current distribution capability of the metal layer. These spacings and dimensions are preferred.

The size and spacing of the apertures can also be affected to some extent by the time and manner in which the apertures are formed in the metal foil. The preferred time for forming the apertures in the metal laminate is during the imaging/etching step. Imaging processing of the power supply and formation has been performed to remove the metal of the interstitial holes to which the PTHs will not connect. In addition, designs with both digital and analog components on the same PCB typically have separate power and ground layers. The digital circuit has one set of power and ground layers and the analog element has another set of power and ground layers. These separate layers require certain regions of the power source/formation to be removed during the imaging step. Since imaging has been performed during these steps, a simple change to the imaging process can form small holes to increase the permeability of the power/formation.

For example, if a photolithographic process is used to remove portions of a layer, a photoresist may be applied to the surface of the layer. As described above, the photoresist is exposed to Ultraviolet (UV) light through a mask to form unexposed (polymerized) photoresist regions that remain after resist development. After the unexposed photoresist is removed, the underlying copper is exposed. The exposed copper areas are then removed during etching, while the copper areas covered by the resist are protected from the etchant. To form the aperture array or apertures in the copper layer, the mask can be modified to include opaque regions that will form the aperture array in the laminate. How the mask forming the array is changed depends on the kind of process used. For example, if a positive photoresist is used, the image on the mask will be the opposite of the mask used for a negative photoresist. It is well known in the art to fabricate masks that are patterned with a particular photoresist. A photolithographic process may be used which may form relatively small holes.

Patterning of layer surfaces with screen-printed inks is also well known in the art. A screen is similar to a mask in the sense that it blocks ink that is pushed through the screen and onto the layer. The image on the screen is the inverse of the image to be formed on the layer (negative type). The ink is protected from the corrosive agent during the subsequent etching step; areas of the layer that are free of ink will corrode and metal in these areas will be removed. If an array of small holes in the metal foil is required, an array of "islands" is typically formed on the screen. The islands on the screen will block the ink and form small holes in the ink deposited on the surface of the layer. After etching, these holes in the ink will then become pinholes in the metal laminate. After etching, another process step removes the ink. Masking a plurality of small holes in the laminate necessarily results in larger holes, since it is difficult, if not impossible, to form very small holes using this method.

Fig. 1 shows a portion 200 of a power core layer that has been fabricated in accordance with a preferred embodiment of the present invention. The power core layer 200 includes a power layer 202 (copper layer), a dielectric layer 204, and a ground layer 205 (second copper layer). The power core layer 200 (prior to drilling, etc.) is lithographically and etched with a CCL similar to the power core layer 110 previously shown in fig. 6, forming an array of penetration holes 220 and clearance holes 210, 250. The clearance holes 210, 250 serve to isolate the power plane 202 or the formation 205 from the PTHs (or tooling holes). The permeation pores 220 form a relatively parallel array of rows and columns. Location 260 indicates where the permeation pores 220 in the array are located, but the permeation pores 220 are too close to the interstitial pores 210 and are omitted. Although this example shows the permeation holes 220 at locations 260 being omitted, the reason for the omission is that a degree of permeability has been provided by the interstitial holes 210. If desired, a permeate hole at location 260 can be made. The clearance holes 210, 250 may be fabricated during processing by a photolithographic process (although the tooling holes are fabricated in a tooling holes step). The penetration holes 220 can then be fabricated in the same lithographic step as the fabrication of the clearance holes 210, 250.

Although the array of apertures 220 is shown as parallel rows and columns, other arrays are possible. For example, the columns or rows may be staggered, as shown in FIG. 2. Fig. 2 shows the upper surface (copper layer 202) of a portion of the power core layer 280. The columns of holes 220 are along parallel lines and the rows of holes 220 are also along parallel lines, however, the positions of the holes along these lines are staggered or alternate.

Further, although these examples discuss copper foil, it should be noted that the technique may also be applied to power plane conductors composed of other metals and combinations of metals such as copper/nickel-iron alloy/copper and copper/stainless steel/copper.

A power core layer having an array of holes 220 as shown in fig. 6, such as power core layer 200, may be used, but the processing steps are hardly changed except for the small changes described for the photolithography or screen printing ink steps.

As noted above, other materials besides copper foil may be used to provide a porous power source or formation for PCBs or LCCs. Some of these materials can be brittle during the drilling stage of PCB or LCC fabrication. For example, fibrous materials can be more easily damaged than metal foils during drilling. In addition, since photolithography and etching techniques are not capable of patterning some of these porous power and ground layers, it is preferable to make some specific changes to standard PCB or LCC fabrication steps. Before turning to a discussion of other materials that may be used in porous power sources and formations, general steps involved in utilizing and fabricating porous power sources/formations constructed of porous materials will be discussed.

Referring now to FIG. 3, three preferred configurations of porous power sources and formations are shown. Each structure is manufactured with slightly different processing steps using the porous power or formation of the PCB/LCC. The most preferred structure of the porous power source and formation is shown as power source/ground core layer 300. The power/ground core layer 300 comprises a porous layer 304 sandwiched between two fiber laminates 302, 305. Two clearance holes 310 are shown which have been drilled in the power/ground core layer 300 to provide clearance for the PTHs after the power/ground core layer 300 is laminated with another power/ground core layer and one or more signal core layers. The lamination forms a composite that is subsequently drilled and metallized to form a PCB or LCC. By laminating the porous layer 304 between the two fiber laminates 302 and 305, the fiber laminates provide protection for the porous layer during drilling and shipping. The fiber stacks 302, 305 may be either non-conductive or conductive. In the case of the latter embodiment, the power/ground core layer 300 will be a conductive composite. The power/ground core layer 300 is then stacked between two non-conductive fiber stacks to form a larger "core" or the power/ground core layer 300 is stacked with other signal layers, power/ground core layers, and non-conductive fiber stacks into a PCB composite.

Fig. 3 also shows second and third less preferred configurations of porous power sources and formations that are more susceptible to drilling and transport damage. The power/ground core layer 320 comprises a fiber stack 324 sandwiched between two porous layers 322, 325. Additionally, the fiber stack 324 may or may not be conductive. The power/ground core layer 320 has been drilled with clearance holes 330. The power/ground core layer 350 includes a porous layer 352. Similarly, the power/ground core layer 350 has been drilled with clearance holes 360. These are less preferred embodiments of the power/ground core layer since the porous layer is susceptible to drilling and transport damage. However, minimal or no damage to the porous material from which the power source/formation is made may also be possible if care is taken during transportation and drilling. Sealing porous materials in a stack of fibrous layers that are susceptible to damage from shipping or drilling is preferred because it reduces the likelihood of damage.

Each of these core layers may be treated in a slightly different manner. Generally, the power/ground core layer 300 will be laminated after an optional adhesion enhancement process (using a chemical such as silane) is performed on the porous layer 304. Clearance holes 310 are then typically drilled in the power/ground core layer. This stage uses drilling instead of patterning and etching with photoresist, since the fiber stack (its dielectric or conductive material) cannot be etched in general. In addition, the clearance hole 310 may be filled with an insulator/media in this step. The drilled power/ground core layer 300 may then be laminated into a composite with another power/ground core layer and one or several signal core layers. The composite is then drilled and metallized (as PTHs) to form a PCB or LCC. Alternatively, the power/ground core layer 350 may be drilled and treated with an adhesion enhancing process and then laminated with two fiber laminates to form the power/ground core layer 300. Although the power/ground core 350 may be mechanically drilled to form clearance holes and tooling holes, laser or other less damaging drilling methods are preferred for power/ground core materials that are susceptible to drilling damage.

In general, the power/ground core layer 320 may be formed by treating the porous layers 322, 325 with an adhesion-promoting process (optional). The fibrous pack (conductive or non-conductive) is then stacked between the two porous layers. Drilling is then typically performed to form clearance (or tooling) holes 330. For power/formation materials that are susceptible to damage from drilling, laser or other less-damaging drilling techniques are preferably employed. An additional advantage of laser drilling in this embodiment is that the two conductive porous layers can be patterned with different mesopore patterns. The gap or machined hole is then filled with an insulating/dielectric material. The power/ground core layer 320 is then laminated with another power/ground core layer and one or several signal layers into a composite.

In general, holes may be drilled in the power/ground core layer 350 and treated with an optional adhesion enhancing material (e.g., silane or copper oxide treatment) and then laminated with two fiber laminates (conductive or non-conductive) to form the core layer 300. Alternatively, the power/ground core layer 350 may be drilled and treated with an adhesion enhancing step and then laminated with another power/ground core layer, several fiber laminates, and one or more signal core layers to form a composite. For example, to form a six-layer composite, the layers from the "upper" layer to the "bottom" layer of the composite are as follows: a signal core layer (e.g., signal core layer 101 of fig. 6), one or more fiber stacks, a power/ground core layer 352, one or more fiber stacks, and a second signal core layer (e.g., signal core layer 130 of fig. 6). The composite is then drilled and metallized to form the PCB/LCC.

As noted above, it is preferred that the conductive material be used in a porous power source or formation that will be formed into a power/ground core layer that is susceptible to damage from drilling or transport, wherein the porous conductive material is sandwiched or sealed between two fiber plies. The power or ground core layer formed in this manner will support and protect the porous conductive material during the drilling step. This protection reduces the amount of fibrous material that may be broken by the drilling process. Power core layers such as power core layer 320 (similar to power core layer 110 of fig. 6) or power core layer 350 may also be fabricated, but drilling and/or shipping may cause the porous material to crack and craze to some extent. In addition, loose fibrous material can contaminate certain processing steps. By sealing the fibrous material and filling the drilled holes with insulation/media, the fibrous material is less likely to contaminate subsequent processing steps.

Referring to fig. 4, there is shown several cross sections of power and ground core layers and a six layer PCB/LCC made up of these core layers. FIG. 4 is an example showing a power core 1000, a drilled power core 1001, a ground core 1010, a drilled ground core 1011, and a six-layer PCB/LCC 1020. The power core layer 1000 is formed by performing an adhesion enhancement process on the porous power layer 1004 and then laminating the layer with two dielectric layers 1002 and 1005. Then, the power core layer 1000 is drilled to form clearance holes 1082 and 1079. After the photoresist mask is applied, a "standard" CCL power core layer is etched to form the imaged power core layer (i.e., power core layer 111 of fig. 6). Because corrosion is not possible with some porous conductive materials used in power/earth formations or fiber laminates, it is preferable to use drilling to form the mesopores. The power core layers 1000 and 1001 in this example are essentially porous conductive layers sandwiched between two stacks of non-conductive fibers. The ground core layer 1010 is formed by subjecting the porous ground layers 1012, 1015 to an adhesion enhancing process and then laminating the layers on both sides of a stack of conductive fibers. Then, core layer 1010 is drilled to form clearance holes 1084 and 1080. The ground core layer 1010 in this example is essentially a conductive layer having three conductive layers (a conductive fiber stack sandwiched between two porous conductive material layers). Although not shown in fig. 4, a dielectric or other insulator may be added to the power core 1001 and ground core 1011 to fill interstitial holes in these cores.

With respect to the conductive fiber layer 1014, a preferred method of forming this layer is to incorporate 40% copper powder by volume into the fiber or fiber/resin layer. During lamination, the copper should be uniformly distributed in the fibre layers. Other conductive fillers and other types of layer materials may also be used, but the fillers and layer materials have the advantage of being less expensive and of being materials commonly used in PCB manufacture.

After core drilling (with the addition of insulation if required), the power core 1001 and ground core 1011 are pressed together with the patterned signal cores 101, 130 and fibre lay-up 1099 to form a composite. The composite was drilled and metallized to form PTHs. After the components are secured to the PCB/LCC, an exemplary six-layer PCB/LCC portion 1020 results. The fiber stack 1099 is a non-conductive dielectric layer that separates the signal layer 132 from the ground core layer 1011, and in particular, the porous layer 1015 of the ground core layer 1011. There is an equivalent stack of fibres between the power core 1001 and ground core 1011 to adhere the two layers together.

The PTH 1008 connects the lines of the signal layers 102 and 105 of the signal core layer 101 with the lines of the signal layers 132 and 135 of the signal core layer 130, similarly to the PTH 108 of fig. 6. The interstitial regions 1082 and 1084 prevent the respective ground and power layers from contacting the PTHs. Although gap regions 1082 and 1084 are shown as being filled with "air," in practice, these regions are typically filled with dielectric, either after drilling the power or ground core layers, or during lamination.

PTH 1009 is similar to PTH 109 of fig. 6, and connects pad 103 on layer 135 of signal core layer 130 and line and power layer 1001. The gap region 1080 prevents the PTH 1009 from connecting to the ground core layer 1011. Similarly, PTH 1006 is similar to PTH 106 of fig. 6, connecting lines on layer 102 of signal core layer 101 and lines on layers 135, 132 of signal core layer 130 with ground core layer 1011. In this example, the ground core layer 1011 includes three conductive layers (two porous layers 1012 and 1015 and one conductive fiber laminate 1014) which are all connected to the PTH 1006. The gap region 1079 prevents the PTH 1006 from connecting to the power layer 1004.

In the example of fig. 4, it is shown that most of the fiber stacks separating the core layers are thin. For example, fiber stacks 1002 and 1005 are thin. This is merely for the purpose of indicating that more plies, thinner or thicker fiber plies may be added if desired, as will be appreciated by those skilled in the art. The six-layer PCB/LCC1020 of FIG. 4 is comparable to the six-layer PCB/LCC 120 of FIG. 6 with little difference except that the PCB/LCC1020 has separate power and ground layers. PCB/LCC1020 also has porous power and formation layers that allow water or other solvents to freely disperse throughout the layers comprising PCB/LCC 1020. Porous power supplies and strata limit cathode/anode filament (CAF) growth and failures due to insulator stripping.

Fig. 5 illustrates a preferred method of forming a power or ground core layer (e.g., power core layer 1000) comprising a porous conductive material according to the present invention. The method 400 of fig. 5 is preferably used to form power and ground core layers to combine the power and ground core layers into a composite PCB or LCC. This method can also be used in the preferred embodiment where a porous conductive material is sandwiched between two fiber laminates as the power plane 1000. This embodiment may better protect the inner porous conductive material. In addition, the fiber lay-up may help to "seal" the fiber material covered with metal and other loose materials, which helps to hold the inner fiber material to the laminate. This is particularly beneficial in the case of carbon materials that may contaminate various parts of the PCB/LCC and the manufacturing process. The method 400 begins by forming an optional thin metal coating on the porous material used (step 410). The metallized fibrous materials of the present invention are generally metals sufficient to carry the required current; more metal may be formed on the fiber at step 410 if additional current carrying capacity is required.

Furthermore, if the preferred porous materials of the present invention are not metallized, these materials may also be metallized at this step. For example, if unmetallized carbon fiber tow is used as the porous material, the tow may be metallized and formed into a woven fabric at step 410. Additional metal is then attached to the fabric at step 410, if necessary. Briefly, step 410 may be used to metalize the non-metal coated material and add additional metal to the metal coated material. Following the method 400, preferred material types for the power source and formation will be discussed in more detail.

The porous material is then optionally treated with an adhesion enhancing chemical process or a copper oxide treatment (step 420). Conductors are then laminated between the two fiber laminates to form a sealed porous power or ground core layer (step 430). Typically, the porous ground/power supply materials are laminated using standard lamination processes. Alternatively, the fibrous porous material may be impregnated with resin using standard impregnation processes (step 433). This standard impregnation process substantially encapsulates the fibrous material. The resin impregnated cloth is then laminated against a release sheet (release sheet) or roughened copper foil. If a roughened copper foil is used, it may be etched away (step 437) or stripped by drilling (step 440). The release tab is typically removed prior to drilling (step 435).

Since the fiber stack is generally not etched to form the necessary electrical interstitial holes (and other openings), these openings are formed in the electrical power/ground core layer (step 440). Generally, these openings can be formed in and through the laminate and porous layer by drilling a pattern of interstitial holes or machining holes. Drilling may be performed by mechanical drilling or by laser or other similar hole forming equipment. If the roughened copper foil has been laminated onto the porous material (step 435) and has not been removed (step 437), it can now be removed by etching (step 445). At this point, the opening may be refilled with pure resin, the resin containing a non-conductive filler or other suitable insulator/medium (step 450). The power/ground core layer is introduced into the composite, preferably by being re-laminated or pressed onto a composite panel structure (step 460). If the holes are not filled at step 450, additional resin flows from the fiber lay-up to and fills the power layer holes of the bore hole during the lay-up cycle. Holes for the PTHs may then be re-drilled and metallized (step 470). After step 470, a PCB/LCC similar to PCB/LCC1020 will be formed.

Although method 400 is the preferred method for fabricating PCB/LCC using porous power/ground layers, the steps of method 400 may vary somewhat depending on the structure of the power/ground core layer used. For example, two layers of porous conductive material may be laminated to the fiber laminate as previously shown, for example, in power and ground core layer 320 of fig. 3. In this example, the processing steps remain very similar to those shown in method 400. For example, steps 410 and 420 of method 400 may be performed, respectively, to add additional metal to the conductive material and enhance adhesion. The fibrous pack (conductive or non-conductive) is then laminated between the two porous layers. Drilling is then typically performed to form clearance holes or tooling holes (step 440). For power/formation materials that are susceptible to borehole damage, it may be preferable to use a laser or other less-susceptible drilling method. An additional advantage of laser drilling in this case is that the two conductive porous layers can be patterned with different patterns of mesopores. The gap or machined hole may be filled with an insulating material at this stage (step 450). The power/ground core layer 320 is then laminated with another power/ground core layer, one or more signal layers, and a non-conductive fiber into a composite (step 460). The composite is then drilled and metallized to form the PCB/LCC (step 470).

In addition, a power/ground core layer similar to power/ground core layer 350 of fig. 3 may also be used to form the power or ground layer. In this example, the processing steps used to form the power source and formation are somewhat different than in method 400. For example, drilling (step 440) may be performed before or after step 410 (if performed). The porous conductive layer may then be treated with an optional adhesion enhancing material (step 420) and stacked with two fiber stacks (conductive or non-conductive) to form the core layer 300 of fig. 3. In this example, step 450 is generally unnecessary because the lamination process can fill each hole with a stack of fibers. Alternatively, a porous conductive layer similar to the power/ground core layer 350 may be drilled and treated with an adhesion-enhancing step (step 420), and then laminated with another power/ground core layer, several fiber laminates, and one or more signal core layers into a composite (step 460). The composite is then drilled and metallized to form the PCB/LCC (step 470).

Finally, the method 400 may be applied to PCBs in other configurations than the six-layer PCB shown in FIG. 4. By applying the process of method 400 to a particular number of layers, a greater or lesser number of layers may be formed. For example, (referring again to fig. 4), if a four layer PCB is desired, the power core layer 1000 may be laminated on the outer surface of the copper laminated layer 1002. The power core layer 1001 is then drilled. Similarly, the core layer 1010 may be laminated on the outer surface of the layer 1015 with the fiber laminate and the copper laminate. The ground core 1011 is then drilled. The openings formed in the power and ground core layers may be filled with an insulator. Two copper stacks can then be patterned, two power and ground layers forming a composite. Drilling holes and plating PTHs are performed to form the PCB. Alternatively, the drilled power core 1001 and the drilled ground core 1011 may form a composite of the following layers in that order: copper layers, optional nonconductive fiber laminate, power core 1001, ground core 1011, nonconductive fiber laminate, and copper layers. The two copper layers can then be patterned into signal layers and the composite drilled and metallized to form a four layer PCB.

The manner in which porous conductive power and formation are fabricated from porous materials has now been generally discussed. These means and materials may be used for any particular porous conductive material as will be discussed below. If there are any additional processing steps that are preferably employed so that the material can be formed into a power or ground core layer, then these steps will be discussed in connection with the power/ground material.

A preferred material for the metallized power source and formation is a sintered metal. Sintered metals consist of metal particles bonded together under pressure and heat. A sintered metal power plane may be formed by pressing together high melting temperature, highly conductive metal particles (e.g., copper) coated with a low melting point metal (e.g., tin) under heat and pressure. The tin-coated copper particles are sintered together to form an electrically conductive but porous sheet.

Such conductive sheets may be used to fabricate power/ground cores similar to power/ground cores 300, 320, or 350. Further, any of the above methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

Additional preferred materials for forming the porous conductive power source and formation may be referred to generally as fibrous conductive materials. These preferred additional materials include fine metal filaments (or "fibers") formed into a sheet, metallized fabrics (e.g., polyester), metallized carbon fiber fabrics, metallized glass fibers. The fabrics can also be divided into woven fabrics (fabrics having some regular structure) and irregular paper fabrics. Irregular paper fabrics are generally composed of irregularly oriented fibers.

For example, a preferred "fabric" material for forming the porous power/ground layer is a wire formed into a woven fabric sheet or an irregular paper fabric sheet. The filaments constituting the sheet are preferably formed to have a small diameter so as to form a sheet. In addition, the wire diameter is preferably large enough to carry the current desired for the application. The metal layer of the non-woven filaments can also be used as a material for porous power sources and ground layers. In addition, the woven fabric sheet or the irregular paper fabric sheet should be subjected to an over-plating process to better electrically connect the filaments at the respective intersections. This will ensure better electrical conductivity between the individual "fibres".

Conductive sheets of these wires may be used to make power/ground core layers similar to power/ground core layers 300, 320 or 350. Further, any of the aforementioned methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

Additional metallized fibrous materials suitable for use in power or ground layers in PCBs are metallized organic fibers such as Liquid Crystal Polymers (LCPs) (e.g., aramid manufactured by DuPont, VECTTAN manufactured by Hoechst-Celanese) and other polyester-like fabrics, SPECTRA (polyethylene manufactured by Allied Signal), and nylon. Aramid and other LCP fibers are preferred because of their low coefficient of thermal expansion (discussed later) and thermal stability. Polyester is also a preferred fiber because it is monofilament (in its woven state) and is not susceptible to shipping damage. These materials are commercially available as woven and random paper fabrics.

While certain organic fiber materials are commercially available as coated fabrics, metallized organic fiber materials suitable for use as a power source or a ground layer may also be produced by the following steps. First, the organic fibrous material is placed in the process chamber and held in a slightly stretched and/or flat position. Having the material stretched or flattened ensures that the metal uniformly covers the exposed surface. Metal is then deposited on the organic fiber material. This deposition can be done in several ways, including plating, sputtering, evaporation, or chemical vapor deposition. The organic fiber material can be flipped over and more metal deposited if the process requires or necessitates. For example, if sputtering is used, the metal is typically deposited on only one surface of the fabric. When a fabric can be used in this manner, more metal is typically applied to the other side of the fabric to increase the current carrying capacity of the fabric. Alternatively, the fabric may be sputtered simultaneously on both sides in a rolling fashion. After sputtering or chemical vapor deposition, more metal can be applied using conventional plating. This additional metal will enhance the current carrying capacity of the metal fiber fabric power source/formation.

Once the metallized fiber sheets are formed, these porous conductive sheets may be used to make a power/ground core layer similar to power/ground core layers 300, 320, or 350. Further, any of the above methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

Another preferred metallization material suitable for use in power sources or formations in PCBs or LCCs is metallized carbon fiber. Since carbon fibers can be used as textile fabrics and strands, the metallization of the fibers can be performed in both states. For example, the metal may be deposited on a carbon fiber fabric. Alternatively, the metal may be deposited on the carbon fiber yarns and the carbon fiber yarns woven into a cloth or fabric. The carbon fibers may have been coated with metal and have been formed into a tow. Such tows are useful for weaving relatively flat fabrics. Furthermore carbon fibres may be incorporated into irregular sheets of paper.

Once the metallized fiber sheets are formed, these porous conductive sheets may be used to make a power/ground core layer similar to power/ground core layers 300, 320, or 350. Further, any of the above methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

Another preferred embodiment as a fiber is a metallized glass fiber. Like carbon fibers, glass can be used as individual fiber yarns or as a sheet of textile fibers. The individual strands may be metallized and woven into a fabric, or a woven sheet of fibers may be metallized. No metal-coated article of these fibers is currently commercially available. To form a metallized fiber or fabric, a metallized fiber or metallized textile fabric can be formed using previous methods. In addition, glass fiber sheets are commercially available in the form of irregular papers. The sheets may be metallized using the metal deposition methods previously discussed.

Once the metallized fiber sheets are formed, these porous conductive sheets may be used to make a power/ground core layer similar to power/ground core layers 300, 320, or 350. Further, any of the above methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

It should be noted that certain fibrous materials used as power sources and formations in the present invention also have low Coefficients of Thermal Expansion (CTEs). The low coefficient of thermal expansion of the power/ground layers reduces the "overall" CTE of the PCBs or stacked chip carriers (LCCs). This is beneficial to prevent cracking of the mounted chips, especially for LCCs. In addition, the LOW CTE POWER/ground layers have other advantages as outlined in co-pending application EN9-98-010 "LOW CTE POWER AND GROUNDLPANES".

Although copper is primarily discussed as the metallization metal, one skilled in the art will recognize that the techniques used to deposit copper may also be used to deposit silver, gold, aluminum, tin, and the like. Furthermore, even if copper is used as the base metal for metallization, additional amounts of other metals may be added in certain processing steps. For example, some manufacturers will add small amounts of gold during processing to enhance the conductivity of the primary connection.

Thus, these preferred embodiments can form porous conductive materials that can be used as ground and power layers for PCBs. These materials should reduce common PCB problems such as peeling and cathode/anode filament growth caused by water and/or other solvents. Reduction of these problems should reduce PCB defects and enhance PCB reliability. This is especially true for chip carriers that must have more stringent moisture resistance.

Although the invention has been shown and described in connection with the illustrated embodiment of porous power sources and strata of PCBs. It will be recognized by those skilled in the art that the preferred embodiments are applicable to other applications requiring porous conductive planar materials and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (28)

1. A power/ground core layer for a printed circuit board, the power/ground core layer comprising: a first water-permeable, non-conductive layer of a first fiber stack; and a first metal sheet including a two-dimensional distribution of through-holes formed through the first metal sheet,

wherein the first non-conductive layer is in surface contact with the first metal sheet, the first metal sheet is permeable to water only through its through holes, the through holes in the first metal sheet do not extend into the first non-conductive layer, the through holes in the first metal sheet have a spacing therebetween, the spacing and diameter of the through holes in the first metal sheet are sufficient to allow water in the first non-conductive layer to pass through the through holes in the first metal sheet sufficiently quickly to prevent water in the first non-conductive layer from collecting at the interface between the first non-conductive layer and the first metal sheet.

2. The power/ground core layer according to claim 1, further comprising a second metal sheet containing a two-dimensional distribution of through-holes formed through the second metal sheet,

wherein the first non-conductive layer is in surface contact with the second metal sheet such that the first non-conductive layer is disposed between the first and second metal sheets, the second metal sheet is permeable to water only through its through holes, the through holes in the second metal sheet do not extend into the first non-conductive layer, the through holes in the second metal sheet have a spacing therebetween, the spacing and diameter of the through holes in the second metal sheet being sufficient to allow water in the first non-conductive layer to pass through the through holes in the second metal sheet sufficiently quickly to prevent water in the first non-conductive layer from collecting at the interface between the first non-conductive layer and the second metal sheet.

3. The power/ground core layer according to claim 1, further comprising: a second water-permeable non-conductive layer of a second fiber stack,

wherein the second non-conductive layer is in surface contact with the first metal sheet such that the first metal sheet is disposed between the first and second non-conductive layers, the spacing and diameter of the through holes in the first metal sheet being sufficient to allow water in the second non-conductive layer to pass through the through holes in the first metal sheet sufficiently quickly to prevent water in the second non-conductive layer from collecting at the interface between the second non-conductive layer and the first metal sheet.

4. The power/ground core layer according to claim 1, wherein the two-dimensional distribution of vias in the first metal sheet is arranged in parallel rows and columns.

5. The power/ground core layer according to claim 4, wherein the rows of said rows and the columns of said columns form an angle with each other, and the angle is not 90 degrees.

6. The power/ground core layer according to claim 4, wherein the through holes in the first metal sheet are evenly spaced in each row and each column.

7. The power/ground core layer according to claim 4, wherein the vias of a first one of said rows or the vias of a first one of said columns are staggered with respect to the vias of a second one of said rows or the vias of a second one of said columns, respectively.

8. The power/ground core layer of claim 1, wherein the spacing of the through holes in the first metal sheet is no greater than 0.05 inches.

9. The power/ground core layer of claim 1, wherein the diameter of the through-holes in the first metal sheet is at least 0.001 inches but less than 0.010 inches.

10. The power/ground core layer according to claim 3, wherein a clearance hole extends through the first non-conductive layer, the first metal sheet and the second non-conductive layer, and a diameter of the clearance hole exceeds a diameter of the through hole of the first metal sheet.

11. The power/ground core layer according to claim 3, wherein vias filled with insulating material extend through the first non-conductive layer, the first metal sheet and the second non-conductive layer, and wherein the diameter of the vias exceeds the diameter of the passage of the first metal sheet.

12. The power/ground core layer according to claim 1, wherein the first fiber stack comprises a material selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanide esters, polyimide, Polytrifluoroethylene (PTEE), and fluoropolymer.

13. A power/ground core layer for post production of printed circuit boards, the power/ground core layer comprising: a first water-permeable, non-conductive layer of a first fiber stack; and a first conductive layer not including a metal sheet having a via hole formed therethrough,

wherein the first non-conductive layer is in contact with a surface of the first conductive layer, the first conductive layer comprising a first conductive material having sufficient porosity to allow water in the first non-conductive layer to pass through the first conductive layer via the first conductive material sufficiently quickly to prevent water in the first non-conductive layer from collecting at an interface between the first non-conductive layer and the first conductive layer.

14. The power/ground core layer according to claim 13, further comprising a second conductive layer which does not comprise a metal sheet having a through-hole formed therethrough,

wherein the first non-conductive layer is in surface contact with the second conductive layer such that the first non-conductive layer is disposed between the first and second conductive layers, the second conductive layer comprising a second conductive material having sufficient porosity to allow water in the first non-conductive layer to pass through the second conductive layer via the second conductive material sufficiently quickly to prevent water in the first non-conductive layer from collecting at an interface between the first non-conductive layer and the second conductive layer.

15. The power/ground core layer according to claim 13, further comprising a second water-permeable, non-conductive layer of a second fiber stack,

wherein the second non-conductive layer is in contact with a surface of the first conductive layer such that the first non-conductive layer is disposed between the first and second conductive layers, the first conductive material having sufficient porosity to allow water in the second non-conductive layer to pass through the first conductive layer via the first conductive material sufficiently quickly to prevent water in the second non-conductive layer from collecting at an interface between the second non-conductive layer and the first conductive layer.

16. The power/ground core layer according to claim 13, wherein the clearance hole extends through the first non-conductive layer and the first conductive layer.

17. The power/ground core layer according to claim 13, wherein the via filled with the insulating material extends through the first non-conductive layer and the first conductive layer.

18. The power/ground core layer according to claim 14, wherein the clearance hole extends through the first conductive layer, the first non-conductive layer and the second conductive layer.

19. The power/ground core layer according to claim 14, wherein the via filled with the insulating material extends through the first conductive layer, the first non-conductive layer and the second conductive layer.

20. The power/ground core layer according to claim 15, wherein the clearance hole extends through the first non-conductive layer, the first conductive layer and the second non-conductive layer.

21. The power/ground core layer according to claim 15, wherein the via filled with the insulating material extends through the first non-conductive layer, the first conductive layer and the second non-conductive layer.

22. The power/ground core layer according to claim 15, wherein the first fiber stack comprises a first material selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanated ester, polyimide, polytrifluoroethylene, and fluoropolymer, and the second fiber stack comprises a second material selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanated ester, polyimide, polytrifluoroethylene, and fluoropolymer.

23. The power/ground core layer according to claim 13, wherein the first conductive material comprises a sintered metal.

24. The power/ground core layer according to claim 13, characterized in that the first electrically conductive material comprises a first fiber material woven into a fabric or formed into an irregular paper fabric.

25. The power/ground core layer of claim 24, wherein the first fiber material is selected from the group consisting essentially of metallized carbon fibers, metallized polyester, metallized liquid crystal polymer, metallized polyethylene, metallized glass fibers, and metal filaments.

26. The power/ground core layer according to claim 13, characterized in that the first fiber laminate comprises a material selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanide esters, polyimides, Polytrifluoroethylene (PTEE) and fluoropolymers.

27. The power/ground core layer according to claim 14, wherein the first conductive material comprises a first fiber material woven into a fabric or formed into an irregular paper fabric, and the second conductive material comprises a second fiber material woven into a fabric or formed into an irregular paper fabric.

28. The power/ground core layer according to claim 27, wherein the first fiber material is selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanide ester, polyimide, polytrifluoroethylene, and fluoropolymer, and wherein the first fiber material is selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanide ester, polyimide, polytrifluoroethylene, and fluoropolymer.