HK1028464A - Low cte power and ground planes - Google Patents

Description

Low CTE power source and formation

This application is related to a co-pending patent application entitled "POROUS POWER AND GROUND PLANES FOR RREQUED PCB DELAMINATION AND BETTER RELIABITY", filed by Japp et al, 26/4 1999, AND having a serial number of 09/300762, which is incorporated herein by reference.

The present invention relates generally to the field of computer manufacturing, and more particularly to reducing the coefficient of thermal expansion of circuit boards used in computers.

Computers and similar electronic devices are widely available in people's daily lives. Many commercial, banking, and government agencies rely on computers to engage in their daily activities. Most of the whole society needs computers to perform their economic, social and communication activities reliably and stably. Computers are today required to run longer and to be down time shorter than ever before.

Because computers are so needed, computer designers have placed more emphasis on their reliability. Many systems today do not allow for significant downtime to replace failed components that make up a computer system. If each component is designed to have a longer life and be more reliable, then each computer that consists of only those components will have a longer life and be more reliable.

The reproduction of component reliability is also applicable to Printed Circuit Boards (PCBs). Most components in computer systems are designed by placing semiconductor packages containing semiconductor chips on a PCB or by placing chips directly on stacked chip carriers (LCCs) and connecting the LCCs to the PCB. PCBs are referred to as "printed" because the circuit traces or copper traces are laid out on the circuit board using techniques that were originally similar to the newsprint printing process. These circuit lines connect together the semiconductor packages or chips. PCBs may simply be formed as insulators with traces printed on one or both faces thereof and one or more packages secured to one or both faces thereof. PCBs, however, have generally become more complex, generally consisting of conductive metal power and ground layers and several signal layers containing circuit lines sandwiched between several insulating layers with metal lines and pads on the top and bottom surfaces of the layers. The upper and lower conductors are connected to each other and to the internal circuit layer by Plated Through Holes (PTHs).

PCBs manufactured in this manner have become standard electronic products. Advances in manufacturing methods have made PCBs relatively inexpensive. But their simplicity makes them more reliable. However, problems associated with PCBs still exist. One of the reasons for some of these problems is the Coefficient of Thermal Expansion (CTE) of the entire PCB and the layers.

Many PCBs, and particularly LCCs, are typically constructed of organic materials and require a low CTE that better matches the CTE of the silicon chip. In an attempt to reduce the CTE of the PCB, various low CTE dielectric materials may be used. However, the effectiveness of using these low CTE dielectrics is limited because the power and ground layers that make up the major portion of the PCB are still comprised of copper. Copper has a higher CTE than certain low CTE dielectric materials. The circuit board or LCC maintains a high composite CTE due to the higher CTE of copper, the higher amount of copper used, and the high tensile modulus of copper.

The high CTE power and ground layers result in a PCB with an overall CTE similar to the CTE of these metal layers. Due to the relatively high overall CTE, the PCB or LCC itself grows longer and larger in size with increasing temperature. The increase in size means that chips, packages, wires and other devices on the surface of the PCB or LCC need to expand in the same proportion or can allow for stress due to size mismatch. Sometimes, these devices or the electrical connections between them cannot withstand these stresses, especially after repeated temperature cycles.

These stresses can especially degrade LCCs. The chip is connected to the LCC by small solder bumps called controlled collapse chip connections (C4). Whereas LCCs are typically connected to PCBs by Ball Grid Arrays (BGAs). A seal and/or primer is applied under and around the chip to protect the chip.

Previous chip carriers have almost always been constructed of ceramics with low CTEs. A low CTE chip carrier does not produce as much stress on the chip because the ceramic layer does not expand as much. However, currently, laminate materials are used as chip carriers. The laminate material has a higher CTEs as described above, which results in greater stress on the chip connected to the LCC. Unfortunately, since the chip is initially composed of crystalline silicon which is susceptible to cracking, such stress will either crack the C4 connection, or the CTE mismatch of the chip/LCC will cause the assembled package to warp, placing tension on the chip, and possibly cracking the chip.

In addition, metal layers commonly used in PCB fabrication have a higher CTE that is much higher than some low CTE media. Due to differences in CTEs, the temperature increase causes the metal to lengthen at a higher rate than the media. This differential expansion can create high stresses on the dielectric that can lead to cracking of the dielectric material. Since the circuit lines are pulled apart, cracking of the dielectric can cause an open circuit. Another effect caused by the difference in CTE is the peeling caused by shear forces, and the peeling of the media from the power source/formation. Shear induced delamination exacerbates the CTE-induced cracking mechanism since the exfoliated media are essentially "suspended" and not connected to the metallization power/ground. However, the periphery of the peeling region is connected to the metallization layer, and tends to move together with the metal layer when the metallization layer becomes longer with an increase in temperature. Cracks may develop around the peripheral region as it moves away from the release medium.

Although low CTE metals such as iron-nickel, stainless steel, and molybdenum have been used to construct low CTE power layers for PCBs and LCCs, the use of these alternative metals complicates manufacturing. These complications include battery action and corrosion, multiple corrosion steps, and complex waste disposal.

Thus, without a way to limit failure and cracking caused by CTE differences between the media and power/formation layers, the higher overall CTE of PCBs and LCCs will continue to cause a number of failure and reliability problems.

Accordingly, embodiments of the present invention provide conductive materials having low Coefficients of Thermal Expansion (CTEs) that may be used for power and ground layers. Fiber materials (e.g., carbon, graphite, glass, and liquid crystal polymers, etc.) are metallized to provide a resulting conductive material with a low CTE. These fibers may be metallized in their respective states and then formed into a fabric, or these materials are formed into a fabric and then metallized, or a combination of both metallization methods may be employed. In addition, the graphite layers may be metallized on one or both sides to provide a material with low CTE and high electrical conductivity. These metallized low CTE power and ground layers can then be laminated into composites for Printed Circuit Boards (PCBs) or for PCBs as laminated chip carriers. The present invention can provide conductors for PCBs and LCCs that do not have the problems associated with particular low CTE metals.

The foregoing and other advantages and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

Preferred exemplary embodiments of the invention will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and:

FIG. 1 is a cross-sectional view of a power source or formation according to several preferred embodiments of the present invention;

FIG. 2 is a cross-sectional view of a six-layer printed circuit board and the layers that make up the six-layer printed circuit board in accordance with a preferred embodiment of the present invention;

FIG. 3 is a process flow diagram of a method of making and using a power source or formation according to a preferred embodiment of the invention;

fig. 4 is a cross-sectional view of a six-layer printed circuit board and the layers that make up the six-layer printed circuit board.

Preferred embodiments of the present invention overcome the limitations of the prior art by providing materials with low Coefficients of Thermal Expansion (CTEs) for power and ground applications. If desired, the power and ground layers may form a core layer and are preferably used for Printed Circuit Boards (PCBs), or PCBs used as stacked chip carriers (LCCs). The present invention relates generally to the art of manufacturing PCBs. A brief description of the general manufacturing techniques for PCBs is given below, followed by the preferred embodiment.

For the manufacture of printed circuit boards, the starting material is generally a sheet consisting of glass fibers and epoxy resin. This is generally referred to as "prepreg" since the fibers are impregnated with resin during initial processing. The resin acts primarily as a binder, binding the fibers to the board. Instead of fiberglass cloth, compressed paper or other suitable material may be used. Thus, the substrate is a flat rigid or slightly tough dielectric material that will be fabricated into the final printed circuit. The starting material may be laminated to both sides of the board with a thin layer of copper or other metal using a suitable adhesive. This combination is commonly referred to as a Copper Clad Laminate (CCL). These CCLs can be converted into simple double-sided boards (with double-sided copper wires) or can be circuitized and laminated with additional media to form a multilayer composite.

In most cases, small holes (typically drilled) are formed through the plates to accommodate electrical connections to the various electronic components to be mounted. The holes are typically drilled with a high speed drill and the location of the holes is shown in the drawings or depending on the design of the plate.

In order to make an electrical connection from one side of the copper stack through the aperture to the other, the plastic wall of the aperture must be made conductive. This can be accomplished by chemical processes known in the industry, such as metallization, which consist of a relatively complex series of chemical bath treatments, rinses, and activation steps to deposit a thin layer of copper on the walls of the hole.

Since the copper layer formed by the metallization process is typically too thin for forming a suitable electrical bridge between the two layers of the board, copper electroplating is used to deposit a thick copper layer in the small hole to form a suitable copper section for carrying the current. The copper plating may be followed by tin-lead or tin plating to improve solderability.

After metallization, the circuit is processed on those surfaces where a circuit pattern is desired. A circuit pattern is a circuit design that applies specification or design requirements to the metal surface of a drilled plate. Images can be formed by applying an organic photoresist blanket as a dry film. Ultraviolet (UV) light is projected onto the photoresist through a mask. The mask contains a pattern that blocks UV light. For negative tone photoresists, the areas of the photoresist not exposed to UV light will be removed in a subsequent development step. The exposed surface metal is then removed by chemical etching. Then, the remaining photoresist is stripped, leaving only the metal pattern.

Referring now to fig. 4, an example of a six-layer PCB and the layers making up the six-layer PCB is shown. In fig. 4, parts of a PCB are shown at different stages of manufacture. In this example, the six-layer PCB120 portion serves as a stacked chip carrier (LCC) connecting chip 160 and PCB/LCC 120 with a PCB (not shown). The six-layer PCB120 includes a "composite" formed by pressing together (referred to as "lamination") two signal core layers 101 and 130, one power core layer 111, and dielectric layers 150 and 152. The core layers are individually patterned and then pressed together to form the composite PCB. During such lamination, the dielectric will flow back into any gaps present between the core layer and the dielectric layer. After lamination, the composite is drilled, the epoxy applied to the exposed copper layer of the drilled hole is removed, the through hole is plated, and the process is performed. For simplicity, FIG. 4 shows the media recirculation zone when the media contains air instead. Further, Plated Through Holes (PTHs) are shown as solid metals, although generally cylindrical metal holes. Finally, the tooling holes (firing holes) that will be used to align the workpiece with the stack and layers are not shown.

The signal core layer 100 includes a dielectric layer 104 sandwiched between two copper layers 102 and 105. The signal core layer 100 is an unprocessed CCL. Copper layers 102 and 105 are signal carrying layers on which copper lines are to be formed. The copper layer 102 may also have pads to which each chip or surface mount package containing the chip will be soldered. The signal core layer 101 represents the signal core layer 100 after patterning of the signal core layer 100. The signal core layer 101 includes copper layers 102 and 105 that have been patterned with circuitry, gaps for PTHs and other gaps/tooling holes and dielectric layers 104. Copper layer 102 has two lines (not numbered) and two pads 107 and 103, while copper layer 105 has five lines. Further, the copper layer 105 has a gap region 170 through which PTH passes after the signal core layer 101 is laminated into a composite, and drilling and hole plating are performed.

The power core layer 110 in fig. 4 includes a dielectric layer 114 sandwiched between two copper layers 112 and 115. Copper layers 112 and 115 may be thicker than copper layers 102 and 104 to provide additional current carrying capability. The power core layer 110 is an unprocessed CCL. Copper layer 112 will become the power plane of the PCB and copper layer 115 will become the ground plane of the PCB (or vice versa). The power core layer 111 represents the power core layer 110 after the power core layer 110 has been patterned. The power core layer 111 includes patterned copper layers 112 and 115 and a dielectric layer 114. Copper layer 112 is patterned to have two gap regions 182 and 179, while copper layer 115 is patterned to have two gap regions 184 and 180. These interstitial regions will prevent the power and ground layers from contacting the PTHs that are drilled at these locations after the power core layer 111 is laminated into a composite and the holes are drilled and plated.

The completed PCB section is illustrated as a six-layer PCB section 120. Such PCBs are commonly referred to as "six-layer" boards because of the six conductive layers. PCB portion 120 is being used as an LCC to connect chip 160 and metal layer 135 underneath the PCB (not shown). The attachment (not shown) between layer 135 and PCB120 is typically accomplished by a grid array (BGA) or similar connection. The six-layer PCB section 120 is shown after the signal core layers 101 and 130, the power core layer 111, and the dielectric layers 150 and 152 have been laminated to form a composite. The composite has been drilled and the coated epoxy removed from the holes. The pinholes have been plated. In addition, components are mounted on the completed LCC. For example, the die 160 has been bonded to the bond pads 103 of the copper layer 102 of the signal core layer 101 by controlled collapse die attach (C4) balls 107. An encapsulant or underfill 162 protects the chip 160. Signal core layer 130 is a signal core layer that is patterned similarly to signal core layer 101. The signal core layer 130 includes copper layers 132 and 135 and a dielectric layer 134. Copper layers 132 and 135 have formed a patterning line. A dielectric layer 150 has been applied between the power layer (copper layer) 112 of the power core layer 111 and the copper layer 105 of the signal core layer 101, while a dielectric layer 152 has been applied between the ground layer (copper layer) 115 of the power core layer 111 and the copper layer 132 of the signal core layer 130. Each dielectric layer 150, 152 may be comprised of more than one dielectric layer.

Several PTHs are shown in PCB 120. PTH 109 connects power layer 112 with C4 ball 107, lines on patterned copper layer 105, and lines on patterned copper layer 135. The gap region 180 may prevent the PTH 109 from shorting to ground. Note that after lamination, the gap region 180 will be filled with a reflow medium, but for simplicity, it is not shown in fig. 4. PTH 108 connects the lines on copper layers 102, 105, 132 and 135, and the signal line on copper layer 102 is also connected to C4 ball 107. Interstitial regions 184 and 182 may prevent PTH 108 from contacting formation 115 or power plane 112, respectively. PTH 106 connects ground layer 115 with lines or pads on copper layers 135, 132 and 102.

The overall Coefficient of Thermal Expansion (CTE) of the PCB120 remains high even with the use of low CTE media in the layers 104, 150, 114, 152 and 134. A high percentage of copper is maintained that will increase the overall CTE. This higher overall CTE can cause problems with both PCBs and PCBs used as LCCs. In the former case, PCBs experience shear-induced peeling or cracking of the dielectric material as the temperature increases, and the high CTE causes the PCB to expand. Since the semiconductor chip provided on the PCB is located in the package, the package and the connection pins or leads absorb the stress caused by the increase in the size of the PCB. The semiconductor chip itself is generally not affected by the increase in the size of the PCB. However, for PCBs used as LCCs, the semiconductor chips are provided directly on the PCB without packaging and pins or leads. The chip itself is subjected to the increased stresses generated in the PCB area as the temperature increases.

This can be seen in fig. 4, where the chip 160 is directly connected to the metal layer 102 of the PCB 120. If the PCB expands with increasing temperature, the higher CTE induced expansion causes the C4 ball 107 to move with the PCB. The C4 balls 107 are directly connected to the chip, which necessarily absorbs the strain due to the increased spacing between the balls 107. Unfortunately, semiconductor chips are predominantly crystalline silicon. The chip itself is subject to cracking because its structure and balls are also far from the chip.

The present invention overcomes the limitations of the prior art by providing low CTEs conductive material for power and ground in Printed Circuits (PCBs) and PCBs as stacked chip carriers (LCCs). By providing low CTE materials for the power and ground layers of PCBs, the overall CTE of the PCB is reduced, which in turn may reduce the chances of chip failure, dielectric cracking, and shear induced delamination. In addition, the problems associated with the use of special low CTE metals (e.g., battery action and corrosion, multiple corrosion steps, and complex waste disposal) can be completely eliminated or significantly reduced.

Before discussing the preferred embodiments, it is helpful to briefly discuss the terminology. As described in the summary section, the term "prepreg" generally includes glass fibers and epoxy resins. Because the fibers are impregnated with resin during processing, they are often referred to as "prepregs". The sheet of fibrous material containing resin is generally referred to as a "fibrous resin composite", and the sheet of fibrous material may be referred to as a "fibrous composite". Unfortunately, when one or more signal layers are laminated with one or more power/ground layers, or when power/ground layers are laminated between prepregs, it is referred to as a "composite". To avoid confusion of such composite structures with fiber composites or fiber resin composites, the fiber composites and fiber resin composites will be referred to as "fiber laminates". The term 'fiber laminate' is intended to include all types of prepregs, fiber composites, fiber resin composites, media, insulators and other materials used in PCB manufacture. In addition, embodiments of the present invention may use conductive fiber laminates (e.g., prepregs impregnated with copper). It should also be noted that although the term "fiber laminate" is used herein, the term is intended to refer to all types of thermoset resins and thermoplastic polymers currently used to construct PCBs, including, but not limited to, epoxy, bismaleimide triazine epoxy, cyanide esters, polyimides, Polytrifluoroethylene (PTEE), and other fluoropolymers, and the like, whether or not they contain any fibers or fillers.

Preferred embodiments of the present invention include various conductive low CTE materials that can be used for power and ground layers. For example, a core layer of a solid low CTE material (preferably a carbon-based material such as graphite) metallized on one or both sides thereof may form the basis of the power/ground layer. In addition, metallized low CTE fibers (e.g., glass, carbon, and liquid crystal polymer fibers) can form a fabric that can serve as a foundation for a power/ground layer, with conductive materials having CTE's typically between-5 and 5 PPM/deg.C being preferred. Materials with CTEs less than 5 PPM/deg.C are preferred. The power/ground core layers formed using these preferred materials should have a composite CTE of 8-12 PPM/deg.C, depending on the fiber lay-up used. The use of these core layers in PCB/LCC can result in PCB/LCC with a composite CTE of 8-12 PPM/deg.C. The CTE is significantly reduced compared to a PCB constructed from ordinary layers, i.e., Copper Clad Laminate (CCL). Even with low CTE fiber stacks, the CTE of a typical PCB is typically near or above 17 PPM/c due to the higher CTE of copper, and the relatively high percentage (volume or weight) of copper in the PCB. Therefore, even if PCBs are fabricated with low CTE fiber laminate layers limited to those fiber laminate layers having a CTE near 17 PPM/deg.C, the CTE of the PCB is typically higher than 17 PPM/deg.C. Although embodiments of the present invention may use conductive materials with CTE higher than 5 PPM/deg.c, the composite CTE of the resulting PCB is still too high for some applications. The conductive material of the present invention is most beneficial for semiconductor chips mounted directly on LCCs. The small difference between the CTE of the chip and the composite CTE of PCBs/LCCs fabricated in accordance with the present invention inhibits cracking of the chip due to CTE mismatch. Utilizing conductive materials with high CTEs will result in a higher composite CTE for the PCB/LCC, which will increase the likelihood of chip defects and cracking. Having introduced preferred methods of making and using low CTE power/ground layers, certain preferred materials will be discussed.

Some preferred materials for forming the low CTE power/ground layers of the present invention are brittle during drilling or transport in PCB or LCC fabrication. For example, fibrous materials may be more susceptible to damage during drilling than metal foils. Furthermore, since photolithography and etching techniques may not pattern some of these low CTE power and ground layers, some variation from the normal PCB or LCC fabrication steps is preferred. Before introducing preferred materials for the low CTE power source and ground layer, a discussion of the general steps involved in utilizing and fabricating a low CTE power source/ground layer constructed of a low CTE material is provided.

Referring now to fig. 1, three preferred configurations of low CTE power and formation are shown. Each structure is manufactured and the processing steps utilized with the low CTE power supply or formation in the PCB/LCC are slightly different. The most preferred structure for a low CTE power source and ground layer is shown as power/ground core layer 300. The power/ground core layer 300 includes a low CTE layer 304 sandwiched between two fiber laminates 302, 305. Two clearance holes 310 are shown which have been drilled in the power/ground core layer 300 to provide clearance for the PTHs after the power/ground core layer 300 is laminated with another power/ground core layer and one or more signal core layers. The lamination forms a composite that is subsequently drilled and metallized to form a PCB or LCC. By layering the low CTE layer 304 between the two fiber stacks 302 and 305, the fiber stack provides protection for the low CTE layer during drilling and shipping. The fiber stacks 302, 305 may be either non-conductive or conductive. In the case of the latter embodiment, the power/ground core layer 300 will be a conductive composite. The power/ground core layer 300 is then stacked between two non-conductive fiber stacks to form a larger "core" or the power/ground core layer 300 is stacked with other signal layers, power/ground core layers, and non-conductive fiber stacks into a PCB composite. It should be noted that the layer 304 may actually have one or more metal layers on both sides of the adjoining fiber lay-up 302, 305. These layers are not shown in fig. 1.

Figure 1 also shows second and third less preferred configurations of low CTE power and formation that are more susceptible to drilling and transport damage. The power/ground core layer 320 includes a fiber stack 324 sandwiched between two low CTE layers 322, 325. Additionally, the fiber stack 324 may or may not be conductive. The power/ground core layer 320 has been drilled with clearance holes 330. The power/ground core layer 350 includes a low CTE layer 352. Similarly, the power/ground core layer 350 has been drilled with clearance holes 360. Since the low CTE layer is susceptible to drilling and shipping damage, these are less preferred embodiments of the power/ground core layer. However, minimal or no damage to the low CTE material from which the power/ground is made may also be possible if care is taken during transportation and drilling. It is preferred to seal low CTE materials in the fiber stack that are susceptible to shipping or drilling damage to reduce the likelihood of damage.

Each of these core layers may be treated in a slightly different manner. Generally, the power/ground core layer 300 will be laminated after an optional adhesion enhancement process (using a chemical such as silane) is performed on the low CTE layer 304. Clearance holes 310 are then typically drilled in the power/ground core layer. This stage replaces patterning and etching with photoresist and drilling is used because fiber stacks and most low CTE fiber materials typically cannot be etched. In addition, the clearance hole 310 may be filled with an insulator/media in this step. The drilled power/ground core layer 300 may then be laminated into a composite with another power/ground core layer and one or several signal core layers. The composite is then drilled and metallized (as PTHs) to form a PCB or LCC. Alternatively, the power/ground core layer 350 may be drilled and treated with an adhesion enhancing process and then laminated with two fiber laminates to form the power/ground core layer 300. Although the power/ground core 350 may be mechanically drilled to form clearance holes and tooling holes, laser or other less damaging drilling methods are preferred for power/ground core materials that are susceptible to drilling damage.

In general, the power/ground core layer 320 may be formed by treating the low CTE layers 322, 325 with an adhesion enhancing process (optional). The fiber stack (conductive or non-conductive) is then stacked between two low CTE layers. Drilling is then typically performed to form clearance (or tooling) holes 330. For power/formation materials that are susceptible to damage from drilling, laser or other less-damaging drilling techniques are preferably employed. An additional advantage of laser drilling in this embodiment is that the two conductive low CTE layers can be patterned with different via patterns. The gap or machined hole is then filled with an insulating/dielectric material. The power/ground core layer 320 is then laminated with another power/ground core layer and one or several signal layers into a composite.

In general, holes may be drilled in the power/ground core layer 350 and treated with an optional adhesion enhancing material (e.g., silane or copper oxide treatment) and then laminated with two fiber laminates (conductive or non-conductive) to form the core layer 300. Alternatively, holes may be drilled in the power/ground core layer 350 and treated with an adhesive layer reinforcement step, then laminated with another power/ground core layer, several fiber laminates, and one or more signal core layers to form a composite. For example, to form a six-layer composite, the layers from the "upper" layer to the "bottom" layer of the composite are as follows: a signal core layer (e.g., signal core layer 101 of fig. 4), one or more fiber stacks, a power/ground core layer 352, one or more fiber stacks, and a second signal core layer (e.g., signal core layer 130 of fig. 4). The composite is then drilled and metallized to form the PCB/LCC.

As noted above, it is preferred that the conductive material be used to form a low CTE power source or ground layer of the power/ground core layer that is susceptible to damage from drilling or transport, with the low CTE conductive material sandwiched or sealed between two fiber lay-ups. The power or ground core layer formed in this manner will support and protect the low CTE layer conductive material during the drilling step. This protection reduces the amount of fibrous material that may be broken by the drilling process. Power core layers like power core layer 320 (similar to power core layer 110 of fig. 4) or power core layer 350 may also be fabricated, but drilling and/or shipping can cause the low CTE material to crack and craze to some extent. In addition, loose fibers or carbon materials can contaminate certain processing steps. By sealing the fibers or carbon material and filling the drilled holes with insulation/media, the fiber material is less likely to contaminate subsequent processing steps.

Referring to fig. 2, there are shown several cross-sections of power and ground core layers and a six layer PCB/LCC made up of these core layers. Fig. 2 is an example showing a power core 1000, a drilled power core 1001, a ground core 1010, a drilled ground core 1011, and a six-layer PCB/LCC 1020 for use as an LCC. The power core layer 1000 is formed by performing an adhesion enhancement process on a low CTE power layer 1087, which is then laminated between the two fiber stacks 1002 and 1005. In this case, the low CTE power layer 1087 is a graphite layer 1004 having metal layers 1097 and 1098 formed on its surface. Then, the power core layer 1000 is drilled to form clearance holes 1082 and 1079. After the photoresist mask is applied, a "standard" CCL power core layer is etched to form the imaged power core layer (i.e., power core layer 111 of fig. 4). Because corrosion is not possible with certain low CTE conductive materials or fiber laminates used for power/ground applications, it is preferable to use drilling to form the clearance holes. The power core layers 1000 and 1001 in this example are primarily low CTE conductive layers sandwiched between two non-conductive fiber stacks.

The ground core layer 1010 is formed by performing an adhesion enhancement process on low CTE ground layers 1012, 1015 (which in this case are metallized fiber materials) and then laminating the layers on both sides of a conductive fiber laminate. Then, core layer 1010 is drilled to form clearance holes 1084 and 1080. The ground core layer 1010 in this example is essentially one conductive layer with three conductive layers (one conductive fiber stack sandwiched between two layers of low CTE conductive material). Although not shown in fig. 2, a dielectric or other insulator may be added to the power core 1001 and ground core 1011 to fill interstitial holes in these cores.

With respect to the conductive fiber layer 1014, a preferred method of forming this layer is to incorporate 40% copper powder by volume into the fiber or fiber/resin layer. During lamination, the copper should be uniformly distributed in the fibre layers. Other conductive fillers and other types of layer materials may also be used, but the fillers and layer materials have the advantage of being less expensive and of being materials commonly used in PCB manufacture.

After core drilling (with the addition of insulation if necessary), the power core 1001 and ground core 1011 are pressed together with the patterned signal cores 101, 130 and fiber stacks 1096, 1095, and 1099 to form a composite. The composite was drilled and metallized to form PTHs. After the components are secured to the PCB/LCC, an exemplary six-layer PCB/LCC portion 1020 results. Fiber stacks 1095, 1096, and 1099 are layers of non-conductive media for isolating the signal, power, and ground cores. In addition, these layers adhere the power, ground and signal core layers together. The power core layer 1001 has a fiber laminate 1005 to be used for adhesion of the power core layer 1001 and the ground core layer 1011. Similarly, the fiber stack 1002 of the power core layer 1001 may be adhered to the signal core layer 101. However, in general, the fiber stack 1005 (and 1002) will be sufficiently cured, meaning that another fiber stack has to be used to bond the power, ground and signal core layers together. Some fibers, once cured, will no longer reflow enough to adequately bond with another layer. The layers may be partially cured, allowing some of them to reflow as the core layers are laminated. In addition, some fiber stacks will reflow multiple times and provide adequate adhesion between the two core layers. In these cases, the fiber layers 1095 and 1096 are not necessarily used for adhesion. Although these fiber stacks are not required for adhesion purposes in these cases, there may be other reasons for utilizing additional fiber stacks (e.g., layer 1095). For example, additional fiber plies may provide such insulation if better electrical insulation is desired. Note that the fiber stack 1099 is generally necessary to provide electrical insulation (in addition to adhesion) and to provide resin filling of interstitial holes 1082 and 1079 between the patterned signal layer 132 and the metallized fiber layer 1015.

PTH1008, similar to PTH 108 of fig. 4, connects the lines of signal layers 102 and 105 of signal core layer 101 with the lines of signal layers 132 and 135 of signal core layer 130. The gap regions 1082 and 1084 prevent the ground and power layers from contacting the TPH. Although the interstitial regions 1082 and 1084 are filled with "air," in practice, these regions are typically filled with a medium: these regions are filled with dielectric either after drilling the power or ground core layers or during lamination with the dielectric/insulator of the fiber stack.

PTH 1009 is similar to PTH 109 of fig. 4, and connects bond pad 103 (and C4 ball 107) on layer 135 of signal core layer 130 and line and power plane 1001. In this example, the power supply layer 1001 includes a conductive layer 1087 actually having three conductive layers (a graphite layer 1004, two metal layers 1097 and 1098). In this example, all three layers of the conductive layer 1087 are in contact with PTH 1099. The gap region 1080 prevents the PTH 1009 from connecting to the ground core layer 1011. Similarly, PTH1006 is similar to PTH 106 of fig. 4, connecting lines on layer 102 of signal core layer 101 and lines on layers 135, 132 of signal core layer 130 with ground core layer 1011. The ground layer 1011 includes three conductive layers (two low CTE layers 1012 and 1015, and one conductive fiber stack 1014) that are all connected to the PTH 1006. The clearance area 1079 prevents the PTH1006 from connecting to the power plane 1087.

In the example of fig. 2, it is shown that most of the fiber stacks on each core layer are thin. For example, fiber stacks 1002 and 1005 are thin. This is merely for the purpose of indicating that more plies, thinner or thicker fiber plies may be added if desired, as will be appreciated by those skilled in the art. The main difference between the six-layer PCB/LCC 1020 of fig. 2 compared to the six-layer PCB/LCC 120 of fig. 4 is that PCB/LCC 1020 has separate power and ground core layers, and these power/ground core layers are formed differently from the common CCL core layer. PCB/LCC 1020 also has low CTE power and ground layers that comprise most of the LCC. The signal layers 102, 105, 132 and 135, although having some metal, contain primarily fiber stacks. Thus, the overall CTE of the signal core layers 101 and 130 approaches the CTE of the fiber stacks 104 and 134. If a low CTE media is used in these fiber stacks, the CTE will be very low. The CTE of the high PCB in this case is essentially due to the metal layers of the power/ground core layer, typically the CCL. In this case, the copper in the CCL determines the CTE of the power/ground core layers due to the amount of copper in the power and ground layers. Such high CTE power/ground core layers can raise the overall CTE of the PCB, leading to possible shear induced delamination, dielectric or die cracking, strain on the die attached to the PCB (used as an LCC), and other undesirable effects.

However, the formation 1011 in FIG. 2 comprises a metallized low CTE fiber material. In addition, the power plane 1087 includes metallized graphite sheets. These layers all contain a significant amount of low CTE material that lowers the overall CTE of the core layer. Therefore, both core layers have lower overall CTE compared to the equivalent CCL core, and these lower overall CTEs reduce the overall CTE of the PCB/LCC. Furthermore, such low CTE core layers can be obtained without the use of alternative metals (e.g., iron-nickel alloys, stainless steel, and molybdenum) that can cause manufacturing complications including cell action and corrosion, multi-step corrosion, and complex waste disposal.

Fig. 3 illustrates a preferred method of forming a power or ground core layer (e.g., power core layer 1000) comprising a low CTE conductive material in accordance with the present invention. The method 400 of fig. 3 is preferably used to form power and ground core layers to combine the power and ground core layers into a composite PCB or LCC. This method can also be used in preferred embodiments where a low CTE conductive material is sandwiched between two fiber laminates as the power plane 1000. This embodiment may better protect the internal low CTE conductive material. In addition, the fiber lay-up may help to "seal" the fiber material covered with metal and other loose materials, which helps to hold the inner fiber material to the laminate. This is particularly beneficial in the case of carbon materials that may contaminate various parts of the PCB/LCC and the manufacturing process. The method 400 begins by forming an optional thin metal coating on the low CTE material used (step 410). The metallized fibrous materials of the present invention are generally metals sufficient to carry the required current; more metal may be formed on the fiber at step 410 if additional current carrying capacity is required.

In addition, if the preferred low CTE materials of the present invention are not metallized, these materials may also be metallized at this step. For example, if unmetallized carbon fiber tow is used as the low CTE material, the tow may be metallized and formed into a woven fabric at step 410. Additional metal may then be attached to the fabric at step 410, if desired. In the particular example of the power core layer 1000, both sides of the graphite layer 1004 are metal coated at step 410 to form the power layer 1087. Briefly, step 410 may be used to metalize the non-metal coated material and add additional metal to the metal coated material. Following the method 400, preferred material types for the power source and formation will be discussed in more detail.

The low CTE material is then optionally treated with an adhesion enhancing chemical process or copper oxide treatment (step 420). Conductors are then sandwiched between the two fiber lay-ups to form a sealed low CTE power or ground core layer (step 430). Generally, standard lamination processes are used to laminate low CTE ground/power materials. Alternatively, the fibrous low CTE material may be impregnated with resin using standard impregnation processes (step 433). This standard impregnation process substantially encapsulates the fibrous material. The resin impregnated cloth is then laminated against a release sheet (release sheet) or roughened copper foil. If a roughened copper foil is used, it may be etched away (step 437) or stripped by drilling (step 440). The release tab is typically removed prior to drilling (step 435).

Since the fiber stack is generally not etched to form the necessary electrical interstitial holes (and other openings), these openings are formed in the power/ground core layer (step 440). Generally, these openings can be formed in and through the laminate and low CTE layer by drilling a clearance hole pattern or machining holes. Drilling may be performed by mechanical drilling or by laser or other similar hole forming equipment. If the roughened copper foil has been laminated to the low CTE material (step 435) and has not been removed (step 437), it can now be removed by etching (step 445). At this point, the opening may be refilled with pure resin, the resin containing a non-conductive filler or other suitable insulator/medium (step 450). The power/ground core layer is introduced into the composite, preferably by being re-laminated or pressed onto a composite panel structure (step 460). If the holes are not filled at step 450, additional resin flows from the fiber lay-up to and fills the drilled power layer holes during the lay-up cycle. Holes for the PTHs may then be re-drilled and metallized (step 470). After step 470, a PCB/LCC similar to PCB/LCC 1020 will be formed.

Although method 400 is the preferred method of fabricating PCB/LCC with low CTE power/ground layers, the steps of method 400 may vary slightly depending on the structure of the power/ground core layer used. For example, two layers of low CTE conductive material may be laminated to the fiber laminate as previously shown, for example, in power and ground core layer 320 of fig. 1. In this example, the processing steps are very similar to those shown in method 400. For example, steps 410 and 420 of method 400 may be performed, respectively, to add additional metal to the conductive material and enhance adhesion. The fiber stack (conductive or non-conductive) is then stacked between two low CTE layers. Additionally, a liquid resin infusion step (step 433) may be performed prior to laminating the fiber lay-up between the two low CTE conductive materials. Drilling is then typically performed to form clearance holes or tooling holes (step 440). For power/formation materials that are susceptible to borehole damage, it may be preferable to use a laser or other less-susceptible drilling method. An additional advantage of laser drilling in this case is that the two conductive low CTE layers can be patterned with different via patterns. The gap or machined hole may be filled with an insulating material at this stage (step 450). The power/ground core layer 320 is then laminated with another power/ground core layer, one or more signal layers, and a non-conductive fiber into a composite (step 460). The composite is then drilled and metallized to form the PCB/LCC (step 470).

In addition, a power/ground core layer similar to power/ground core layer 350 of fig. 1 may also be used to form the power or ground layer. In this example, the processing steps used to form the power source and formation are somewhat different than in method 400. For example, drilling (step 440) may be performed before or after step 410 (if performed). The low CTE conductive layer may then be treated with an optional adhesion enhancing material (step 420) and stacked with a two fiber stack (conductive or non-conductive) to form the core layer 300 of fig. 1. In this example, step 450 is generally unnecessary because the lamination process can fill each hole with a stack of fibers. Alternatively, a low CTE conductive layer similar to the power/ground core layer 350 may be drilled and treated with an adhesion enhancing step (step 420) and then laminated to a composite with another power/ground core layer, several fiber stacks, and one or more signal core layers (step 460). The composite is then drilled and metallized to form the PCB/LCC (step 470).

Finally, the method 400 may be applied to PCBs in other configurations than the six-layer PCB shown in FIG. 2. By applying the process of method 400 to a particular number of layers, a greater or lesser number of layers may be formed. For example, (referring again to fig. 2), if a four layer PCB is desired, the power core layer 1000 may be laminated on the outer surface of the copper laminated layer 1002. The power core layer 1001 is then drilled. Similarly, the core layer 1010 may be laminated on the outer surface of the layer 1015 with the fiber laminate and the copper layer. The ground core 1011 is then drilled. The openings formed in the power and ground core layers may be filled with an insulator. Two copper stacks can then be patterned, two power and ground layers forming a composite. Drilling holes and plating PTHs are performed to form the PCB. Alternatively, the drilled power core 1001 and the drilled ground core 1011 may form a composite of the following layers in that order: copper layers, optional nonconductive fiber laminate, power core 1001, ground core 1011, nonconductive fiber laminate, and copper layers. The two copper layers can then be patterned into signal layers and the composite drilled and metallized to form a four layer PCB.

The manner in which low CTE conductive power and ground layers are fabricated from low CTE materials has now been generally discussed. These means and materials may be used for any particular low CTE conductive material discussed below. If there are any additional processing steps that are preferably employed so that the material can be formed into a power or ground core layer, then these steps will be discussed in connection with the power/ground material.

The most preferred embodiment of a power/ground layer comprising a low CTE material is a graphite or carbon sheet with copper on one or both sides. Graphite is a naturally occurring conductive material composed of carbon. The term "graphite" refers to a characteristic special structure of carbon atoms. The graphite may be naturally occurring or manufactured artificially. Although graphite has a crystalline structure to some extent, the electrical conductivity of graphite is mainly anisotropic. Very pure crystalline graphite has excellent electrical and thermal conductivity and negative CTE. Bulk graphite generally has very low electrical and thermal conductivity and has a low positive to negative CTE.

Those skilled in the art will recognize that graphite or carbon sheets suitable as the base material for the power/ground layers may be fabricated in a variety of ways. For example, the bulk graphite may be sintered or compressed into thin graphite sheets. Graphite flakes can be made by chemical vapor deposition, which can form highly ordered pyrolytic graphite. However, the latter tablet is fragile and very expensive. In addition, the graphite sheet can be formed by winding carbon fibers onto a mandrel to form a carbon fiber spool, then removing the mandrel, flattening the spool, and then graphitizing the spool under high heat. In some cases, this results in a sheet of carbon fibers that have lost all of their orientation and shape, which is substantially well crystallized, becoming purer graphite. These methods of forming graphite/carbon sheets are well known in the art.

A metal is deposited on a graphite or carbon sheet and the combined material has a low CTE. The metal may be deposited on the graphite using a variety of methods known to those skilled in the art. For example, sputtering, evaporation or chemical vapor deposition may be used to deposit the metal on the graphite. These metal coating methods will be described in more detail below. The metal may be applied to one or both faces of the graphite sheet, although it is preferred that the sheet be metallized on both faces, since metallization can provide more metal and increase current carrying capacity on both faces.

PCBs and PCBs for use as LCCs can be formed using the metallized graphite or carbon material in the manner shown and described above. For example, a power/ground core layer similar to power/ground core layer 300, 320, or 350 may be fabricated from the conductive sheet. The resulting reduction in the overall CTE of PCBs/LCCs reduces shear induced delamination and cracking of the chip to C4 bond.

The additional preferred materials for forming the low CTE conductive power source and formation may be referred to generally as fiber conductive materials. These preferred additional materials include metallized fabrics (e.g., liquid crystal polymers), metallized carbon fiber fabrics, metallized glass fibers. The fabrics can also be divided into woven fabrics (fabrics having some regular structure) and irregular paper fabrics. Irregular paper fabrics are generally composed of irregularly oriented fibers. The irregular paper web does not have the same fiber structure.

For example, a preferred material for forming a low CTE power/ground layer is a metallized low CTE organic fiber, such as Liquid Crystal Polymers (LCPs). There are several companies that make LCPs, and the trademarks of some of these fibers are well known. Aramid is an LCP made by DuPont, sometimes referred to as KEVLAR. VECTRAN is an LCP manufactured by Heochst-Celanese. These fibers have CTEs of about-5 to 5 parts per million per degree Celsius (PPM ℃). In addition, these fibers are thermally stable. Other types of organic fibers having similar CTEs as LCPs that are suitable for use in the present invention include SPECTRA (which is polyethylene manufactured by allied signal). Woven and irregular paper fabrics of these materials are commercially available. In addition, metallized products of certain LCPs are already commercially available. For example, aragon is a trademark of DuPont's metallized aramid fiber.

While certain organic fiber materials are commercially available as coated fabrics, metallized organic fiber materials suitable for use as a power source or a ground layer may also be produced by the following steps. First, the organic fibrous material is placed in the process chamber and held in a slightly stretched and/or flat position. Having the material stretched or flattened ensures that the metal uniformly covers the exposed surface. Metal is then deposited on the organic fiber material. This deposition can be done in several ways, including plating, sputtering, evaporation, or chemical vapor deposition. The organic fiber material can be flipped over and more metal deposited if the process requires or necessitates. For example, if sputtering is used, the metal is typically deposited on only one surface of the fabric. When a fabric can be used in this manner, more metal is typically applied to the other side of the fabric to increase the current carrying capacity of the fabric. Alternatively, the fabric may be sputtered simultaneously on both sides in a rolling fashion. After sputtering or chemical vapor deposition, more metal can be applied using conventional plating. This additional metal will enhance the current carrying capacity of the metal fiber fabric power source/formation. These processes can also be used to coat the carbon or graphite sheets discussed above with metal. In addition, these processes can also be used to coat other preferred low CTE materials discussed above with metal. In addition, these techniques can also be used to coat the carbon or graphite sheets discussed above with metal.

Once the metallized fiber sheets are formed, these low CTE conductive sheets can be used to fabricate power/ground core layers similar to power/ground core layers 300, 320, or 350. Further, any of the above methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

Another most preferred metallized fibrous material suitable for use as a power source or formation for PCBs or LCCs is metallized carbon or graphite fibers. Since carbon or graphite fibers can be used as both woven yarns and as single yarns or tows, the fibers can be metallized in both states. For example, the metal may be deposited on a carbon or graphite fiber fabric. Alternatively, it may be deposited on carbon or graphite fibers and woven into a cloth or fabric. Metallized products of carbon and graphite fibers and products that have been formed into tows or yarns are already commercially available. The tow or yarn can be used to weave relatively flat woven fabrics. In addition, irregular sheets of carbon fiber are commercially available. Any carbon fiber having a low CTE (preferably less than 2 PPM/c) can be used in embodiments of the present invention.

By way of example, 1K (1000 fibers of 6 microns per yarn or tow) graphite/carbon fiber may be plated with 50-60 wt% copper. The plated tow can be used to weave a flat woven fabric of 30 x 30 threads per inch. As described in connection with fig. 3, one method of manufacturing the power/ground core layer is to treat the fabric with an adhesion enhancing step such as a silane coupling agent or copper oxide conversion process. The treated fabric was impregnated with resin according to standard impregnation procedures. The resin impregnated cloth is then laminated to a release sheet or roughened copper foil. If a roughened copper foil is used, it is typically etched away at this point. The release sheet is removed and the portion is drilled with a pattern of clearance holes. In this example, the patterned power plane is then laminated to a composite and adhered thereto with a fiber laminate. The composite is then drilled and plated in the usual manner. Where the carbon/graphite fabric is drilled through, a PTH connection is formed. The fabric is a dense textile fabric and provides a substantially continuous layer to form a connection at any drilled hole location.

The process results in a power layer having a metallized carbon fiber volume of 60% and a CTE of about 9 PPM/DEG C. The CTE is already much lower than that of a solid copper layer having a CTE of about 17 PPM/DEG C. With carbon fibers having a CTE of about 2 PPM/deg.C, 9 PPM/deg.C can be produced. Even lower CTEs can be achieved with lower CTE graphite fibers. The carbon and graphite fibers have CTEs in the range of about-1.4 PPM/deg.C to about 2.0 PPM/deg.C. Such a power/ground layer should have a current carrying capacity of about 1 ounce of pure copper, but the thickness of the structure is about 3-4 mils, instead of 1.4 mils of 1 ounce of pure copper.

In addition, carbon fiber and graphite are less reactive than most standard PCB chemistry. Corrosion and other processes do not readily affect the carbon fibers and graphite.

Once the metallized fiber sheets are formed, these low CTE conductive sheets can be used to make power/ground core layers similar to power/ground core layers 300, 320, or 350. Further, any of the above methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

Yet another preferred embodiment of a fibrous material having a low CTE is a metallized glass or quartz fiber. Similar to carbon fibers, yarns or woven sheets of glass and quartz fibers or irregular paper fibers are already commercially available. The strands may be metallized and formed into a fabric, or the fibers that have been formed into a sheet may be metallized. Additional metal may be added to each fabric to provide additional current carrying capability. Currently, metallized products of these fibers are not commercially available. To form a metallized fiber or fabric, a metallized fiber, or metallized fabric, can be formed using previous methods. In addition, glass fiber sheets in the form of irregular paper are already commercially available. The sheets may be metallized using the metal deposition methods previously discussed.

Glasses come in many different forms, many of which are formed by incorporating certain "impurities" into silica. For example, S-glass is a silicon-aluminum-magnesium compound that may or may not be wound into fibers, and E-glass is a calcium-aluminum-borosilicate (Ca-A1) that is used primarily in textile fabrics₂O₃-SiO₂) The compound, D-glass, is a glass having a low dielectric constant. Common glass fibers have CTEs of about 1-3 PPM/deg.C. For example, the CTE of E-glass is about 2.8 PPM/deg.C, while the CTE of S-glass is about 1.6-2.2 PPM/deg.C.

The CTE of a power/ground core layer formed using copper clad glass and laminated with resin (as in method 400) is about 12 PPM/c at 60% by volume of the metallized glass fibers. The CTE has been significantly reduced from that of a solid copper layer (or PCB fabricated from a solid copper layer) of about 17 PPM/deg.c.

Once the metallized fiber sheets are formed, these low CTE conductive sheets made of metallized glass fibers can be used to make power/ground core layers similar to power/ground core layers 300, 320, or 350. Further, any of the above methods of fabricating these core layers and integrating them into a PCB/LCC may be performed.

It should be noted that the fibrous materials used as the power source and formation of the present invention are permeable to water and other solvents. Permeability to water or other solvents reduces delamination of the fiber stack and cathode/anode filament growth in PCBs. Such low CTE POWER/formations are discussed in co-pending EN9-98-002 "POROUS POWER AND GROUND PLANES FOR REDUCED PCBDELAMINATION AND BETTER RELIATY".

Accordingly, embodiments of the present invention provide low CTE materials that may be used to form power/ground core layers that form the basis of PCBs or PCBs used as LCCs. These low CTE materials reduce stress on the PCB/LCC layers and the chips and chip connections mounted thereon when forming the power/ground layers. The reduction in stress is particularly beneficial for PCBs used as LCCs because the chip is directly attached to the LCC and does not tolerate significant strain prior to cracking. Embodiments of the fibrous material of the present invention have the added advantage of having permeability to water or other solvents.

Although copper is primarily discussed as the metallization metal, one skilled in the art will recognize that the techniques used to deposit copper may also be used to deposit silver, gold, aluminum, tin, and the like. Furthermore, even if copper is used as the base metal for metallization, additional amounts of other metals may be added in certain processing steps. For example, some manufacturers will add small amounts of gold during processing to enhance the conductivity of the primary connection.

Claims (34)

1. A power/ground core layer for a printed circuit board, the power/ground core layer comprising:

at least one fiber laminate; and

at least one layer of conductive material having a Coefficient of Thermal Expansion (CTE) lower than the CTE of the copper layer.

2. The power/ground core layer according to claim 1, wherein the at least one layer of conductive material is two layers of conductive material, the at least one fiber laminate layer being sandwiched between the two layers of conductive material.

3. The power/ground core layer according to claim 1, wherein the at least one fiber laminate layer is two fiber laminate layers with the at least one layer of conductive material sandwiched therebetween.

4. The power/ground core layer according to claim 1, wherein at least one of the fiber laminates is non-conductive.

5. The power/ground core layer according to claim 1, wherein at least one of the fiber laminates is electrically conductive.

6. The power/ground core layer according to claim 1, wherein the CTE of the conductive material is less than 5PPM/° c.

7. The power/ground core layer according to claim 1, wherein the conductive material comprises metallized carbon or graphite sheets.

8. The power/ground core layer according to claim 1, wherein the conductive material comprises a metallized fiber material woven into a fabric or formed into an irregular paper fabric.

9. The power/ground core layer according to claim 8, wherein the fiber material is selected from the group consisting essentially of carbon fibers, graphite fibers, liquid crystal polymer fibers, polyethylene fibers, quartz fibers, and glass fibers.

10. The power/ground core layer according to claim 1, wherein the at least one fiber laminate is selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanide esters, polyimides, Polytrifluoroethylene (PTEE), and fluoropolymers.

11. A Printed Circuit Board (PCB), the PCB comprising:

at least one signal core layer, each signal core layer comprising at least one signal layer and at least one fiber stack; and

at least one power/ground core layer, the core layer comprising:

at least one fiber laminate; and

at least one layer of conductive material having a Coefficient of Thermal Expansion (CTE) lower than the CTE of the copper layer.

12. The PCB of claim 11, wherein the at least one layer of conductive material is two layers of conductive material, wherein the at least one fiber laminate of the at least one power/ground core layer is sandwiched between the two layers of conductive material.

13. The PCB of claim 11, wherein the at least one fiber laminate of the at least one power/ground core layer is a two-layer fiber laminate with the at least one layer of conductive material sandwiched therebetween.

14. The PCB of claim 11 wherein at least one of the fiber laminates of at least one of the power/ground core layers is non-conductive.

15. The PCB of claim 11, wherein at least one of the fiber laminates of at least one of the power/ground core layers is electrically conductive.

16. The PCB of claim 11, wherein the CTE of the conductive material is less than 5PPM/° c.

17. The PCB of claim 11, wherein the conductive material comprises metallized carbon or graphite flakes.

18. The PCB of claim 11, wherein the conductive material comprises a metallized fiber material woven into a fabric or formed into an irregular paper fabric.

19. The PCB of claim 18, wherein the fibrous material is selected from the group consisting essentially of carbon fibers, graphite fibers, liquid crystal polymer fibers, polyethylene fibers, quartz fibers, and glass fibers.

20. The PCB of claim 11 wherein the at least one fiber laminate is selected from the group consisting essentially of epoxy, bismaleimide triazine epoxy, cyanide esters, polyimide, Polytrifluoroethylene (PTEE), and fluoropolymer.

21. A method of manufacturing a Printed Circuit Board (PCB), the method comprising the steps of:

a) providing at least one power/ground layer comprising at least one layer of conductive material having a CTE lower than the CTE of the copper layer;

b) forming a plurality of openings in at least one power source/formation;

c) forming a composite with at least one power source/ground layer and at least one signal layer;

d) forming a plurality of openings in the composite; and

e) a plurality of plated through holes are formed in the composite.

22. The method of claim 21, wherein the step of providing at least one power/ground layer further comprises the step of forming at least one fiber stack and at least one power/ground core layer of low CTE conductive material.

23. The method according to claim 22, wherein the at least one fiber stack of the power/ground core layer is selected from the group consisting essentially of epoxy, bis-3 maleimide triazine epoxy, cyanide esters, polyimide, Polytrifluoroethylene (PTEE), and fluoropolymer.

24. The method of claim 22, wherein the at least one layer of conductive material is two layers of conductive material, and wherein the step of forming the power/ground core layer comprises sandwiching the at least one fiber laminate between the two layers of conductive material.

25. The method of claim 24 wherein the step of sandwiching at least one fibrous laminate between two layers of conductive material comprises the steps of sealing at least one layer of conductive material using a dipping process and laminating the sealed conductive material with a release sheet or roughened copper foil.

26. The method of claim 22, wherein the at least one fiber laminate is a two-layer fiber laminate, and wherein the step of forming the source/ground core layer includes sandwiching the at least one layer of conductive material between the two fiber laminates.

27. The method of claim 22, wherein at least one of the fiber plies is non-conductive.

28. The method of claim 22, wherein at least one of the fiber stacks is electrically conductive.

29. The method of claim 21, further comprising the step of coating the conductive material with an additional metal.

30. The method of claim 21, further comprising the step of performing an adhesion enhancement process on the low CTE conductive material.

31. The method of claim 30, wherein the adhesion-enhancing process is a copper oxide treatment or a silane treatment.

32. The method of claim 21, wherein the low CTE conductive material comprises a metallized carbon or graphite sheet.

33. The method of claim 21, wherein the conductive material comprises a metallized fibrous material woven into a fabric or formed into an irregular paper fabric.

34. The method of claim 33, wherein the fibrous material is selected from the group consisting essentially of carbon fibers, graphite fibers, liquid crystal polymers, polyethylene fibers, quartz fibers, and glass fibers.