HK1015579B - Apparatus for demodulating and decoding video signals - Google Patents
Apparatus for demodulating and decoding video signals Download PDFInfo
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Description
Technical Field
The present invention relates to the field of digital signal processing, and more particularly to the demodulation and decoding of video signals encoded into different standards, such as satellite or terrestrial transmissions.
Background
Digital television systems for terrestrial or satellite broadcast modulate and encode signals for transmission in different ways and according to different signal formats. The specific method and format employed may be dictated by internationally recognized regulations. One such protocol established for the european satellite communication system is the "baseline modulation/channel coding system protocol for digital multi-program television using satellites" established by the european broadcasting union at 11/19 1993. This system is also known as the "Direct Video Broadcast (DVB)" system, which involves satellite and cable television signal distribution. Another transmission system that has been used in the united states, as defined by proprietary industry regulations, is the "Digital Satellite System (DSS)". However, regardless of whether the transmitted signal format is dictated by an approved standard or by proprietary industry regulations, the video signal receiver must be able to receive the transmitted signal format. U.S. patent 5497401 entitled viterbi decoder branch metric calculation apparatus for a punctured and applied trellis convolutional decoder suitable for multi-channel receivers for satellite, terrestrial and cable transmission of FEC compressed digital television data discloses a system for receiving different transmitted signal formats over different types of transmission, such as satellite, terrestrial and cable transmission ranges.
The video signal receiver uses demodulation and decoding functions that are specifically associated with the format of the signal to be received. The demodulation function depends on the type of modulation, the signal shape, the data rate employed by the transmission system, and whether a single-ended or differential output is required. The decoding function depends on the type of encoding, scrambling, interleaving, and the code rate employed by the transmission system encoder.
Disclosure of Invention
In accordance with the present invention, it is recognized that a signal processing network may advantageously accommodate a variety of demodulation and decoding functions within the context of, for example, a digital television signal processing system. In accordance with the principles of the present invention, a disclosed digital signal processing network provides an adaptive demodulation and decoding network that accommodates different types of demodulation and decoding functions.
According to one aspect of the invention, there is provided a demodulator network for demodulating a carrier wave modulated by video information according to one of a plurality of different modulation formats, comprising: a timing recovery network that recovers timing data from the modulated carrier; an adaptive carrier recovery network for recovering said video information from said carrier modulated in said different modulation formats in response to said timing data; and a selectable slicer network included in said carrier recovery network for applying a set of decision thresholds to data provided by said carrier recovery network to recover said video information, said set of decision thresholds being selected from a plurality of sets of decision thresholds adapted to said different modulation formats.
According to another aspect of the present invention there is provided a receiver apparatus for adaptively processing an input signal containing data in one of a plurality of different input formats and encoded in one of a plurality of different encoding formats, comprising: an adaptive timing recovery network that recovers timing information from a received input signal as a function of the input signal format; an adaptive data recovery network for recovering said data in response to said timing information; a selectable slicer network included in said data recovery network for applying a set of decision thresholds to data provided by said data recovery network to recover said data, said set of decision thresholds being selected from a plurality of sets of decision thresholds adapted for said different input formats; and an adaptive decoder for selectively decoding said recovered data as a function of the received data encoding format to produce recovered and decoded output data.
According to another aspect of the present invention there is provided a receiver for adaptively processing a carrier modulated by video data according to one of a plurality of different modulation formats, wherein said modulated video data is encoded according to one of a plurality of different formats, the receiver comprising: an adaptive timing recovery network for recovering timing data from the modulated carrier as a function of a received carrier modulation format; an adaptive carrier recovery network for recovering modulated data from said modulated carrier in response to said timing data; a selectable slicer network included in said carrier recovery network for applying a set of decision thresholds to data provided by said carrier recovery network to recover said modulated data, said set of decision thresholds being selected from a plurality of sets of decision thresholds adapted for said different modulation formats; an adaptive viterbi decoder viterbi decoding the recovered modulated data and providing a viterbi decoded output as a function of the received data encoding format; an adaptive de-interleaver for de-interleaving said viterbi-decoded output and for providing an output in accordance with a de-interleaving function selected from a plurality of de-interleaving functions; an adaptive error processor that error corrects the de-interleaved output to provide an error corrected output; and a descrambler for descrambling the error correction output.
According to one feature of the invention, the adaptive decoder provides decoded output data of the recovered video information.
According to another feature of the present invention, the signal quality detector utilizes a carrier recovery network signal to provide an estimate of the error of the recovered video information. The adaptive carrier recovery network is automatically compatible with the video modulated carrier in response to the error estimate.
Drawings
In the drawings:
fig. 1 is a block diagram of an apparatus for adaptively demodulating and decoding signals encoded in DSS and DVB formats in accordance with the principles of the present invention.
Figure 2 is a block diagram showing components of figure 1 for demodulating and decoding DSS satellite signal formats.
Figure 3 is a block diagram showing components of figure 1 that demodulate and decode DVB satellite signal formats.
Figure 4 is a functional block diagram showing the demodulation and decoding of the DVB cable signal format of figure 1.
Fig. 5 is a more detailed block diagram of the demodulation apparatus of fig. 1.
Fig. 6 is a block diagram showing an AGC error calculation function of the demodulation apparatus of fig. 5.
Detailed Description
A system of the present invention for demodulating and decoding signals of different signal formats, such as satellite and cable television signals, is shown in fig. 1. The system is particularly configurable to be capable of demodulating and decoding signals in a DSS satellite, DVB satellite or DVB cable signal format. This configurability is obtained by maximizing the use of functions common to the demodulation and decoding processes for these three signal formats. This configurability is also achieved by appropriately selecting, implementing and interfacing demodulation and decoding functions.
In fig. 1, a video data modulated carrier wave is received by an antenna 15, processed and digitized by a network 20. The resulting digital output signal is demodulated by demodulator 10 and decoded by decoder 12. The output of the decoder 12 is further processed to produce decompressed output video data suitable for display by the display settings. The demodulator 10 and decoder 12 are both adaptive demodulation and decoding networks having different types of demodulation and decoding functions that are selected by the microcontroller 105 using the interface 100. Both the demodulator 10 and the decoder 12 are configured by control signals from the microcontroller interface 100. The form of the control signal provided by the interface 100 is determined by the signal provided by the microcontroller 105 to the interface 100. In fig. 2, the demodulator 10 and decoder 12 of fig. 1 are configured to be capable of receiving DSS satellite signal formats. In fig. 3 and 4, the demodulator 10 and decoder 12 of fig. 1 are configured to be capable of receiving DVB satellite and DVB cable signal formats, respectively. The configurable demodulator 10 and the configurable decoder 12 may advantageously be housed within a single signal processing device, such as an integrated circuit.
The demodulator 10 may be configured to provide the functionality required to demodulate each of the DSS and DVB signal formats. The main functions of the demodulator 10 are to recover and track the carrier frequency, to recover the transmitted data clock frequency and to recover the video data itself. In addition, the demodulator also includes an AGC network (fig. 5) that appropriately scales the analog input data prior to the analog-to-digital conversion by unit 20. These demodulator functions are implemented with units 25, 30, 35, 40 and 45. The operations of timing recovery, carrier recovery, slicer and differential decoder are well known and are described briefly in, for example, digital communications by Lee and Messerschmidt (1988 by Kluwer academic press of boston, ma).
The different functional characteristics that the demodulator 10 exhibits in the three signal format modes are shown in table I.
TABLE IFunction of demodulator 10 in DSS and DVB modes
DSS | DVB satellite | DVB cable | |
Clock rate | Rate 1 | Rate 2 | Rate 3 |
Feed forward equalization | Is free of | Is free of | Is provided with |
Decision feedback equalization | Is free of | Is free of | Is provided with |
Excess bandwidth factor | 20% | 35% | 15% |
Modulation type | QPSK | QPSK | QAM |
Selectable signal groups | Is free of | Is free of | Has 64 points or 256 points |
Differential output decoding | Is free of | Is free of | Is provided with |
Demodulator 10 is able to accommodate differences in data clock rates, feed forward equalization, decision feedback equalization, Excess Bandwidth Factor (EBF), modulation type, symbol constellation and decoding listed in table I for the three input signal formats. The difference in clock rates is accommodated by ensuring that the system is able to operate at the highest and lowest data clock frequencies of the three input signal formats. Other differences are accommodated by configuring the associated demodulation functions as described below.
Fig. 5 illustrates the demodulator 10 of fig. 1 in more detail. In fig. 5, an input network 20 receives an input signal from an antenna 15, converts it to digital form, and processes it. The network 20 includes a Radio Frequency (RF) tuner and Intermediate Frequency (IF) mixer and amplifier stage 200 that downconvert the input video signal to a lower frequency band suitable for further processing. The network 20 also includes a gain controlled amplifier 205 and a split phase network 207. The phase splitting network splits the received video signal into quadrature I and Q components. Amplifier 205 scales the I and Q components appropriately for digitization by analog-to-digital converter 210 within network 20. The Automatic Gain Control (AGC) signal of amplifier 205 is provided by an AGC error detector network 270 described below. The digital signal of unit 210 is provided to multiplexer 215 of demodulator 10.
In satellite mode (DSS or DVB), the multiplexer 215 passes the digitized video signal from the network 20 to the rotator 225, bypassing the "Feed Forward Equalizer (FFE)" within the unit 220, under control of a control signal. In wired mode, multiplexer 215 passes the digitized signal to rotator 225 (e.g., a complex multiplier) via a "feed-forward equalizer" of unit 220 under control of a control signal. A "feed forward equalizer" is an adaptive FIR type digital filter that compensates for transmission channel disturbances such as frequency/phase irregularities.
The output data of multiplexer 215 is processed by a carrier recovery loop consisting of units 225, 220, 230, 30, 35, 40, 265, 260 and 255 that recovers the baseband video information. The data for unit 215 is a sequence of symbols in the form of complex I and Q quadrature components at the input of carrier recovery loop rotator 225. The sequence of symbols is a binary data sequence, with each symbol in the sequence being represented by a designated numerical value. As is well known, a symbol set may be represented in the complex plane by a set of points called a constellation. The DSS and DVB satellite signal formats use 4-point "Quadrature Phase Shift Keying (QPSK)" symbol constellation, and the DVB cable signal formats use 64 or 256-point "Quadrature Amplitude Modulation (QAM)" symbol constellation. The carrier recovery loop compensates for symbol point offsets and symbol point rotations caused by phase and frequency jitter of the carrier frequency introduced by the transmission channel. This compensation is accomplished by taking the error signal from the recovered data using a complex multiplier (rotator 225) and then applying the error signal to the loop input data to compensate for the phase and frequency jitter. The functions of each component of the carrier recovery loop are performed on the I and Q complex signal components using known signal processing techniques.
The complex multiplier function of rotator 225 multiplies the output data of element 215 by the compensation component of "Voltage Controlled Oscillator (VCO)" 255, producing the compensation data as an output. The compensation data from rotator 225 is passed through multiplexer 230 to slicers 30 and 35. In satellite mode, the control signal causes the multiplexer 230 to bypass the Decision Feedback Equalizer (DFE) of unit 220. Conversely, in wired mode, the control signal causes the multiplexer 230 to pass the compensated data from the rotator 225 to the DFE within the unit 220. The DFE adds the compensated data from rotator 225 to the delayed, scaled version of the selected slicer output from multiplexer 40. This summing operation is a well-known decision feedback equalization process that reduces inter-symbol interference in the compensated data of rotator 225. The DFE may be omitted in those applications where such interference is not significant. The feedback equalized data from unit 220 is returned to multiplexer 230 and passed to limiters 30, 35 and viterbi unit 50 of decoder 12.
Multiplexers 230 and 215 may both be part of equalizer 220 or may be omitted if a fixed satellite, terrestrial, or cable demodulation configuration is desired. Furthermore, although the FFE and DFE equalizers of unit 220 are shown as being external to demodulator 10, they may both be included within a single integrated circuit network along with demodulator 10. In this case, the adaptive FFE and DFE equalizers can be configured for a particular mode by programming the correct filter coefficients with the control signals.
As indicated in table I, the satellite input signal format is QPSK modulated and the cable input signal format is QAM. The configuration control signal is used by the multiplexer 40 to select the particular slicer used in the system depending on whether the input signal format is satellite QPSK or cable QAM. In addition, as indicated in table I, in the wired mode, QAM slicer 35 is also configured for the particular QAM symbol constellation involved. The limiter 35 then assumes a 64-point or 256-point group limiter function in response to the configuration control signal.
The corrected output from multiplexer 230, which is unequalized in satellite mode and feedback equalized in wired mode, is passed to limiters 30 and 35. Slicer 30 processes the corrected output from multiplexer 230 to recover data from the Quadrature Phase Shift Keying (QPSK) modulated signal. Likewise, slicer 35 recovers data from the QAM signal. Slicers 30 and 35 apply a series of decision thresholds to the corrected output of multiplexer 230 to recover the symbol sequence of the original demodulator 10 input data. In satellite mode, then, viterbi detection units 50 and 60 (fig. 1) of decoder 12 recover the data used by the receiver from the corrected output of multiplexer 230. Conversely, in wired mode, the recovered data used by the receiver is provided by the selected slicer (30 or 35) and output by the multiplexer 40. The output of multiplexer 40 is differentially decoded by unit 45 and passed to multiplexer 65 of decoder 12 (fig. 1). In wired mode, multiplexer 65 (fig. 1) responds to the control signal by differentially decoding the output of selection unit 45 for further processing and bypassing viterbi decoder units 50 and 60 in fig. 1. Differential encoding/decoding is a well-known technique used (in wired mode) to overcome problems associated with potential phase ambiguity in the generated carrier and recovered symbol constellation. The recovered data output by multiplexer 40 is used by the carrier recovery loop, timing recovery network, signal quality detector and AGC functions of demodulator 10 in both satellite and cable modes.
With continued reference to fig. 5, the recovered data at the inputs of the limiters 30, 35 and the output of the multiplexer 40 is processed by the phase error detector 265, the low pass filter 260 and the VCO255 of the carrier recovery loop to provide the I and Q feedback compensation signal components used by the rotator 225. Phase detector 265 determines an error signal representing the phase and frequency difference between the inputs of limiters 30 and 35 and the limiter output from multiplexer 40. The error signal is low pass filtered by unit 260 and used by VCO255 (as is known) to generate I and Q quadrature compensation components, which are processed by rotator 225 to generate an error compensation signal that is provided to multiplexer 230. Thereby compensating the signal applied to the multiplexer 230 for phase and frequency errors associated with symbol point offsets and symbol point rotations introduced during transmission.
The inputs to the limiters 30, 35 and the recovered data output signal of the multiplexer 40 are also used by the AGC error detector 270 to form a gain control signal. The control signal controls the gain of amplifier 205 within processor 20 and ensures that the I and Q input signals to the analog-to-digital converter of processor 20 are properly scaled as needed for proper analog-to-digital conversion. The detector 270 is based on the quadrature component (I) of the signal input to the limiters 30, 35m,Qm) And the quadrature component (I) of the output from the multiplexer 40s,Qs) The error is calculated as the difference between the squared sums of.
Fig. 6 shows an implementation of the AGC error calculation function within the detector 270. Quadrature input component I from limiters 30, 35 of multiplexer 230m、QmSquared by multipliers 300 and 305 and summed by adder 315. In addition, the quadrature component I of the recovered data output by the multiplexer 40s、QsIs used to access stored values in a look-up table in memory 310. The stored value represents IsAnd QsThe sum of the squared values of (a). This stored value of memory 310 is then subtracted from the output of adder 315 by subtractor 320 to produce the final AGC error. Detector 270 of fig. 6The calculated AGC error used is given by:
AGC error ═ I2 m+Qm 2)-(I2 ss+Q2 ss)(I2 m+Qm 2) The item is obtained from element 315, and (I)2 ss+Q2 ss) The item is utilizing IsAnd QsObtained as an input pointer from look-up table 310, which is (I)2 s+Qs 2) An approximation of. The advantage of this AGC error is I relative to the origin (0, 0)m,QmPoints and Is、QsA function of the difference in vector distances between points. Yet another advantage is the combination ofm、QmAnd Is、QsThe magnitude difference between the vectors of the orthogonal representation is independent. Because the AGC error signal has these characteristics, it can be low pass filtered and used to control the gain of AGC amplifier 205.
This AGC error calculation is superior to the actual error in mitigating computational complexity. The actual AGC error is given by:
actual AGC error ═ v (I)2 m+Qm 2)-√(I2 s+Q2 s)
As an alternative, the actual error function or another modified form of the actual error function may be substituted for the implementation of the AGC error signal of fig. 6.
The calculated AGC error signal is low pass filtered in detector 270 of fig. 5 to produce an output signal that controls the gain of amplifier 205. The AGC error signal is also provided to a signal quality detector unit 275.
Signal quality detector 275 estimates the signal-to-noise ratio (SNR) of the input signal to demodulator 10 using the AGC error signal provided by unit 270. Unit 270 first generates the absolute value of the AGC error signal. Unit 270 then applies a decision threshold to the result to determine whether the AGC error is within the programmed value range. Thus, the magnitude of the AGC error value corresponding to the estimate of the SNR value is determined. The SNR estimate is provided to the microcontroller 105 via the interface 100 of fig. 1. The microcontroller 105 is programmed to determine whether the SNR value is outside a predetermined range. If the SNR value is outside of the predetermined range, the microcontroller 105 can reconfigure the system including all of the configurable components-demodulator 10, equalizer 220, and decoder 12-for different input signal formats. In this manner, the microcontroller 105 can properly demodulate and decode the provided input signal format by repeatedly reconfiguring the functions of the demodulator 10 and decoder 12 using control signals from the interface 100. Such configuration functions may be programmed to be performed as part of the initialization step, or may be programmed based on input signals to the microcontroller, for example, from an operator accessible switch. The signal quality detector 275 may also estimate the error or SNR of the demodulated data by other methods. These methods include, for example, the calculation of the mean square error between the front and rear slicer data within the carrier recovery loop. Mean square error calculation and other error estimation methods are described in digital communications by Lee and Messerschmidt (1988 edition Kluwer academic press boston, ma, usa) and other literature.
The sampling and synchronization clocks used by the demodulator 10 of fig. 5 are generated by components including a filter 235, a symbol timing recovery unit 240, and an output processor 250. The output of the analog-to-digital converter 210 of the processor 20 is band-pass filtered by a configurable filter 235 to compensate for variations in the "Excess Bandwidth (EB)" represented by the "Excess Bandwidth Factor (EBF)". Although the preferred embodiment uses a band pass filter, other filtering characteristics, such as a low pass filter, may be used for EBF compensation. The resulting output, the input signals to the slicers 30 and 35 and the selected slicer output of the multiplexer 40 are used by the timing recovery unit 240 to generate the sampling and synchronization clocks. These recovered clocks, which correspond to the transmitter clock, are used to time the operation of demodulator 10, processor 20 (in particular the analog-to-digital conversion) and equalizer 220.
The timing component of fig. 5 utilizes the digital signal of the analog-to-digital converter 210 in generating the required timing information. Although the signal before being digitized by converter 210 exhibits the same raised cosine waveform for all three signal formats, variations in the "Excess Bandwidth Factor (EBF)" detailed in Table I will change this waveform. EBF is a reference that represents the extent to which the actual system bandwidth exceeds the minimum bandwidth required to ensure accurate signal recovery. Both EBF and raised cosine waveforms are described in the above-mentioned reference digital communications. Variations in EBF between input signal formats can cause errors in the recovered timing clock. To compensate for this timing error, the I and Q outputs of the analog-to-digital converter 210 are filtered by unit 235 before the timing and clock generation of unit 240. Filter 235 is programmed by microcontroller 105 through interface 100 to filter the digital video signal of converter 210 to achieve proper clock and timing recovery for each EBF value of the three input signal formats as shown in table I. The filter 235 may also be programmed to pass the signal without any filtering, for example, for testing purposes.
Within unit 240, the error compensation data of filter 235 is compared with both the data input to limiters 30, 35 and the recovered data output by multiplexer 40. Based on this comparison, unit 240 generates phase and timing error signals that are provided to symbol timing output processor 250. The signal comparison and the generation of the timing error signal are performed according to well-known principles, for example as detailed in "BPSK/QPSK timing error detector for sample receiver" by f.m. gardner (ieee transactions on Communication, 5 1986). The phase and timing error signals of cell 240 are filtered and buffered by output processor 250 to provide control signals to a voltage controlled crystal oscillator (VCXO) device included within cell 250. Although a monolithic VCXO may be used, in the preferred embodiment the VCXO is a separate device. The control signal input to the VCXO controls the frequency and phase of the sampling and synchronizing clock signals that it outputs. The sampled and synchronized clock outputs are used by analog-to-digital converter 210 and other demodulator components.
In fig. 1, a configurable decoder 12 provides the functionality required to decode DSS and DVB signal formats. The main functions of the decoder 12 include punctured convolutional viterbi decoders 50, 60, a symbol to byte mapper 70, a deinterleaver network 75, 80, 85, 90, 95, a reed-solomon decoder 110, and a descrambler 115. These individual functions are well known and described, for example, in the above-mentioned reference digital communication. The operating characteristics of the various components of the decoder 12 for the DSS and DVB modes are shown in table II.
Table II.Functionality of the decoder 12 in DSS and DVB modes
DSS | DVB satellite | DVB cable | |
Data puncturing convolutional code rate | 2/36/7 | 1/22/33/45/67/8 | Not applicable to |
Viterbi decoder | Is provided with | Is provided with | Is free of |
Symbol to byte mapper | 1 → 8 bits per symbol | 1 → 8 bits per symbol | 6 → 8(64-QAM) bits per symbol 8 → 8(256-QAM) bits per symbol |
Type of deinterlacer | Ramsey | Forney | Forney |
Descrambling device | Is free of | Is provided with | Is provided with |
The decoder 12 accommodates differences in code rate, deinterleaver type, symbol to byte mapping and descrambler requirements for the three input signal formats listed in table II. These differences are accommodated by configuring the functionality of the decoder 12 as described below.
Decoder stages 50 and 60 form a punctured convolutional viterbi decoder capable of decoding the various code rates shown in table II. Units 50 and 60 process, decode and error correct the filtered digital video signal output by unit 25 which is provided to the input of unit 50. These units provide a first level of correction of random transmission errors. One of two possible code rates (2/3 or 6/7) may be selected in a DSS satellite signal configuration. Conversely, one of five possible code rates (1/2, 2/3, 3/4, 5/6, or 7/8) may be selected in a DVB satellite signal configuration. The term "code rate" herein refers to the error correction overhead involved in encoding data. For example, a code rate of 1/2 refers to encoding 2 data bits for every 1 bit of input data. Similarly, a code rate of 7/8 refers to encoding 8 data bits for every 7 bits of input data. The variable code rate of the transmitted data stream is achieved by deleting bits from the encoded data stream that was encoded with the basic code rate of 1/2. For example, to obtain a code rate of 2/3, 1 bit of 4 bits generated by encoding 2 input data bits at a code rate of 1/2 is deleted, leaving 3 bits to be transmitted. Other code rates can be obtained using the same principles.
Unit 50 comprises means for synchronizing the video signal input data stream to enable viterbi decoding and for inserting "placeholder" blank bits. This is accomplished using a synchronous state machine that is configured with control signals from the interface 100 for the particular code being received. Synchronization is achieved by identifying and resolving bit positions and phase ambiguities within the input data stream. Bit positions and phase ambiguities are identified using processes of receiving, decoding, re-encoding, and comparing re-encoded data to input data. Successful synchronization is indicated by an acceptable error rate between the re-encoded data and the original input data. For this process, all possible states caused by ambiguity of phase and bit position in the input signal are detected by the synchronous state machine. If synchronization is not achieved, unit 50 generates an out-of-lock indication. This indication causes the VCO255 (fig. 5) of the demodulator 10 to insert the code type and configuration dependent phase shift into the incoming data stream. This synchronization process is repeated until locking is achieved. While this is the best method of synchronization, there are other methods that employ different sequences of operations.
After the data stream synchronization is achieved as described above, substitute "placeholder" white space bits equal in number to the deleted bits processed at the transmitter are inserted into the data stream. Appropriate "placeholder" blank bits are inserted with a configurable state machine within unit 50 for a particular code type and code rate of the received data stream. For a selected code rate, unit 50 is configured by loading registers within unit 50 in accordance with control signals transmitted by microcontroller 105 through interface 100. And configuring a 'occupancy' bit insertion state machine according to the loaded register information to insert the correct number of occupancy bits so as to realize proper code rate selection. This information is also used to appropriately configure the viterbi synchronization network of the unit 50 as well. After inserting the "placeholder" bits, the fixed basic code rate of 1/2 is output from unit 50. This means that the various transmission code rates shown in table II are all decoded using one viterbi decoder 60 operating at a fixed base code rate (1/2). The "placeholder" bits inserted within cell 50 are identified within viterbi decoder 60. The information identified from such placeholder bits enables the viterbi decoding algorithm to correctly decode the data. The output of the final viterbi decoder 60 is supplied to a multiplexer 65.
In a satellite input signal configuration, multiplexer 65 provides the output of viterbi decoder 60 to symbol to byte mapper 70 in response to a control signal from interface 100. The mapper 70 transforms the single bit output of the viterbi decoder 60 into an 8-bit mapped data byte. In a wired signal input configuration, on the other hand, multiplexer 65 provides the differentially decoded output of unit 45 to mapper 70 based on the state of the control signal. Further, in the wired input signal configuration, the function of the mapper 70 differs depending on whether 64 or 256 symbol groups are selected. If a 64-point QAM constellation is selected, the mapper 70 will code convert the 6-bit symbols into 8-bit mapped data bytes for each point of the 64-point constellation. Conversely, in the 256-point QAM burst mode, for each point of the 256-point burst, the mapper 70 transcodes the 8-bit symbol into an 8-bit mapped data byte.
The mapped data output of the mapper 70 is provided to a synchronization unit 75 and a memory 95 for further processing. The mapped data output is interleaved data. I.e. data that has been arranged in a predetermined order before transmission. The purpose of the interleaving operation is to spread or disperse the data over time within a predetermined sequence so that data loss during transmission does not result in loss of adjacent data. Instead, any data loss is spread out and therefore more easily masked or corrected. The synchronization unit 75 and the memory 95 together with the deinterleaver address generators 80, 85 and the multiplexer 90 constitute a configurable deinterleaving function that restores the data to its original sequence. In the DSS mode, the deinterlacing algorithm proposed by Ramsey in "implementation of the best interleaver" (IEEE Transactionson Information Theory, volume IT-15, 5/1970) is used. In contrast, in DVB mode, the algorithm proposed by Forney in "burst error code correction for classical burst error channel" (IEEE Transactions on Communications Technology, volume COM-19, 10/1971) is used.
The synchronization network 75 detects the sync word in the interleaved data signal and provides an output signal that is synchronized to the beginning of the data. The sync word itself is not interleaved but occurs periodically in time. To enable sync word detection, information identifying the sync word and the expected packet length is loaded into registers within unit 75. This information is provided by the microcontroller 105 through the interface 100 using control signals. The output synchronization signal of unit 75 is provided to address generators 80 and 85 to synchronize the address signals of units 80 and 85 with the interleaved data of mapper 70. The generated address signals are then provided to the memory 95 through the multiplexer 90.
In the DSS mode, multiplexer 90 provides the address signals of generator 80 to memory 95 according to the state of the control signal. In DVB mode multiplexer 90 provides address signals from generator 85 to memory 95 according to different control signal states. The Ramsey de-interlacing function is implemented in DSS mode with generator 80 and the Forney de-interlacing function is implemented in DVB mode with generator 85. These de-interleaving functions are implemented with a logic state machine. Generators 80 and 85 generate a series of read and write addresses and associated memory control signals (e.g., read, write and output enable) that are communicated to memory 95 through multiplexer 90. The sequence of write addresses generated by the generators 80, 85 ensures that the interleaved data of the mapper 70 is written to memory locations of the memory 95 in the order in which the input interleaved data was received. The sequence of read addresses generated by the generators 80, 85 ensures that the data is read from the memory 95 in the desired de-interleaving order. The resulting de-interleaved output data from memory 95 is provided to reed-solomon decoder 110. Additional background information regarding the operation of the configurable deinterlacer function is found in co-pending U.S. patent application No. 08/346,950 to j.s.
The reed-solomon decoder 110 operates in all modes of the decoder 12 to decode and error correct the deinterleaved output data from the memory 95. Reed-solomon decoder 110 is configured with internal registers that are loaded in response to control signals from interface 100. The information loaded into these registers configures the unit 110 to decode the expected data of a particular packet length in the de-interleaved output data of the memory 95. This information may also include other configuration parameters such as the number and type of parity bytes expected in the data, and parameters such as the type of reed-solomon decoder function selected for use.
The reed-solomon decoded data output of unit 110 is provided to descrambler 115 and multiplexer 120. In the DSS mode, multiplexer 120 provides the decoded data of cell 110 to output processor 125 based on the state of the control signal. Conversely, in the cable and satellite DVB modes as shown in table II, the decoded data of unit 110 is first descrambled by descrambler 115. In both modes, multiplexer 120 provides the descrambled output of cell 115 to output processor 125 in response to different control signal states. Output processor 125 processes the output data of multiplexer 120 to provide the "output data" of the system of fig. 1. The processor 125 provides the functionality required to interface this "output data" to other video receiver processing networks. These functions include aligning the output data with the appropriate logic levels and providing a clock signal associated with the output data signal to facilitate interfacing with other video receiver networks. Finally, although MPEG compatibility is not essential in systems employing the present invention, the output data of unit 125 is processed by MPEG compatible transport processor 130 to provide synchronization and error indication information for use in video data decompression. The transport processor 130 also separates data by type based on the header information analysis. The data output by processor 130 is decompressed by MPEG decompressor 135 to provide video data suitable for encoding into an NTSC format signal by NTSC encoder 140. The encoded decompressed output data of unit 140 is provided to a display processing circuit including a display device (not shown).
In the embodiment of fig. 2, the demodulator 10 and decoder 12 of fig. 1 are configured with control signals to process DSS satellite signal formats. The network shown in fig. 2 performs the same functions as described above with reference to fig. 1. In the DSS mode, the AGC loop of demodulator 10 (discussed with reference to fig. 5 and 6) uses the QPSK slicer output from multiplexer 40. The resulting gain-controlled filtered digital video signal output of unit 25 is then processed, viterbi decoded and error corrected by units 50 and 60 of decoder 12. In the DSS mode, the unit 50 may be configured according to either the 2/3 or 6/7 code rates as described above. The resulting viterbi-decoded output of unit 60 is passed through multiplexer 65 to symbol to byte mapper 70. The output of the mapper 70 is deinterleaved by units 75, 85, 90 and 95, for example, configured in accordance with a Ramsey deinterleaver function. The de-interleaved output of memory 95 is decoded by reed-solomon decoder 110 and passed through multiplexer 120 to output processor 125. The decoded demodulated output of processor 125 is processed by networks 130, 135 and 140 as described with reference to fig. 1.
In the embodiment of fig. 3, the demodulator 10 and decoder 12 of fig. 1 are configured with control signals to process DVB satellite signal formats. The network shown in fig. 3 performs the same functions as described above with reference to fig. 1. In the DVB satellite mode, the AGC loop of the demodulator 10 uses the QPSK slicer output from the multiplexer 40 as in the DSS mode. The resulting gain-controlled filtered digitized video signal output of unit 25 is then processed, viterbi decoded and error corrected by units 50 and 60 of decoder 12. In the DVB mode, unlike the DSS mode, the unit 50 can be configured at 5 different code rates (1/2, 2/3, 3/4, 5/6, and 7/8). The resulting viterbi-decoded output of unit 60 is passed through multiplexer 65 to symbol to byte mapper 70. The output of the mapper 70 is deinterleaved by units 75, 80, 90 and 95 configured according to the Forney deinterleaver function. The de-interleaved output of memory 95 is decoded by reed-solomon decoder 110, descrambled by unit 115, and then passed through multiplexer 120 to output processor 125. The decoded demodulated output of processor 125 is processed by networks 130, 135 and 140 as described with reference to fig. 1.
In the embodiment of fig. 4, the demodulator 10 and decoder 12 of fig. 1 are configured with control signals to receive DVB cable signal formats. The network shown in fig. 4 performs the same functions as described above with reference to fig. 1. In this DVB cable mode, the AGC loop of demodulator 10 uses the QAM slicer output from multiplexer 40. The QAM slicer is configured according to 64 or 256-point symbol groups according to the input signal of the demodulator 10. The final data recovered by the selected slicer configuration at the output of multiplexer 40 is differentially decoded by unit 45 and provided to multiplexer 65 of decoder 12. The decoded output of unit 45 is passed through multiplexer 65 to symbol to byte mapper 70. The output of the mapper 70 is deinterleaved by units 75, 80, 90 and 95, for example configured in accordance with the Forney deinterleaver function. The de-interleaved output of memory 95 is decoded by reed-solomon decoder 110, descrambled by unit 115 and passed through multiplexer 120 to output processor 125. The decoded demodulated output of processor 125 is processed by networks 130, 135 and 140 as described with reference to fig. 1.
The demodulator 10 and decoder 12 functions and means for configuring and selecting both functions may be implemented in a variety of ways. For example, instead of selecting these functions with multiplexers, a configurable logic network may be used to perform various functions. Alternatively, a tri-state logic buffering scheme may be used to select between the individual functional outputs instead of using a multiplexer to select. Furthermore, by applying the principles of the present invention, the functionality itself may be altered to provide decoding and demodulation of other input signal formats.
Claims (19)
1. A demodulator network for demodulating a carrier wave modulated by video information in accordance with one of a plurality of different modulation formats, comprising:
a timing recovery network (25) for recovering timing data from the modulated carrier;
an adaptive carrier recovery network (25) for recovering said video information from said carrier modulated in said different modulation formats in response to said timing data; and
a selectable slicer network (30, 35, 40) included in said carrier recovery network for applying a set of decision thresholds to data provided by said carrier recovery network to recover said video information, said set of decision thresholds being selected from a plurality of sets of decision thresholds adapted for said different modulation formats.
2. The demodulator network of claim 1, further comprising:
an Automatic Gain Control (AGC) network (25; 270) provides a gain control output that is a function of the difference between the signal generated before the limiter network and the signal generated after the limiter network.
3. The demodulator network of claim 1, wherein:
the timing recovery network includes a configurable filter to compensate for excessive bandwidth variations of the modulated carrier.
4. The demodulator network of claim 1, wherein:
the selectable slicer network applies decision thresholds appropriate for PAM, QPSK or QAM symbol groups.
5. The demodulator network of claim 1, wherein:
the modulation format of the video information uses a symbol group comprising a plurality of symbol points.
6. The demodulator network of claim 1, wherein:
the carrier recovery network further includes a selectable equalizer network (220) for compensating for errors associated with the transmission channel, the configuration of the equalizer network being selected in accordance with the modulation format of the modulated carrier.
7. The demodulator network of claim 6, wherein:
the selectable equalizer network includes a feedforward equalizer and a decision feedback equalizer.
8. The demodulator network of claim 1, further comprising:
a selectable differential decoder (45) for differentially decoding signals generated by the carrier recovery network.
9. The demodulator network of claim 1, wherein:
the carrier recovery network can operate at different clock rates.
10. The demodulator network of claim 1, further comprising:
a signal quality detector (275) providing as output estimates of errors present in said recovered video information obtained in accordance with said different modulation formats.
11. The demodulator network of claim 10, wherein:
automatically configuring the adaptive carrier recovery network to be compatible with the modulation format of the video modulated carrier based on the error estimate.
12. The demodulator network of claim 10, wherein:
the error estimate is a function of the sum of the squares of the quadrature components of the signal processed by the carrier recovery network.
13. The demodulator network of claim 10, wherein:
the error estimate is a function of a difference between the first and second values, wherein:
the first value represents a sum of squares of quadrature components of a signal input to the limiter network, and
the second value represents a sum of squares of quadrature components of an output signal of the limiter network.
14. A receiver apparatus for adaptively processing an input signal containing data in one of a plurality of different input formats and encoded in one of a plurality of different encoding formats, comprising:
an adaptive timing recovery network (25) for recovering timing information from the input signal as a function of the received input signal format;
an adaptive data recovery network (25) for recovering said data in response to said timing information;
a selectable slicer network (30, 35, 60) included in said data recovery network for applying a set of decision thresholds to data provided by said data recovery network to recover said data, said set of decision thresholds being selected from a plurality of sets of decision thresholds adapted for said different input formats; and
an adaptive decoder (12) selectively decodes the recovered data as a function of the received data encoding format to produce recovered and decoded output data.
15. The apparatus of claim 14, wherein:
said input signal is a carrier wave modulated by said data, said input format is a modulation format, said modulation and coding format is suitable for satellite, terrestrial or cable transmission; and
the data recovery network is a carrier recovery network.
16. The apparatus of claim 15, further comprising:
a signal quality detector (275) providing as an output an estimate of an error occurring in said recovered and decoded output data.
17. The apparatus of claim 16, wherein:
automatically configuring the adaptive receiver to be compatible with the received carrier modulation format based on the error estimate.
18. A receiver for adaptively processing a carrier modulated by video data in accordance with one of a plurality of different modulation formats, wherein said modulated video data is encoded in accordance with one of a plurality of different formats, comprising:
an adaptive timing recovery network (25) for recovering timing data from the modulated carrier as a function of a received carrier modulation format;
an adaptive carrier recovery network (25) for recovering modulated data from said modulated carrier in response to said timing data;
a selectable slicer network (30, 35, 40) included in said carrier recovery network for applying a set of decision thresholds to data provided by said carrier recovery network to recover said modulated data, said set of decision thresholds being selected from a plurality of sets of decision thresholds adapted for said different modulation formats;
an adaptive viterbi decoder (50, 60) viterbi decoding said recovered modulated data and providing a viterbi decoded output as a function of the received data encoding format;
an adaptive deinterleaver (80, 85, 90) for deinterleaving the viterbi-decoded output and providing an output in accordance with a deinterleaving function selected from a plurality of deinterleaving functions;
an adaptive error processor (110) that error corrects the de-interleaved output to provide an error corrected output; and
a descrambler (115) for descrambling the error correction output.
19. The apparatus of claim 18, further comprising:
a signal quality detector (275) providing as an output an estimate of an error occurring in said recovered and decoded output data.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US501,361 | 1995-07-12 | ||
US08/501,361 US5671253A (en) | 1995-07-12 | 1995-07-12 | Apparatus for demodulating and decoding video signals encoded in different formats |
PCT/US1996/011109 WO1997003509A1 (en) | 1995-07-12 | 1996-06-28 | Apparatus for demodulating and decoding video signals |
Publications (2)
Publication Number | Publication Date |
---|---|
HK1015579A1 HK1015579A1 (en) | 1999-10-15 |
HK1015579B true HK1015579B (en) | 2003-09-11 |
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