MXPA98000366A - Device for decoding video signals coded in different way - Google Patents

Abstract

The present invention relates to an adaptive receiver including an adaptive decoder (12) for providing decoded output information from a video encoded signal for satellite, terrestrial or cable transmission. The apparatus includes an adaptive decoder (50, 60) for providing a first decoded output as a function of an encoder rate selected from a plurality of code schemes. The apparatus also includes an adaptive deinterleaver (80, 85, 90) for deinterleaving the first decoded output according to a deinterleaver function selected from a plurality of deinterleaver functions. In addition, the apparatus includes an output signal processor (125) for processing the deinterleaved output information to provide the decoded output information. The demodulator can also incorporate an adaptive error decoder (110) to detect and correct errors in the deinterleaved output. In addition, a signal quality detector can provide an estimate of the error in the decoded output information. The device is automatically configured to be compatible with the format of the encoded video signal in response to the err estimate.

Description

DEVICE FOR DECODING VIDEO SIGNALS CODED IN DIFFERENT FORMATS This invention relates to the field of digital signal processing, and more particularly to the demodulation and decoding of video signals encoded for different standards for satellite or terrestrial transmission, for example. Digital television systems used for terrestrial or satellite broadcast modulate and encode television signals for transmission by different methods and in different signal formats. The particular method and format adopted can be prescribed by an internationally recognized specification. One of those specifications, prepared for a European satellite communication system, is the "Specification of the Baseline Modulation System / Channel Coding for Digital Television of Multiple Satellite Programs" by the European Broadcasting Union, November 19 1993. This system is also known as a Direct Video Broadcasting (DVB) system and covers both the distribution of satellite and cable television signals. Another transmission system, already in use in the United States of North America and defined by a proprietary commercial specification, is the Digital Satellite System (DSS). However, whether the transmitted signal format is prescribed by a recognized standard or by a proprietary commercial specification, a video signal receiver must be able to receive the transmitted signal format. A system for receiving different signal formats transmitted in the context of different types of transmission such as satellite, terrestrial and cable is described in United States Patent Number: 5,497,401, entitled "A Branch Metric Computer for a Viterbi Decoder of a Punctured and Pragmatic Trellis Code Convolutional Decoder Suitable for Use in a Multi-Channel Receiver of Satellite, Terrestrial and Cable Transmitted FEC Compressed-Digital Television Data "(A branched measurement computer for a Viterbi decoder of a pragmatic Trellis code convolutional decoder and convenient points for use in a multi-channel receiver of FEC compressed digital television information transmitted via satellite, terrestrial and cable) by JS Stewart and collaborators. A video signal receiver employs demodulation and decoding functions that are specifically related to the signal format to be received. The demodulation function depends on the type of modulation, the shape of the signal, the information regime used by the transmission system, and whether a simple or differential output is required. The decoding function depends on the type of coding, disturbance, interleaving and the code rate used by the encoder of the transmission system. In accordance with the present invention, it is recognized that a signal processing network can conveniently accommodate multiple decoding functions in the context of a digital television signal processing system, for example. In accordance with the principles of the invention, a developed digital signal processing network provides adaptive decoding networks that incorporate different types of decoding functions, illustratively related to code rate, deinterleaving, and error processing functions. In a system for adaptively receiving and processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission, the apparatus according to the principles of the invention provides decoded output information. In an illustrated embodiment, the apparatus includes an adaptive decoder to provide a first decoded output as a function of a selected code rate of a plurality of code schemes. The apparatus also includes an adaptive deinterleaver for deinterleaving the first decoded output according to an interleaving function selected from a plurality of deinterleaving functions. further, the apparatus includes an output signal processor for processing the deinterleaved output information to provide the decoded output information. In accordance with a feature of the invention, an adaptive error decoder detects and corrects errors in an adaptive decoder output. According to another characteristic of the invention, a signal quality detector provides an error estimate in the decoded output information. The device is automatically configured to be compatible with the encoded video video signal format in response to the error estimate.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawing: Figure 1 is a block diagram of the apparatus according to the principles of the invention for adaptively demodulating and decoding signals encoded in digital satellite system and direct video broadcast formats. Figure 2 is a block diagram showing the elements of Figure 1 configured to demodulate and decode a satellite signal format of digital satellite system. Figure 3 is a block diagram showing the elements of Figure 1 configured to demodulate and decode a satellite DVB direct video broadcast signal format. Figure 4 is a block diagram showing the elements of the function of Figure 1 configured to demodulate and decode a DVB direct video broadcast cable signal format. Fig. 5 is a more detailed block diagram of the demodulator apparatus of Fig. 1. Fig. 6 is a block diagram showing the automatic gain control error computation function of the demodulator apparatus of Fig. 5. according to the invention for demodulating and decoding signals of different signal formats such as cable and satellite television signals is shown in Figure l. In particular, this system can be configured to demodulate and decode signals in satellite signal formats by digital satellite system, satellite by direct video broadcasting or cable by direct video broadcasting. This possibility of configuration has been achieved by maximizing the use of functions common to the process of demodulation and decoding of three signal formats. It has also been achieved through the proper selection, implementation and interplay of the demodulation and decoding functions. In Figure 1, a carrier wave modulated with video information is received by an antenna 15, and is processed and digitized by the network 20. The resulting digital output signal is demodulated by the demodulator 10 and decoded by the decoder 12. The output of the decoder 12 is further processed to provide decompressed output video information suitable for display by a visual display device. Both the demodulator 10 and the decoder 12 are adaptive demodulation and decoding networks incorporating different types of demodulation and decoding functions that are selected by a microcontroller 105 via the interface 100. The status of the Control signal provided by the interface 100 is it determines by signals provided by the microcontroller 105 for the interface 100. In Figure 2, the demodulator 10 and the decoder 12 of Figure 1 are configured to receive a satellite signal format of digital satellite system DSS. In Figures 3 and 4, the demodulator 10 and the decoder 12 of Figure 1 are configured to receive the DVB satellite and DVB cable signal formats, respectively. Both the configurable demodulator 10 and the configurable decoder 12 can be conveniently housed in a single signal processing device such as an integrated circuit, for example. The configurable demodulator 10 provides the functions required to demodulate each of the DSS digital satellite system and satellite and DVB cable signal formats. The primary functions of the demodulator 10 are the recovery and immediate visualization of the frequency of the carrier wave, the recovery of the clock frequency of the transmitted information, and the recovery of the video information itself. In addition, the demodulator includes an automatic gain control network (FIG. 5) for appropriately scaling analog input information prior to the analog-to-digital conversion in unit 20. The functions of the demodulator are implemented by the units., 30, 35, 40 and 45. Synchronization recovery, carrier wave recovery, splitter and differential decoder operations are known individually and are generally described, for example, in the reference text Digi tal Coiranunication, Lee and Messerschmidt (Kluwer Academic Press, Boston MA, USA, 1988). The different functional characteristics presented by the demodulator 10 in the three format modes are shown in Table I.

The demodulator 10 accommodates the differences in the information clock rates, feed forward equalization, decision feedback equalization, bandwidth factor (EBF), modulation type, symbol constellations and decoding for three signal formats. entry listed in Table I. The difference in the clock rate is accommodated by ensuring that the system is capable of operating at the highest and lowest information clock frequencies of the three input signal formats. The other differences are accommodated by configuring the demodulation functions concerned as described below. Figure 5 represents the demodulator 10 of Figure 1 in greater detail. In Figure 5, an input signal is received from the antenna 15, converted to the digital form and processed by the input network 20. The network 20 includes a radio frequency (RF) tuner and an intermediate frequency mixer (IF). ) and amplification states 200 for converting downward the video signal input to a lower frequency band suitable for further processing. The network 20 also includes a gain controlled amplifier 205 and a phase division network 207. The phase division network divides the video signal into the quadrature components I and Q. The amplifier 205 appropriately scales the components I and Q for digitizing by analog-to-digital converters 210 within the network 20. An automatic gain control signal (AGC) for the amplifier 205 is provided by the automatic gain control error detector network 270 described below. A digital signal from the unit 210 is provided to the multiplexer 215 of the demodulator 10. In the satellite mode (DSS or DVB), the multiplexer 215, as determined by the Control signal, drives the digitized video signals from the network 20. to the rotating part 225 and deflects them by a forward power equalizer (FFE) within the unit 220. The forward power equalizer is an adaptive FIR type digital filter and compensates for the disturbances of the transmission channel as the irregularities of frequency / phase. The output information from the multiplexer 215 is processed by a carrier wave recovery cycle comprised of the units 225, 220, 230, 30, 35, 40 and 265, 260 and 255 to recover the baseband video information. The information of the unit 215 is a sequence of symbols in the form of the complex I and Q components of the quadrature at the entrance to the rotating part of the recovery cycle of the carrier wave 225. This sequence of symbols is a sequence of information binary where each symbol is represented by assigned digital values. The set of symbols can be represented in a complex plane as a set of points called a constellation of signals, as it is known. The DSS and DVB digital satellite system satellite signal formats use a 4-point quadrature phase shift manipulation (QPSK) symbol constellation, and the DVB cable signal format uses a constellation of radio modulation symbols. Quadrature amplitude (QAM) either of 64 or 256 points. The carrier wave recovery cycle compensates for the deviation of symbol points and the rotation of the symbol points caused by the phase and frequency tremor at the frequency of the carrier wave introduced by the transmission channel. This is achieved by deriving an error signal from the recovered information, followed by the application of the error signal to the input information of the cycle to compensate for the phase and frequency tremor using a complex multiplier (rotating part 225). Each of the functions of the elements of the recovery cycle is performed by both components of complex signals I and Q, using known signal processing techniques. The function of the complex multiplier of the rotating part 225 multiplies the output information of the unit 215 by the compensation components from the controlled voltage oscillator (VCO) 225 to produce information compensated as an output. The compensated information of the rotary part 225 is passed to the dividers 30 and 35 via the multiplexer 230. In a satellite mode, the Control signal causes the multiplexer 230 to bypass the decision feedback equalizer (DFE) of the unit 220. In contrast, in the cable mode, the Control signal causes the multiplexer 230 to conduct the compensated information from the rotary 225 to the decision feedback equalizer (DFE) in unit 220. The decision feedback equalizer sum this information compensated from the rotary part 225 with a scaled, delayed version of the divider output selected from the multiplexer 40. This addition operation is a known decision feedback equalization process and reduces intersymbol interference in the compensated information output of the rotating part 225. In those applications where the interference is not significant, the feedback equalization can be omitted. of decision The equalized feedback information from the unit 220 is returned to the multiplexer 230 and passed to the dividers 30, 35 and the Viterbi unit 50 of the decoder 12. Both multiplexers 230 and 215 can be part of the equalizer 220, or eliminated if desired. fixed demodulation configuration of satellite, terrestrial or cable. In addition, although both the FFE and DFE equalizers of the unit 220 are displayed external to the demodulator 10, they can be included with the demodulator 10 in a single integrated circuit network. In that case, the adaptive equalizers FFE and DFE can be configured for a particular mode by programming the appropriate filter coefficients using the Control signal. As indicated in Table I, the satellite input signal formats are modulated by quadrature phase shift manipulation (QPSK) and the input signal format is a type of quadrature amplitude modulation. The particular divider used in the system is selected by the configuration of the control signal via the multiplexer 40 depending on whether the format of the input signal is of quadrature satellite phase shift modulation or quadrature extension modulation type. of cable. In addition, in the cable mode, the quadrature extension modulation divider 35 is also configured for the particular quadrature magnification modulation symbol constellation involved as indicated in Table I. Then, the divider 35 has a function of divider of a constellation of either 64 points or 356 points in response to the configuration control signal. The corrected output of the multiplexer 230, which is inequalized in the satellite mode and equalized by feedback in the cable mode, is passed to the dividers 30 and 35. The divider 30 processes the corrected output from the multiplexer 230 to retrieve the information from the Modulated signals of Quadrature Phase Change Manipulation (QPSK). Similarly, the divider 35 retrieves information from quadrature magnification modulation signals. The dividers 30 and 35 apply a series of decision thresholds to the sequence of the input information of the original demodulator. Then, in the satellite mode, the information used by the receiver is retrieved from the corrected output of the multiplexer 230 by the Viterbi detection units 50, 60 of the decoder 12.

(Figure 1) . In contrast, in the cable mode, the recovered information used by the receiver is provided by the selected splitter (30 or 35) and the output by the multiplexer 40. The output of the multiplexer 40 is differentially decoded by the unit 45 and passed to the multiplexer 65 of the decoder 12 (Figure 1). In the cable mode, the multiplexer 65 (Figure 1) responds to the Control signal by selecting the differential decoded output of the unit 45 for further processing and bypasses the Viterbi decoder units 50 and 60 in Figure 1. The encoding / decoding Differential is a known technique used (in cable mode) to overcome the problem associated with the potential ambiguity of the phase in the derived carrier wave and in the recovered symbol constellation. The output of the information retrieved from the multiplexer 40 is used in both the satellite and cable modes by the carrier wave recovery cycle, the synchronization recovery network, the signal quality detector and the control functions of the receiver. automatic gain of the demodulator 10. Continuing with Figure 5, the input to the dividers 30, 35 and the information output recovered from the multiplexer 40 are processed by the phase error detector of carrier wave recovery cycle 265, the filter of low pass 260 and VCO 225, to provide the feedback compensation signal components I and Q used by the rotating part 225. The phase detector 265 determines an error signal representing the phase and the frequency difference between the input to the dividers 30 and 35, and the output of the splitter from multiplexer 40. This error signal is filtered by low pass by unit 260 and is used by Oscillating r voltage controlled 255 (as is known) to generate the quadrature compensation components I and Q which are applied by the rotary part 225 to provide compensated error signals to the multiplexer 230. By these means the signals applied to the multiplexer 230 are compensate for the phase and frequency errors associated with the deviation of the symbol points and the rotation of symbol points during transmission. The input to the dividers 30, 35 and the output signal of the information retrieved from the multiplexer 40 are also used by the automatic gain control error detector 270 to form a gain control signal. This control signal controls the gain of the amplifier 205 in the processor 20, and ensures that the I and Q input signals to the analog-to-digital converters of the processor 20 are appropriately scaled as required for the proper analog-to-digital conversion. The detector 270 calculates an error based on the difference between the sum of the squares of the components of the quadrature of the signal input to the dividers 30, 35 (Im, Qm), and the sum of the squares of the components of the quadrature of the output of multiplexer 40 (Is, Qs). Figure 6 shows an implementation of the computation function of the automatic gain control error within the detector 270. The separator 30, 35 the input components of the square Im, Qm of the multiplexer 230 are squared by the multipliers 300 and 305 and added by the adder 315. In addition, the quadrature components Is, Qs of the information output retrieved from the multiplexer 40 are used to access a value stored in a look-up table in the memory 310. This stored value represents the sum of the square values of Is and Qs. The value stored from the memory 310 is subtracted from the output of the adder 315 by the subtractor 320 to produce the resulting automatic gain control error. The implementation of the computed automatic gain control error used by detector 270 in Figure 6 is given by: AGC error = (Im2 + Qm2) - (Iss2 + Qss2). The term (Im2 + Qm2) is obtained from unit 315 and the term (Iss2 + Qss2) is obtained from query table 310 as an approximation of (Is2 + Qs2) using Is and Qs as input pointers. This automatic gain control error has the advantage of being a function of the difference in the distance of the vector between the point Im, Qm and the point Is, Qs with respect to a point of origin (0,0). It also has the advantage of being independent of the angular difference between the vectors represented by the quadrature components Im, Qm and Is. Because the automatic gain control error signal has these characteristics, it can be filtered at a low rate and Use to control the gain of the Automatic Gain Control Amplifier 205. This calculation of the Automatic Gain Control error is preferably used with respect to the actual error to reduce computational complexity. The actual Automatic Gain Control error is given by: Real Automatic Gain Control Error = 1 (Im¿ + Qvc? Z) (Is < Qs2) As an alternative, the current error function or other modified version of the actual error function can be used instead of the implementation of the Automatic Gain Control error signal of Figure 6. The Gain Control error signal calculated automatic is filtered at low pass within the detector 270 of Figure 5 to produce an output signal to control the gain of the amplifier 205. The automatic gain control error signal is also provided to the signal quality detector unit 275 The signal quality detector 275 estimates the signal with respect to the noise ratio (SNR) of the input signal with respect to the demodulator 10 using the automatic gain control error signal provided by the unit 270. The unit 270 first it forms the absolute value of the Automatic Gain Control error signal. Then unit 270 applies the decision thresholds to the result to determine whether the Automatic Gain Control error is within a programmed range of values. This provides a determination of the magnitude of the error of the Automatic Gain Control value that corresponds to an estimate of the value of SNR. This SNR estimate is provided to microcontroller 105 via interface 100 in Figure 1.E1 microcontroller 105 is programmed to determine if the SNR value falls outside a previously determined range. If the SNR value is outside the previously determined range, the microcontroller 105 can reconfigure the system including all the configurable elements of the demodulator 10, the equalizer 220 and the decoder 12 for a different input signal format. In this way, the microcontroller 105 can iteratively reconfigure the demodulator 10 and the decoder 12 operates using the Control signal via the interface 100 to properly demodulate and decode the applied input signal format. This configuration function can be programmed to be performed as part of the initialization procedure or in response to an input signal to the microcontroller from a switch accessible to the operator, for example. In addition, the signal quality detector 275 may use other methods to make an error or SNR estimate in the demodulated information. These methods include, for example, an average squared error calculation and other error estimation methods described in Digi tal communication, Lee and Messerschmidt (Kluwer Academic Press, Boston, MA, USA, 1988) and other texts. The sampling and synchronization clocks used by the demodulator 10 in Figure 5 are generated by elements including the filter 235, the synchronization recovery unit 240 and the output processor 250. The outputs of the analog-to-digital converters 210 the processor 20 is filtered by bandpass by the configurable filter 235 to compensate for variations in excess bandwidth (EB) as expressed by the excess bandwidth factor (EBF). Although the preferred embodiment uses a bandpass filter, other filter characteristics such as a lowpass filter can be used for compensation of the excess bandwidth factor. The resulting output, the input signals to the dividers 30 and 35, and the output of the selected divider of the multiplexer 40 are used by the synchronization recovery unit 240 to generate the sampling and synchronization clocks. These recovered clocks correspond to transmitter clocks and are used to synchronize the operation of the demodulator 10, and processor 20, (in particular the analog-to-digital conversion), and the equalizer 220. To derive the required synchronization information, the synchronization elements of Figure 5 use a digital signal from the analog-to-digital converters 210. Although the signal prior to digitization by the converters 210 has the same elevated cosine form for the three signal formats, variations in the excess bandwidth factor (EBF) detailed in Table I may alter this form. The excess bandwidth factor is a parameter that indicates the degree to which the bandwidth of the actual system exceeds the minimum bandwidth required to ensure accurate signal recovery. Both the bandwidth factor and the elevated cosine shape are described in the reference text Digi tal Communication, mentioned previously. The variation in the bandwidth factor and the shape of the input signal between the input signal formats can cause an error in the recovered synchronization clocks. In order to compensate for this synchronization error, the I and Q outputs of the analog-to-digital converters are filtered by the unit 235 prior to the generation of the clock and synchronization in the unit 240. The filter 235 is programmed by the microcontroller 105 via the interface 100 to filter the digital ideo signal from the converters 210 for proper clock recovery and synchronization for each of the bandwidth factor values of the three input signal formats as shown in Table I. The filter 235 can be programmed to compensate for various signal forms and excess bandwidth factor values in addition to those of the three input signal formats described in the Table.

I. Also, filter 235 can also be programmed to pass unfiltered signals, for example for testing purposes. Within the unit 240 the error compensated information of the filter 235 is compared with both the information input to the dividers 30, 35 and the information output retrieved from the multiplexer 40. Based on this comparison, the unit 240 derives a signal of phase error and synchronization that is applied to a symbol synchronization output processor 250. The comparison of signals and derivation of the synchronization error signal is performed according to known principles as detailed, for example, in " BPSK / QPSK Timing-Error Detector for Sampled Receivers ", by FM Gardner, IEEE Transactions on Communications, May 1986. The phase error signal and synchronization of the unit 240 is filtered and sent to interim memory by the output processor 250 to provide a control signal to a controlled crystal oscillator (VCXO) device included in unit 250. In the preferred embodiment, the VCXO is a separate device, although an integral VCXO can be used. The control signal input to the VCXO controls both the sampling frequency and phase and the output of the synchronization clock signal via the VCXO. This sampling and synchronization clock output is used by analog-to-digital converters 210 and other demodulator elements. In Figure 1, the configurable decoder 12 provides the functions required to decode the DSS and DVB digital satellite system signal formats. The primary functions of the decoder 12 include a convolution Viterbi decoder 50, 60, a byte symbol mapper 70, a de-interleaver network 75, 80, 85, 90, 95, a Reed-Solomon 110 decoder, and a 115 alarm clock. individual functions are known and described, for example, in the reference text Digi tal Communication previously noted. The operating characteristics of the decoder elements 12 are shown in Table II for the digital satellite system modes DSS and DVB.

Table II 12 decoder functions in DSS and DVB modes The decoder 12 accommodates differences in the code rate, in the type of deinterleaver, in the symbol for mapping the bytes and in the requirements of the wake-up device for the three input signal formats, as listed in Table II. The differences are accommodated by configuring the functions of the decoder 12 as described below. The stages of the decoder 50 and 60 constitute a dotted convolution Viterbi decoder capable of decoding the various code regimes shown in Table II. The units 50 and 60 process, decode and correct errors of the digital video signal outputs from the unit 25 that the input of the unit 50 is applied.

These units provide a first level of random error correction. In the DSS digital satellite system satellite signal configuration one of two possible code regimes (2/3 or 6/7) can be selected. Conversely, in the DVB satellite signal configuration, one of five possible code schemes (1/2, 2/3, 3/4, 5/6, or 7/8) can be selected. The term "code regime" in this context defines the higher correction error carried by the encoded information. For example, a code rate of 1/2 means that 2 bits of information are encoded by each bit of input information. Similarly, a code rate of 7/8 means that 8 bits of information are encoded per 7 bits of input information. The variable code rate of the transmitted information stream is achieved by erasing bits of a coded information stream with a base code rate of 1/2. For example to achieve a 2/3 code rate one of the 4 bits produced by encoding 2 bits of input information in the 1/2 code rate is cleared, leaving 3 bits to be transmitted. The other code regimes are achieved using the same principle. The unit 50 includes conditions for synchronization of the input information stream of the video signal to enable Viterbi decoding and the insertion of the phantom bits for the "space section". this is achieved by using a synchronization state machine which is configured by the Control signal via the interface 100 for the particular code being received. The synchronization is achieved by identifying and resolving both the positions of the bits and the ambiguities of the phases in the input information stream. The position of the bits and the phase ambiguities are identified by a process of receiving, decoding, re-encoding and comparing the information to be encoded with the input information. Successful synchronization is indicated by an acceptable error rate between the information to be encoded and the original input information. By this process all the possible states that arise from the ambiguities of phase position and bits in the input signal are tested by the synchronization state machine. If synchronization has not been achieved, an out-of-closure indication is generated by the unit 50. This indication causes the voltage-controlled oscillator 255 of the demodulator 10 (Figure 5) to insert a type of code and a dependent phase change within the input information stream. This synchronization process is repeated until closure is reached. Although this is the preferred synchronization method, other methods using different operation sequences are also possible.

After the information stream has been synchronized as mentioned above, the replacement of the phantom bits of the location section equals the bits erased in the transmitter and inserted into the information stream. A configurable state machine in the unit 50 is used to insert the appropriate "apart-place" ghost bits for the type and rate regime of the information stream. The unit 50 is configured for the selected code rate by loading a register within the unit 50 in response to the Control signal carried from the microcontroller 105 via the interface 100. The "insert-place" bit insertion state machine is set to insert the correct number of off-site bits for the selection of the appropriate code rate in response to the loaded registration information. Similarly, the Viterbi synchronization network 50 is also configured appropriately using this information. After insertion of "apart-place" bits, a fixed base code rate of 1/2 is taken out of unit 50. This means that the various code schemes shown in Table II are all decoded using a single decoder Viterbi 60 that operates in the fixed base code regime (1/2). The "apart-place" bits inserted in the unit 50 are identified within the Viterbi decoder 60. The information gained from this "apart-place" bit identification allows the Viterbi decoder algorithm to decode the information correctly. The resulting output of the Viterbi decoder 60 is provided to the multiplexer 65. In a satellite input signal configuration, the output of the Viterbi decoder 60 is provided to a symbol to byte mapper 70 by the multiplexer 65 in response to the control signal from the interface 100. The mapper 70 converts a single bit output of the Viterbi decoder 60 into an 8-bit mapped information byte. Alternatively, in the cable signal input configuration, the differentially decoded output of the unit 45 is provided to the mapper 70 by the multiplexer 65 in response to the status of the Control signal. In addition, in the cable input signal configuration, the function of the mapper 70 varies depending on whether a 64 or 256 dot symbol constellation is selected. If a constellation of 64 quadrature amplitude modulation points is selected, the mapper 70 converts a 6-bit symbol code for each of the 64 constellation points into an 8-bit byte of mapped information. In contrast, in the 256-point quadrature expansion modulation constellation configurations, the mapper 70 converts an 8-bit symbol code for each of the 256 constellation points into an 8-bit mapped information byte. The transformation of the mapping of symbols to bytes can be varied depending on the constellation of symbols chosen and the requirements of output bytes of the system. The mapped information output of the mapper 70 is provided to the synchronization unit 75 and the memory 95 for further processing. This output of mapped information is interleaved information. That is, the information has been arranged in a prescribed sequence before transmission. The purpose of the interleaving operation is to disseminate or disperse information over time in a previously determined sequence, so that a loss of information during transmission does not result in a loss of contiguous information. Instead of this, any loss of information is dispersed and therefore is more easily disguised or corrected. The synchronization unit 75 and the memory 95 together with the deinterleaver directs the generators 80, 85 and the multiplexer 90 constitutes a configurable deinterleaver function to restore the information to its original sequence. In DSS digital satellite system mode, a deinterleaver algorithm proposed by Remsey is used as described in "Realization of Optimum Interleavers" IEEE Transactions on Information Theory, vol. IT-15, May, 1970. In contrast, in the DVB mode the algorithm proposed by Forney as described in "Burst -Correcting Codes for the Classic Bursty Channel," IEEE Transactions on Communication Technology Vol. COM-19, October, 1971 The synchronization network 75 detects the synchronization words in the interleaved information signal and provides synchronized output signals at the beginning of the information. The synchronization words are not in themselves interspersed, but they occur at periodic intervals in time. To allow detection of synchronization words, the information identifying the synchronization words and the expected packet lengths is loaded into the registers within the unit 75. This information is provided by the microcontroller 105 via the interface 100 by means of the Control signal. The output synchronization signals from the unit 75 are provided to the address generators 80 and 85 to synchronize the address signals from the units 80 and 85 with the data interleaved from the mapper 70. The generated address signals are then applied to the memory 95 via the multiplexer 90. In the DSS digital satellite system mode, the multillexer 90 in response to the status of the Control signal, applies address signals from the generator 80 to the memory 95. In the video broadcast mode Directly, the multiplexer 90 applies direction signals from the generator 85 to the memory 95 in response to different Control signal status. The generator 80 is used in the DSS mode to implement the Ramsey deinterleaving function and the generator 85 is used in the DVB mode to implement the Forney deinterleaving function. These deinterleaving functions are implemented using logic state machines. Generators 80 and 85 produce a directed read-write sequence and associated memory control signals such as read, write and allow output = which are passed via multiplexer 90 to memory 95. The sequence of written addresses produced by the generators 80, 85 ensure that the information is read out of the memory 95 in the desired de-interleaved order. The deinterleaved output information resulting from the memory 95 is provided to the Reed-Solomon 110 decoder. Additional background information concerning the operation of the deinterleaving function is presented in the United States Patent Application Serial Number. : 08 / 346,950 from J. S Stewart. The Reed Solomon 110 decoder operates in all modes of the decoder 12 and decodes and corrects errors of the deinterleaved output information from the memory 95. The Reed-Solomon 110 decoder is configured by internal registers that are loaded in response to control from the interface 100. The information loaded within these registers configures the unit 110 to decode the lengths of the particular packets of the expected information in the deinterleaved output information from the memory 95. The information may also include other configuration parameters such as the number and type of parity bytes expected in the information, the number of bytes of error correction per packet, and parameters that select the function type of the Reed-Solomon decoder used, for example. The Reed Solomon decoded information output from the unit 110 is provided to both the wake-up device 115 and the multiplexer 120. In the DSS mode the multiplexer 120, in response to the control signal status, applies the decoded information from the unit 110 to the processor. output 125. In contrast, in both cable and satellite DBV modes, as shown in Table II, the decoded information of the unit 110 was first aroused by the wake-up device 115. In these modes, the multiplexer 120 responds to different control signal status and applies the output awakened from the unit 115 to the output processor 125. The output processor 125 processes the output information from the multiplexer 120 and provides output information for the output system. Figure 1. The processor 125 provides the necessary functions for the interface of the Output Information with other processing networks receiving video. These functions include shaping the output information at appropriate logic levels and providing a clock signal associated with the output information signal to facilitate interphase with other video receiving networks. Finally, the output information from the unit 125 is processed by the MPEG 130 compatible transport processor to provide synchronization and error indication information used in decompression of video information, although MPEG compatibility is not essential in a system. which employs the invention. The transport processor 130 also separates the information according to the type based on an analysis of the header information. The output of information from the processor 130 is decompressed by the MPEG 135 decompressor to provide suitable video information to encode it as an NTSC format signal by the NTSC 140 encoder. The decompressed output information encoded from the unit 140 is provided for the visual display processing circuits including a visual display device (not shown). In the embodiment of Figure 2, the demodulator 10 and the decoder 12 of Figure 1 are configured via the Control signal to process the DSS satellite signal format. The networks shown in Figure 2 perform the same functions as previously described with respect to Figure 1. In this, the DSS mode the automatic gain control cycle demodulator 10 (discussed in connection with Figures 5 and 6) uses the output of the QPSK divider via the multiplexer 40. The resulting controlled digital gain filtered video signal output from the unit 25 is then processed, decoded by Viterbi and corrected for errors by decoder units 50 and 60 12. In this DSS mode the unit 50 can be configured for 2/3 or 6/7 code schemes as defined above. The resulting decoded Viterbi output from unit 60 is passed via multiplexer 65 to symbol mapper byte. The output of the mapper 70 is deinterleaved by the units 75, 85, 90 and 95 which are configured, for example, for the Ramsey deinterleaver function. The deinterleaved output from the memory 95 is decoded by the Reed Solomon 110 decoder and passed via the multiplexer 120 to the output processor 125. The decoded, demodulated output from the processor 125 is processed by the networks 130, 135 and 140 as shown in FIG. describes in relation to Figure l. In the embodiment of Figure 3, the demodulator 10 and the decoder 12 of Figure 1 are configured via the Control signal to process the DVB satellite signal format. The networks shown in Figure 3 perform the same functions as those previously described in relation to Figure 1. In this DVB satellite mode, as in the DSS mode, the automatic gain control cycle of the demodulator 10 uses the output of the splitter. QPSK via multiplexer 40. The resultant digitized, filtered, gain-controlled video signal output from unit 25 is then processed, decoded by Viterbi and corrected for errors by decoder 12, units 50 and 60. In this DVB mode, unlike the DSS mode, the unit 50 can be configured for five different code modes (1/2, 2/3, 3/4, 5/6, or 7/8). The output decoded by Viterbi resulting from unit 60 is passed via multiplexer 65 to symbol mapper byte. The output of the mapper 70 is deinterleaved by the units 75, 80, 85, 90 and 95 that are configured for the function of the Forney deinterleaver. The deinterleaved output of the memory 95 is decoded by the Reed-Solomon 110 decoder, waked by the unit 115 and then passed via the multiplexer 120 to the output processor 125. The decoded, demodulated output from the processor 125 is processed by the networks 130, 135 and 140 as described in relation to Figure 1. In the embodiment of Figure 4, the demodulator 10 and the decoder 12 of Figure 1 are configured via the Control signal to receive the signal format of DVB cable. The networks shown in Figure 4 perform the same functions as those previously described in relation to Figure 1. In this DVB cable mode the automatic gain control cycle demodulator 10 uses the output of the quadrature amplitude modulation divider via the multiplexer 40. The quadrature amplitude modulation divider is configured for a 64 or 256 point constellation, depending on the input signal to the demodulator 10. The resulting information retrieved by the configuration of the selected divider at the output of the multiplexer 40 is decodes differently by unit 45 and is provided to multiplexer 65 of decoder 12. The decoded output of unit 45 is passed via multiplexer 65 to the byte symbol mapper 70. The output of mapper 70 is deinterleaved by units 75. , 80, 90 and 95 that are configured, for example, for the deinterleaver function of Forney. The deinterleaved output of the memory 95 is decoded by the Reed Solomon 110 decoder, waked by the unit 115 and passed via the multiplexer 120 to the output processor 125. The decoded output, demodulated from the processor 125 is processed by the networks 130. , 135 and 140 as described in relation to Figure 1. Both the functions of the demodulator 10 and the decoder 12 and the elements for configuring and selecting these functions can be implemented in a variety of ways. For example, instead of using ultiplexers for the selected functions, a configurable logical network could be used to perform these functions. Alternatively, a three-state logical buffer scheme could be used to select between separate function outputs instead of using multiplexers for selection. In addition, by applying the principles of the invention, the functions themselves can be varied to provide decoding and demodulation of other input signal formats.

Claims (22)

1. In a system for adaptively receiving and processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission modes, an apparatus comprising: an adaptive decoder (50, 60) to provide a decoded output as a function of a code regime selected from a plurality of code schemes, the decoded output being provided from an input signal encoded in different signal formats for different transmission modes; an adaptive deinterleaver (80, 85, 90) for deinterleaving the decoded output according to a deinterleaver function selected from a plurality of deinterleaver functions, wherein the adaptive deinterleaver is configured with the selected deinterleaver function, - and an output signal processor (125) to process deinterleaved output information.

2. An apparatus according to claim 1, wherein the decoder is a Viterbi adaptive decoder configured with a decoding function selected to decode the input signal.

3. An apparatus according to claim 1, wherein the output processor includes a wake-up device (115) to wake up the de-interleaved output information and the deinterleaved output information bypasses the wobbler when the input signal has a predetermined format.

An apparatus according to claim 1, further including a demodulator (10) for demodulating a modulated video input signal to provide the input signal encoded in different signal formats.

5. In a system for adaptively receiving and processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission, the apparatus comprises: an adaptive decoder (50, 60) to provide a decoded output as a function of a code regime selected from a plurality of code regimes; an adaptive deinterleaver (80, 85, 90) for deinterleaving the decoded output according to a deinterleaver function selected from a plurality of deinterleaver functions; and an output signal processor (125) for processing deinterleaved output information where the adaptive decoder deviates when the encoded video signal has a predetermined format.

6. An apparatus according to claim 5, further including a differential decoder (45) for providing a differentially decoded output as the first decoded output when the encoded video signal has that predetermined format.

The apparatus according to claim 4, wherein the demodulator demodulates a quadrature amplitude modulation video input signal.

The apparatus according to claim 1, further including an adaptive byte mapper (70) for selectively mapping information to be deinterleaved as a function of the different signal formats and different signal constellations of the input signal .

The apparatus according to claim 7, wherein the demodulates a quadrature phase change manipulation video input signal.

The apparatus according to claim 1, wherein the adaptive decoder and the adaptive deinterleaver are automatically configured to be compatible with the format of the encoded video signal in response to an error estimate in the deinterleaved output information.

11. The apparatus according to claim 1, further including an adaptive error processor (110) for correcting errors in the deinterleaved output information, adapting the error processor between different signal formats by changing at least one of: (a) type of error function, (b) length of error correction code, and (c) length of information packet.

The apparatus according to claim 11, wherein the adaptive error processor adapts between different signal formats by adapting the parity information in the deinterleaved output information.

The apparatus according to claim 11, wherein the adaptive error processor is a Reed-Solomon decoder.

14. In a system for adaptively receiving and processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission modes, the apparatus comprises: an adaptive decoder (50, 60) to provide a decoded output as a function of a code regime selected from a plurality of code schemes; the decoded output being provided from an encoded input signal in different signal formats for different transmission modes; an adaptive error decoder (110) for detecting and correcting errors in the decoded output, adapting the error decoder between different signal formats by changing at least one of: (a) type of error function, (b) code length of error correction and (c) information packet length, - and an output signal processor (125) to process the error corrected information.

15. The apparatus according to claim 14, wherein the adaptive error decoder is a Reed-Solomon decoder.

16. In a system for adaptively receiving and processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission modes, the apparatus comprises: an adaptive deinterleaver (80, 85, 90) for deinterleaving the decoded output according to a deinterleaver function selected from a plurality of deinterleaver functions; and an adaptive error decoder (110) for detecting and correcting errors in the decoded output, adapting the error decoder between different signal formats by changing at least one of: (a) type of error function, (b) code length of error correction and (c) length of information packet; and an output signal processor (125) for processing the error corrected information.

The apparatus according to claim 16, wherein the function of the adaptive error decoder is a Reed-Solomon function.

18. The apparatus according to claim 16, wherein the adaptive deinterleaver is configured with the selected deinterleaving function.

19. A method for adaptively processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission modes, comprising: adaptively decoding an input signal as a function of a code rate selected from a plurality of code schemes to provide a decoded output, the input signal being encoded in different signal formats for different transmission modes; selecting a deinterleaving function among a plurality of deinterleaving functions; configure the adaptive deinterleaver with the deinterleaver function; adaptively deinterleaving the decoded output using the selected deinterleaver function, and processing the deinterleaved information.

20. A method for adaptively processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission modes, comprising the steps of: selecting a code regime from a plurality of transmission modes; code, - adaptively decoding an encoded input signal in different signal formats for different transmission modes as a function of the selected code rate to provide a decoded output; detecting errors adaptively in the decoded output; Adaptively correct errors in the decoded output by changing at least one of: (a) type of error function, (b) length of error correction code, -, and (c) length of information packet, - and process information corrected for errors.

21. A method for adaptively processing a video signal encoded in one of a plurality of different formats suitable for satellite, terrestrial or cable transmission modes, comprising the steps of: selecting a deinterleaver function from a plurality of deinterleaver functions, - de-interleaving the decoded output using the deinterleaver function; detect errors in the deinterleaved output of different signal formats; adaptively correcting an error in the de-interleaved output of different signal formats by changing at least one of: (a) type of error function, (b) length of error correction code, and (c) length of information packet; and process the corrected information of errors.

22. A method according to claim 21 further including the step of configuring the adaptive deinterleaver with the selected deinterleaver function.