HK1095666A - Integrated circuit package having an inductance loop formed from a multi-loop configuration - Google Patents

Description

Integrated circuit package having an inductor loop formed from a multi-loop structure

Technical Field

The present invention relates generally to integrated circuits and, more particularly, to an integrated circuit package having an inductor loop formed by at least one input/output pin of the package. The invention also relates to a system that is at least partially controlled by the encapsulated inductor loop.

Background

One constant goal of circuit designers is to reduce the size of integrated circuits. This goal is driven by the ever-smaller market demand for consumer electronics, communication devices, and display systems, among others. However, there are a number of obstacles that prevent this goal from being achieved, one of which is discussed below.

Many integrated circuits are not stand-alone devices. To ensure proper operation, these circuits must therefore be connected to one or more external components through connections that do not involve the use of IC package input/output pins. As shown in fig. 1, this is achieved, for example, by connecting the integrated circuit chip 1 to an off-package component 2 using wire bonds 3. The need to establish an off-package connection increases the cost and complexity of the manufacturing process and is therefore considered highly undesirable. These connections also expose the integrated circuit to an increased risk of damage caused by external influences, which leads to reduced reliability and performance.

One conventional integrated circuit requiring an out-of-package connection is commonly used in frequency synthesizers for mobile communication devices such as cellular telephones. Because the phase noise specifications are very stringent in these devices, the voltage controlled oscillator in the phase locked loop used to generate the frequency is usually based on some resonant structure. Ceramic resonators and LC tank circuits are common examples. Although the implementation details of LC tank oscillators vary, typical resonant structures include an inductor in parallel with a fixed capacitor (C) and a variable capacitor (Cx). Without any loss, the energy is at frequency f_out＝(1/2π)〔L(C+C_x)〕^-1/2Passing between the heater and the inductor, the inductance value L is selected to control the operating bandwidth of the device.

In an integrated circuit comprising the aforementioned frequency synthesizer, the inductor for bandwidth selection purposes is provided outside the package (i.e. mounted on the circuit board). The use of off-package or circuit board mounted inductors increases system cost. Furthermore, connection problems may occur between the package and the circuit board, which adversely affects the reliability and performance of the PLL circuit.

Attempts have been made to overcome the deficiencies of these conventional devices. One approach disclosed in US patent US6,323,735 is to form the inductor entirely within an integrated circuit package containing the phase-locked loop circuit. This is accomplished by using wires that connect pads on the IC chip to the same pads on the package substrate. The connection between the pad and the wire forms an inductive loop that controls the operating frequency band of the PLL circuit. Multiple pads may be included on the package substrate to form inductor loops of different lengths. The inductor loop is then selectively activated to change the operating frequency.

The method described in the' 735 patent is undesirable for at least two reasons. First, to completely form the inductor loop within the IC package, the package substrate must be formed to include pads spaced from the input/output package pins. The need to form these special pads adds cost and complexity to the manufacturing process. Second, to accommodate the pads, the substrate of the integrated circuit must be enlarged, resulting in more circuit board consumption. These results are disadvantageous for the goals of increasing integration and miniaturization.

Another approach disclosed in "Wireless CMOS Frequency synthesis" by Craninckx discloses a self-contained integrated circuit package containing an inductor loop. Such inductor loops are formed by connecting bonding wires between bonding pads on the IC chip and corresponding input/output pins of the IC package. The input/output pins are then connected by third wire bonds. While this approach does not require the formation of dedicated pads on the package substrate, it has at least two drawbacks that make it undesirable. First, as in the' 735 patent, wire bonds are used to connect input/output pins. As noted previously, these weld lines are susceptible to damage during manufacture and/or use. Second, input/output pins connected by third wire bonds are located on opposite sides of the package. As a result, the third wire must pass through the IC chip. This is undesirable because the wires may short certain portions of the chip circuitry and introduce noise and other interference effects that substantially degrade chip performance.

Based on the foregoing considerations, it is apparent that there is a need for an integrated circuit package that is more economical than conventional IC packages and requires fewer manufacturing processing steps, and that is also less susceptible to damage and noise that degrades the reliability and performance of the chip circuitry and the host system of the chip. There is also a need for an integrated circuit package that is independent at least with respect to the connection of the inductor loop to the chip and by which at least one of the aforementioned advantages can be realized.

Disclosure of Invention

It is an object of the present invention to provide an integrated circuit package that is more economical and requires fewer manufacturing process steps than conventional IC packages.

It is a further object of this invention to provide such an integrated circuit package that is less susceptible to damage and noise that degrades the reliability and performance of the chip circuitry and the host system of the chip.

It is a further object of the present invention to provide an integrated circuit package that is independent at least with respect to the connection to the inductor loop of the IC chip and by which at least one of the aforementioned advantages can be achieved.

It is another object of at least one embodiment of the invention to achieve one or more of the foregoing objects by forming an inductor loop from a plurality of sub-loops, such sub-loops increasing the effective inductance of the loop by an amount proportional to the sum of the lengths of the sub-loops.

It is another object of the present invention to provide an integrated circuit package that does not require dedicated bonding pads formed on the package substrate for forming an inductor loop connected to the chip.

It is another object of the present invention to achieve one or more of the aforementioned objects by forming an inductor loop formed by at least one input/output pin of a package.

It is a further object of the invention to provide a system that is at least partially controlled by an integrated circuit package according to any of the preceding types.

These and other objects and advantages of the present invention are achieved by providing a semiconductor package including an integrated circuit chip and an inductor loop connected in a self-contained manner within the package. This independent connection is achieved by forming a loop from at least one (and preferably a plurality of) sub-loops. This can be achieved as follows: first and second conductors are connected between a first pad on the chip and a first input/output pin of the package, and third and fourth conductors are connected between a second pad on the chip and a second input/output pin of the package. A fifth conductor connects the first and second input/output pins. This fifth conductor may comprise a metallization layer comprised in a sub-surface layer of the package or on the surface of the substrate. The first and second input/output pins may be adjacent pins within the package, or the pins may be separated by at least a third input/output pin. The first to fourth conductors are preferably bonding wires.

According to another embodiment, the semiconductor package includes an integrated circuit chip and an inductor loop connected in a separate manner within the package. Such an inductor loop is formed by first and second conductors connecting a first pad on the chip to a first input/output pin of the package and third and fourth conductors connecting a second pad on the chip to a second input/output pin of the package. To implement the multi-loop structure, the first and second input/output pins are adjacent and in contact with each other within the package. Further, the first to fourth conductors may be bonding wires.

According to another embodiment, a semiconductor package includes an integrated circuit chip and an inductor loop connected in a separate manner within the package. Such an inductor loop includes first and second conductors connecting a first pad on the chip to a first input/output pin of the package and third and fourth conductors connecting a second pad on the chip to a second input/output pin of the package. To implement such a loop, the first and second input/output pins are made to have an integral structure. Further, the first to fourth conductors may be bonding wires.

According to another embodiment, a semiconductor package includes an integrated circuit chip and an inductor loop connected in a separate manner within the package. Such an inductor loop includes first and second conductors connecting a first pad on the chip to a first input/output pin of the package and third and fourth conductors connecting a second pad on the chip to a second input/output pin of the package. To implement such a loop, one or more bonding wires are included to connect the first and second input/output pins. In addition, the first to fourth conductors may be bonding wires.

The invention also includes an oscillator circuit comprising an active oscillator having two output nodes, an inductor loop coupled to the output nodes, and at least one capacitive circuit coupled to one of the output nodes. The capacitive circuit includes a capacitor, a resistor, and a first switch, wherein the resistor provides a bias voltage to the capacitor when the first switch is open, and the first switch couples and decouples the capacitor to the output node of the active oscillator. The active oscillator and the capacitive circuit are preferably included in a semiconductor package that includes an integrated circuit chip.

The inductor loop includes first and second conductors connecting a first pad on the chip to a first input/output pin of the package, at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, and a fifth conductor connecting the first input/output pin to the second input/output pin. The first, second, third and fourth conductors may be bonding wires, and the fifth conductor may comprise a metallization layer on or within a substrate surface of the package. Alternatively, the fifth conductor may comprise at least one bonding wire connecting the first input/output pin to the second input/output pin, and in a variant the fifth conductor comprises at least two bonding wires. The first and second input/output pins may be adjacent or separated by a third input/output pin. In other embodiments, the oscillator circuit of the present invention includes other embodiments of the inductor loop described above.

Drawings

Fig. 1 is a diagram illustrating a conventional integrated circuit package that is not self-contained.

Fig. 2 is a diagram showing a semiconductor package according to a first embodiment of the present invention.

Fig. 3(a) and 3(b) are diagrams illustrating an example of how the metallization layers in the semiconductor package of the first embodiment of the present invention are formed relative to one or more intermediate input/output pins of the package.

Fig. 4 is a diagram illustrating another manner in which a metallization sub-layer may be formed in a semiconductor package according to the first embodiment of the present invention.

Figure 5 is a diagram illustrating one manner in which input/output pins may contact the metallization sub-layer of figure 4.

Fig. 6 is a diagram showing a semiconductor package according to a second embodiment of the present invention.

Fig. 7 is a diagram showing a semiconductor package according to a third embodiment of the present invention.

Fig. 8 is a diagram showing a semiconductor package according to a fourth embodiment of the present invention.

Fig. 9 is a diagram of a voltage controlled oscillator according to an embodiment of the present invention.

Fig. 10 is a diagram showing a first variation of the voltage controlled oscillator of fig. 9.

Fig. 11 is a diagram showing a second variation of the voltage controlled oscillator of fig. 9.

Fig. 12 is a diagram showing a third variation of the voltage-controlled oscillator of fig. 9.

Detailed Description

In one aspect, the present invention is a semiconductor package having an integrated circuit chip and an inductor loop connected in a self-contained manner within the package. The present invention is also a system that is at least partially controlled by the inductor loop of the semiconductor device described above. The system may be a communication system or other type of system in which an inductive loop is used to set the transmitter and/or RF carrier frequency. Various embodiments of the invention are discussed individually below.

Fig. 2 shows a semiconductor package according to a first embodiment of the present invention. The package includes an integrated circuit chip 10 mounted on or within a package housing 11. The housing includes a substrate 12 for supporting the chip and a plurality of input/output (I/O) pins 13 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown). The substrate may be any type of substrate known in the art, and the I/O pins may be connected to the chip using any of a variety of conventional connection techniques, including (but not limited to) wire bonds and solder bumps. Examples of this type of package include lead frame packages, Ball Grid Array (BGA) packages (including ball grid array packages using Tape Automated Bonding (TAB), Pin Grid Array (PGA), thin low profile package (TSOP), low profile J-lead package (SOJ)); small Outline Package (SOP), Chip Scale Package (CSP), and the like.

The I/O pins may take any of a variety of forms. For example, the pins shown are external package leads disposed along the periphery of the package substrate. However, pins may be formed in other ways, if desired, including (but not limited to) conductive vias extending through the package substrate to solder bump connections provided on opposite sides of the package.

The semiconductor package also includes a separate inductor loop 20 located within the package. The inductor loop is formed of multiple loops using multiple conductors. A first sub-loop is formed by connecting first and second conductors 22 and 23 between a first pad 24 on the chip to a first input/output pin 26 of the package. A second sub-loop is formed by connecting third and fourth conductors 32 and 33 between a second pad 34 on the chip to a second input/output pin 36 of the package. Whether a second sub-ring is included is optional. For example, a single conductor may be used to connect pad 34 and pin 36. Alternatively, other sub-loops may be formed by connecting three or more conductors between pad 24 and pin 26 or between pad 34 and pin 36 or both. The first to fourth conductors are preferably bonding wires.

To implement the loop, a fifth conductor is included to connect the first and second input/output pins. The fifth conductor includes a metallization layer 40 that may be formed in a variety of ways. One approach involves forming layer 40 on the upper surface 50 of the package substrate. Such a layer is preferably formed so that the ends juxtapose pins 26 and 36, respectively, as shown in fig. 2. The metallization layer may be formed using any well-known technique including, but not limited to, ion implantation and plasma etching. In addition, the metallization layer is preferably formed on the substrate before the integrated circuit chip is mounted within the package. As a variant, the metallization layer may be formed before the mounting of the chip or even before the I/O pins are formed on or connected to the substrate. In the latter case, the first and second I/O pins may be connected after its formation or formed on top of the metallization layer, thereby implementing an inductor loop.

Once the inductor loop is formed, it may also be used to control one or more circuits on the integrated circuit chip. For example, if the integrated circuit includes a phase locked loop, the inductance value of the loop may be used to set the frequency band or output frequency of this circuit. Alternatively, the length of the loop may be used to set other operating parameters of the chip. The particular application of the inductor loop of the present invention may vary, for example, depending on the parameters set and the particular function to be performed by the integrated circuit.

The inductance value of the loop depends on its total length. This length can be set in various ways to achieve the desired inductance value. For example, the length of the conductor may be set to achieve the desired total loop length. Additionally or alternatively, a different number of sub-loops may be included between respective pins and pads until a desired loop length is reached, thereby achieving a desired inductance value. Preferably, the input/output pins connected in the ring are adjacent to each other on the circuit package. However, the pins may not be adjacent if desired. In this case, the distance between the pins connected in the loop has an effect on the loop length, which in turn corresponds to the desired inductance value.

Fig. 3(a) and 3(b) provide examples of this latter variation of the invention. In both figures, the intermediate pins 65 and 70 are located between the pins 46 and 56 connected in the inductor loop. In fig. 3(a), the surface metallization 52 passes under the intermediate pins. These pins are preferably not connected to the chip. Otherwise, the metallization layer may short circuit the circuit connected to the pin. In fig. 3(b), the surface metallization layer 62 is arranged along a path that avoids contact with the intermediate pins 72 and 73 to connect the pins 74 and 75. As a result, the intermediate pin can be connected to the chip circuit without any short-circuit effect. According to another variant, the length of the inductor loop can be varied using a combination of the aforementioned techniques.

Fig. 4 shows another way of forming the metallization layer is to include it in a sub-layer of the package substrate (below the surface layer). In this figure, layer 80 is a surface layer of the substrate, layer 81 is an underlying metallization layer, which may or may not be directly adjacent to the surface layer, and conductive vias 82 and 83 connect pins 85 and 86 to the metallization layer. As a variation of the conductive vias, at least one (and preferably two) of the input/output pins connected in the ring have protruding portions 95 and 96 (fig. 5) that contact the underlying metallization layer, respectively. Fig. 5 shows a cross-section of a variation of the invention, in which for illustrative purposes only input/output pins 95 are shown, which are in contact with the underlying metallization layer 96 by way of projections 97.

Fig. 6 shows a semiconductor package according to a second embodiment of the present invention. Such a package includes an integrated circuit chip 110 mounted on or within a package housing 110. The housing includes a substrate 112 for supporting the chip and a plurality of input/output (I/O) pins 113 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown). The substrate may be formed of one material and the I/O pins may be formed and connected in any of the ways indicated in the discussion of the first embodiment.

The semiconductor package also includes a separate inductor loop 120 within the package. The conductor loop has a multi-loop structure in which a first sub-loop is formed by connecting first and second conductors 122 and 123 between a first pad 124 on the chip to a first input/output pin 126 of the package. A second sub-loop is formed by connecting third and fourth conductors 132 and 133 between a second pad 134 on the chip to a second input/output pin 136 of the package. The first to fourth conductors are preferably bonding wires. Unlike the first embodiment, at least one additional wire bond 40 is included to connect pins 126 and 136. The connections between these pins ensure that the loop is completed and that a desired inductance value based on the total length of the loop is established. Once the inductor loop is formed, it can be used to control one or more circuits on the integrated circuit chip.

The foregoing embodiments may be varied in many ways. For example, one sub-ring may be replaced by a single conductor. Alternatively, more than one sub-ring may be connected between pad 124 and pin 126 or between pad 134 and pin 136, or both. In addition, the number of sub-rings connected between each pad pin pair may be different from each other.

Fig. 7 shows a semiconductor package according to a third embodiment of the present invention. Such a package includes an integrated circuit chip 150 mounted on or within a package housing 160. The housing includes a substrate 162 for supporting the chip and a plurality of input/output (I/O) pins 163 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown). The substrate may be formed of one material and the I/O pins may be formed and connected in any of the ways indicated in the discussion of the first embodiment.

The integrated circuit package also includes a separate inductor loop 180 within the package. The inductor loop preferably comprises the following sub-loops. A first sub-loop is formed by connecting conductors 182 and 183 between a first pad 184 on the chip to a first input/output pin 186 of the package. A second sub-loop is formed by connecting conductors 192 and 193 between a second pad 194 on the chip to a second input/output pin 196 of the package. These conductors are preferably bonding wires. Unlike the first embodiment, the pins connected within the inductor loop are adjacent and in contact with each other. The connections between these pins ensure that the loop is completed and that a desired inductance value based on the total length of the loop is established. Once the inductor loop is formed, it can be used to control one or more circuits on the integrated circuit chip.

The foregoing embodiments may be varied in many ways. For example, one sub-ring may be replaced by a single conductor. Alternatively, more than one sub-ring may be connected between pad 184 and pin 186, or between pad 194 and pin 196, or both. In addition, the number of sub-rings connected between each pad-pin pair may be different from each other.

Fig. 8 shows a semiconductor package according to a fourth embodiment of the present invention. Such a package includes an integrated circuit chip 200 mounted on or within a package housing 210. The housing includes a substrate 212 for supporting the chip and a plurality of input/output (I/O) pins 213 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown). The substrate may be formed of one material and the I/O pins may be formed and connected in any of the ways indicated in the discussion of the first embodiment.

The integrated circuit package also includes a separate inductor loop 220 within the package. The inductor loop preferably comprises a plurality of sub-loops. A first sub-loop is formed by connecting conductors 222 and 223 between a first pad 224 on the chip to an input/output pin 226 of the package. A second sub-loop is formed by connecting conductors 232 and 233 between a second pad 234 on the chip to a second input/output pin 236 of the package. These conductors are preferably bonding wires. Unlike the first and second embodiments, the pins connected within the inductor loop have an integral structure; that is, they are formed in one continuous section, although they each have different leads 240 and 241 for connection to a printed circuit board or other external circuit. Connecting the first and second conductors to the pins ensures that the loop is realized and that a desired inductance value based on the total length of the loop is established. Once the inductor loop is formed, it can be used to control one or more circuits on the integrated circuit chip.

A semiconductor package according to any of the foregoing embodiments may be used in any of a wide variety of applications. One exemplary application is in a communication system where the inductor loop is used to set one or more parameters such as, but not limited to, an operating frequency. An exemplary embodiment of a voltage controlled oscillator of the type usable in such a communication system will be described below.

Voltage controlled oscillator

One exemplary application of the present invention relates to the formation of an integrated Voltage Controlled Oscillator (VCO) of the type disclosed in pending U.S. patent application No. 10/443,835 (attorney docket No. GCTS-0024), the entire contents of which are incorporated herein by reference. A VCO may be included in a phase locked loop to provide frequency signals for a variety of well known purposes, but those skilled in the art will appreciate that such VCO applications are by no means the only applications of the present invention. As highlighted above, the various embodiments of the present invention may be used in any practical circuit requiring an inductive element. An exemplary embodiment of a VCO application according to the present invention will now be discussed.

Because the phase noise specifications in mobile phone applications are so stringent that the allowable types of VCOs are limited and LC oscillators are typically used. The LC oscillator includes a resonant tank circuit and a few active devices to compensate for energy losses in the tank circuit. Since the tank circuit is one type of band pass filter, the phase noise performance of the LC oscillator is better than other types of oscillators.

The nominal frequency of the LC oscillator may be expressed according to the following equation:

where f is_VCOL is the inductance and C is the capacitance, which is the nominal frequency of the VCO. From this equation, it is apparent that there are at least two ways in which the output frequency of the VCO can be controlled. One involves changing the capacitor (C) of the oscillator circuit and the other involves changing the inductance value (L). A voltage controlled oscillator formed in accordance with the present invention is based on any one or more of the inductor loop embodiments shown in fig. 2-8, either alone or with additional adjustments in capacitance value-oneThe inductance value is set.

Fig. 9 illustrates an oscillator circuit 600 according to an embodiment of the invention. This circuit includes an oscillator 610 and at least one conditioning circuit 620 operably coupled to the oscillator 610. The adjustment circuit includes a bias resistor 622, a reactive element 624 (e.g., a capacitor), and a first switch 626. The first switch 626 selectively couples and decouples the reactive element 624 from the oscillator circuit 600. The bias resistor 622 provides a bias voltage V when the first switch is open_AThe reactive element 624 is given such that the reactive element 624 has a bias.

Bias voltage V, discussed in detail below_AThe reactive element may be delivered in various configurations. For example, bias switch 628 may be located between bias resistor 622 and bias voltage V_AIn the meantime. The bias switch 628 selectively couples the bias resistor 622 to the bias voltage when the reactive element 624 is decoupled by the first switch 626. The bias switch 628 couples the bias resistor 622 to the bias voltage V when the first switch 626 couples the reactive element 624 to the oscillator circuit 600_AAre selectively decoupled. Alternatively, the bias resistor 622 may be sized (e.g., high resistance value) to bias the voltage V_AMay be constantly coupled to a bias resistor and bias voltage V when first switch 626 is closed_AThe operating characteristics of the regulating circuit are not substantially changed.

Bias voltage V_AMay be connected to ground, supply or common mode voltage of the oscillator output. In addition, a bias voltage V_AMay be variable and may be selected from a range of ground voltages to supply voltages. In addition, the switches 626 and 628 may be semiconductor switching devices, such as transistors or the like.

As shown in fig. 9, the regulating circuit 610 is part of the resonant circuit 630. Those of ordinary skill in the art will appreciate that resonant circuit 630 may contain additional components such as inductors, capacitors, and resistors. When the first switch 626 is open or closed, the reactive element 624 is removed from or added to the resonant circuit 630, respectively. Accordingly, the first switch 626 may change the characteristics of the resonant circuit 630, and thus the frequency of the VCO. In addition, additional regulation circuitry may be added to the resonant circuit 630 to increase the range of control. Furthermore, those of ordinary skill in the art will appreciate that the regulating circuit of fig. 9 may be used in either single-ended or differential type oscillators, as increased tuning range and improved phase noise performance are advantageous for both types of oscillators.

Fig. 10-12 show variations of the oscillator circuit of fig. 9, each type including first and second cascaded regulator stages coupled on either side of the oscillator active circuit and an inductor loop coupled to the cascaded regulator stages. These variations are discussed below.

Fig. 10 is a schematic diagram showing a first modification of the voltage-controlled oscillator of the present invention. Such a variation preferably includes an active oscillator circuit 702, for example corresponding to circuit 610 in fig. 9. The circuit in fig. 10 has a differential configuration with output nodes OUT706 and OUTB 708. The inductor 704 is preferably coupled to the output nodes OUT706 and OUTB 708. Two or more circuits having capacitors 722 coupled in series with switches 718 are also coupled to OUT 706. Capacitor 722 is coupled to output node 706 and switch 718. Switch 718 is preferably a transistor switch coupled to a reference voltage, which may be ground as shown in fig. 9. In addition, the circuit preferably includes a series coupled resistor and switch such as an explicit resistor 710 coupled in series with a transistor switch 714. Explicit resistor 710 is coupled at one end to a common node of capacitor 722 and transistor switch 718, transistor switch 714 is coupled at the other end of resistor 710, and a bias voltage V_AIn the meantime.

Similar components and connections are preferred for the output node OUTB 708. For example, a capacitor 722 is preferably coupled in series with the transistor switch 720, with the other end of the capacitor 722 coupled to the output node OUTB 708. Further, one terminal of transistor switch 720 is coupled to ground. Further, there is preferably an explicit resistor 712 coupled in series with a transistor switch 716 such that resistor 712 is coupled to a common node of capacitor 722 and transistor switch 720, with one terminal of transistor switch 716 coupled to a bias voltage V_A. One of ordinary skill in the artThe person will understand that the capacitors 722 have the same or different values. Likewise, the associated resistors and switches have the same or different values, as determined by the specific design requirements of each application.

The operation of the circuit shown in fig. 10 is described below. Preferably, the values of resistors 710 and 712 are determined or optimized to obtain the best phase noise performance in the off state. Since the resistance values are typically high (e.g., over a few K Ω), a low on-resistance of the transistor switches 714 and 716 is not required. Thus, the size of the transistor switches 714 and 716 can be very small. In addition, the additional parasitic capacitance of the transistor switches 714 and 716 is small, and since the resistors 710 and 712 are designed to cover most of the resistance in the off state, the characteristic variations of the transistor switches 714 and 716 are not severe. Bias level V_AThe common level in the off-state is determined and can have any value from ground to the supply voltage. Thus, the bias level V_ACan be generated from a simple bias generator such as a resistor divider. V_AIt may also be a ground voltage or a supply voltage itself.

Fig. 11 is a schematic diagram showing a second modification of the voltage-controlled oscillator of the present invention. This variation 800 preferably includes an active oscillator circuit 802, for example, corresponding to circuit 610 in fig. 9. The circuit in fig. 11 has a differential structure with output nodes OUT 806 and OUTB 808. Inductor 804 is preferably coupled between output nodes OUT 806 and OUTB 808. A series circuit comprising a capacitor 822, a resistance shown as an explicit resistor 810, and a switch 814 or the like (e.g., a transistor) is preferably coupled to the output node OUT 806 at one end of the capacitor 822 and one end of the transistor switch 814, which are opposite ends of the series circuit.

In addition, a switch 818 or the like (e.g., a transistor) is preferably coupled between a reference voltage, which is a ground voltage, and a common node of the capacitor 822 and the resistor 810. Similar circuitry may be coupled to the output node OUTB 808. For example, a series circuit including the capacitor 822, the resistor 812, and the transistor switch 816, which is provided between one terminal of the capacitor 822 and one terminal of the transistor switch 816, is coupled to the output node OUTB 808 through one terminal of the capacitor 822 and one terminal of the transistor switch 816. Preferably, transistor switch 820 is coupled between ground and the common node of capacitor 822 and resistor 812. One of ordinary skill in the art will appreciate that the capacitors 822 may have the same or different values. Likewise, the associated resistors and switches may have the same or different values, as determined by the specific design requirements of each application.

In the embodiment shown in fig. 11, no additional bias circuit is required in the off state. In contrast, the common mode voltage of the active circuit in the LC oscillator provides an appropriate DC bias to the other end of the capacitor that is not connected to the oscillator output. Further, in VCO 800, the size of transistor switches 814 and 816 may be very small. Therefore, the additional parasitic capacitance of the transistor switches 814 and 816 is not severe.

Fig. 12 is a schematic diagram showing a third modification of the voltage-controlled oscillator of the present invention. As shown in fig. 12, the VCO preferably includes an active oscillator circuit 902, for example corresponding to circuit 610 in fig. 9. This circuit has a differential structure with output nodes OUT 906 and OUTB 908. The inductor 904 is preferably coupled between the output nodes OUT 906 and OUTB 908. Further, a capacitor 922 is preferably coupled in series with a switch 918 (e.g., a transistor), wherein the remaining terminal of the capacitor 922 is coupled to the output node OUT 906 and the remaining terminal of the transistor switch 918 is coupled to ground. Preferably, there is an explicit resistance, preferably coupled at the common node of capacitor 922 and transistor switch 918, and a bias voltage V_AWith resistor 910 in between.

Similar circuitry is preferably coupled to OUTB 908. For example, capacitor 922 is preferably coupled in series with transistor switch 920, with the remaining terminal of capacitor 922 coupled to output node OUT 908 and the remaining terminal of transistor switch 920 coupled to ground. Preferably, an explicit resistor 912 is coupled at the bias voltage V_AAnd the common node of the capacitor 922 and the transistor switch 920. One of ordinary skill in the art will appreciate that capacitor 922 may be usedTo have the same or different values. Likewise, the associated resistors and switches may have the same or different values, as determined by the specific design requirements of each application.

In the embodiment shown in fig. 12, the open switches (e.g., switches 814 and 816 in fig. 10) are eliminated, which reduces or limits the loss of performance. This is because the resistances of explicit resistors 910 and 912 are selected so that they do not significantly change the operating characteristics over the on-period of switches 918 and 920. One of ordinary skill in the art will appreciate that appropriate values for resistors 910 and 920 are determined empirically for a given oscillator design (e.g., capacitance, frequency range, etc.). The other terminals not coupled to the oscillator output preferably have a DC bias voltage substantially the same as the common mode voltage of the oscillator 902 when the switches 918 and 920 are opened to reduce capacitance.

In fig. 9-12, the voltage controlled oscillator may be formed on a chip that is preferably mounted in a separate semiconductor package constructed in accordance with any of the embodiments of the invention as shown in fig. 2-8. Thus, the packaged inductor loop can be used as a bias voltage to set the output frequency of the VCO. More specifically, the length of this loop may be formed to produce an inductance value (corresponding to any one or more of inductors 704, 804, and 904) that causes the VCO to output a desired frequency or operate within a desired frequency band.

For example, in one non-limiting but particularly advantageous application, the loop length may be formed to produce an inductance value of 1.3 nH. This causes the PLL incorporating the VCO to output a frequency of 1.98GHz, provided that the VCO is an RF 1-type (e.g., PCS) oscillator and the capacitance is 4.96 pF. Where the VCO is an RF 2-type (e.g., CDMA) oscillator with the same capacitance value, the loop length of the inductor may be formed to produce a value of 1.81nH, which is sufficient to produce an output transmission frequency from a PLL of 1.28 GHz. The manner in which the inductance value can be used to control the output frequency of the PLL is well known and may be implemented, for example, in the manner disclosed in US patent US6,323,735, the contents of which are incorporated herein by reference. The inductor loop is also used in conjunction with multiphase clock signals in a manner disclosed in more detail below.

As described below, a voltage controlled oscillator according to the present invention is advantageously used in a PLL circuit to generate a frequency (e.g., local oscillator signal) signal in a communication receiver. However, those of ordinary skill in the art will appreciate that the VCO of the present invention may be used in any other device that uses or may use a PLL or VCO. For example, these devices include receivers, transmitters, transceivers, wireless communication devices, base stations, or mobile devices (e.g., cellular phones, PDAs, pagers, etc.).

It is further noted that voltage controlled oscillators formed in accordance with the present invention have various advantages. For example, the tuning range of the PLL may be increased compared to conventional types of devices. Furthermore, the problems associated with the on and off states of the VCO tuning circuit may be substantially reduced or even eliminated. Further, the size of the transistor switch can be reduced, thereby promoting miniaturization.

One of ordinary skill in the art will also recognize that methods for tuning a device having an oscillator circuit are disclosed in the foregoing description. These methods include, for example, providing a bias voltage to the reactive element through a bias resistor such that the reactive element has the bias voltage when the first switch is open, coupling or decoupling the reactive element from the oscillator circuit using the first switch, and coupling the bias resistor to the bias voltage through a second switch. Further, the method may include opening the second switch if the first switch is closed and closing the second switch if the first switch is open. The method may be used in a wide variety of devices such as PLLs, receivers, transmitters, transceivers, wireless communication devices, base stations, and/or mobile devices.

Other modifications and variations of the present invention will be apparent to those of ordinary skill in the art in view of the foregoing description. Thus, while certain embodiments of the invention have been described in detail herein, it will be apparent that many modifications can be made without departing from the spirit and scope of the invention.

Claims (52)

1. A semiconductor package, comprising:

an integrated circuit chip; and

an inductor loop, comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of third and fourth conductors connecting a second pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor connecting the first input/output pin to the second input/output pin.

2. The semiconductor package of claim 1, wherein the first, second, third and fourth conductors are bonding wires.

3. The semiconductor package of claim 1, wherein the fifth conductor comprises a metallization layer having a substrate of the package.

4. A semiconductor package according to claim 3, wherein the metallization layer is on a surface of the substrate.

5. A semiconductor package according to claim 3, wherein the metallization layer is comprised in a sub-surface layer of the substrate.

6. The semiconductor package of claim 1, wherein the fifth conductor comprises at least one bonding wire connecting the first input/output pin to the second input/output pin.

7. The semiconductor package of claim 6, wherein the fifth conductor comprises at least two bonding wires.

8. The semiconductor package of claim 1, wherein the first input/output pin and the second input/output pin are adjacent pins.

9. The semiconductor package of claim 1, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

10. A semiconductor package, comprising:

an integrated circuit chip; and

an inductor loop, comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and in contact with each other.

11. The semiconductor package of claim 10, wherein the first, second, third and fourth conductors are bonding wires.

12. A semiconductor package, comprising:

an integrated circuit chip; and

an inductor loop, comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary structure.

13. The semiconductor package of claim 12, wherein the first, second, third and fourth conductors are bonding wires.

14. A semiconductor package, comprising:

an integrated circuit chip including a phase-locked loop; and

an inductor loop having a length corresponding to an output frequency of a phase locked loop, said inductor loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor connecting the first input/output pin to the second input/output pin.

15. The semiconductor package of claim 14, wherein the first, second, third and fourth conductors are bonding wires.

16. The semiconductor package of claim 14, wherein the fifth conductor comprises a metallization layer having a substrate of the package.

17. The semiconductor package of claim 16, wherein the metallization layer is on a surface of the substrate.

18. The semiconductor package of claim 16, wherein the metallization layer is included in a sub-surface layer of the substrate.

19. The semiconductor package of claim 14, wherein the fifth conductor comprises at least one bonding wire connecting the first input/output pin to the second input/output pin.

20. The semiconductor package of claim 19, wherein the fifth conductor comprises at least two bonding wires.

21. The semiconductor package of claim 14, wherein the first input/output pin and the second input/output pin are adjacent pins.

22. The semiconductor package of claim 14, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

23. A semiconductor package, comprising:

an integrated circuit chip including a phase-locked loop; and

an inductor loop having a length corresponding to an output frequency of a phase locked loop, said inductor loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and in contact with each other.

24. The semiconductor package of claim 23, wherein the first, second, third and fourth conductors are bonding wires.

25. A semiconductor package, comprising:

an integrated circuit chip including a phase-locked loop; and

an inductor loop having a length corresponding to an output frequency of a phase locked loop, said inductor loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary structure.

26. The semiconductor package of claim 25, wherein the first, second, third and fourth conductors are bonding wires.

27. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output node; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit comprising a capacitor, a resistor and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open, wherein said first switch couples and decouples the capacitor to the output node of said active oscillator, wherein the active oscillator and the capacitive circuit are both included in a semiconductor package comprising an integrated circuit chip, said inductive loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor connecting the first input/output pin to the second input/output pin.

28. The oscillator circuit of claim 27, wherein the first, second, third and fourth conductors are bonding wires.

29. The oscillator circuit of claim 27, wherein the fifth conductor comprises a metallization layer with a substrate of the package.

30. The oscillator circuit of claim 29, wherein the metallization layer is on a surface of the substrate.

31. The oscillator circuit of claim 29, wherein the metallization layer is included in a subsurface layer of the substrate.

32. The oscillator circuit of claim 27, wherein the fifth conductor includes at least one bond wire connecting the first input/output pin to the second input/output pin.

33. The oscillator circuit of claim 32, wherein the fifth conductor includes at least two bonding wires.

34. The oscillator circuit of claim 27, wherein the first input/output pin and the second input/output pin are adjacent pins.

35. The oscillator circuit of claim 27, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

36. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output node; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit comprising a capacitor, a resistor and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open, wherein said first switch couples and decouples the capacitor to the output node of said active oscillator, wherein the active oscillator and the capacitive circuit are both included in a semiconductor package comprising an integrated circuit chip, said inductive loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and in contact with each other.

37. The oscillator circuit of claim 36, wherein the first, second, third and fourth conductors are bonding wires.

38. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output node; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit comprising a capacitor, a resistor and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open, wherein said first switch couples and decouples the capacitor to the output node of said active oscillator, wherein the active oscillator and the capacitive circuit are both included in a semiconductor package comprising an integrated circuit chip, said inductive loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary structure.

39. The oscillator circuit of claim 38, wherein the first, second, third and fourth conductors are bonding wires.

40. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output node; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit comprising a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open, wherein said first switch couples and decouples the capacitor to the output node of said active oscillator, wherein the active oscillator and the capacitive circuit are included in a semiconductor package comprising an integrated circuit chip, said inductive loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor connecting the first input/output pin to the second input/output pin.

41. The oscillator circuit of claim 40, wherein the first, second, third and fourth conductors are bonding wires.

42. The oscillator circuit of claim 40, wherein the fifth conductor comprises a metallization layer with a substrate of the package.

43. The oscillator circuit of claim 42, wherein the metallization layer is on a surface of the substrate.

44. The oscillator circuit of claim 42, wherein the metallization layer is included in a subsurface layer of the substrate.

45. The oscillator circuit of claim 40, wherein the fifth conductor includes at least one bond wire connecting the first input/output pin to the second input/output pin.

46. The oscillator circuit of claim 45, wherein the fifth conductor includes at least two bonding wires.

47. The oscillator circuit of claim 40, wherein the first input/output pin and the second input/output pin are adjacent pins.

48. The oscillator circuit of claim 40, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

49. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output node; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit comprising a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open, wherein said first switch couples and decouples the capacitor to the output node of said active oscillator, wherein the active oscillator and the capacitive circuit are included in a semiconductor package comprising an integrated circuit chip, said inductive loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and in contact with each other.

50. The oscillator circuit of claim 49, wherein the first, second, third and fourth conductors are bonding wires.

51. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output node; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit comprising a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open, wherein said first switch couples and decouples the capacitor to the output node of said active oscillator, wherein the active oscillator and the capacitive circuit are included in a semiconductor package comprising an integrated circuit chip, said inductive loop comprising:

(a) first and second conductors connecting a first pad on a chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary structure.

52. The oscillator circuit of claim 51, wherein the first, second, third and fourth conductors are bonding wires.