HK1092532B - Memory bus checking procedure - Google Patents

Description

Memory bus checking procedure

Technical Field

The present invention relates generally to electronic memory cards and their use in host devices, and more particularly to a method of checking the electrical functionality of a data bus linking such a memory card with a host device.

Background

Memory cards are known in the art. For example, flash-based cards are small, packaged cards containing a large amount of non-volatile memory that can be removably inserted into a portable electronic device. Such memory cards are generally used for personal computers, notebook computers, personal digital assistants, mobile phones, and cameras in which a data storage device can be detached and replaced by another. In particular, the size of a "multi-media card" is small, but can currently store up to 128MB of data. The "multi media card" package has a seven pad serial interface and is easily integrated into a variety of host devices. The host device typically provides only one slot for insertion of a "multi-media card". That is because only one card/host can talk at a time. The host has a data processor, such as an ASIC (application specific integrated circuit) or a chipset operatively connected to the card slot. As disclosed by Cedar et al (WO02/15020), unique addresses are assigned to each inserted memory card as part of a system initialization routine. The unique Card Identification (CID) number is stored in a register in each card during manufacture. In order for the host processor to initially be able to address each card and, in turn, assign such addresses, the host commands all cards to transmit their CID simultaneously. Thereafter, a unique small address is assigned to each card inserted.

There are two main ways to affect the data rate between the memory and the host processor. One is the bus frequency and the other is the bus width. The data rate may also be affected by different timing methods, such as single-edge and double-edge data timing with rising/falling edges. With the technology known today, the bus width is obtained by checking the value from an internal register provided in the memory card.

It is advantageous and desirable to eliminate internal registers in the memory card for determining the width of the memory bus and the register checking process.

Disclosure of Invention

The present invention employs a memory bus checking process to determine the width of the memory bus. Preferably, during boot up, the host device sends a test bit pattern to the memory card inserted in the device slot and compares the test bit pattern with a response bit pattern provided by the memory card. Advantageously, the response bit pattern is the complement of the test bit pattern. By this simple procedure, the available data bus width can be determined. The available data bus width may be different from the maximum bus width of the host device or the bus width of the memory card. The maximum bus width of the host device may be greater than, less than, or equal to the bus width of the memory card.

If necessary, a second cycle of the bus checking process is performed to ensure that the bits do not remain at either '0' or '1'. Advantageously, the test bit pattern of the second cycle is the complement of the first bit pattern. By means of such a handshake process, the electrical functionality of the data bus can be verified. In addition, it is also possible to mix host devices of various data bus widths with memory cards of various data bus widths. With the present invention, it is no longer necessary to check the bus width value from an internal register located in the memory card.

According to a first aspect of the present invention, a method for checking the electronic functionality of a data bus between a first electronic module and a second electronic module operatively connected to the first electronic module is provided. The method comprises the following steps:

transmitting the first bit pattern to the second electronic module through the data bus;

generating a second bit pattern in the second electronic module according to the received first bit pattern; and

the second bit pattern is transmitted to the first electronic module over the data bus.

The method further comprises the following steps:

the received second bit pattern is compared to the first bit pattern to determine the available data bus width.

The second bit pattern has a predetermined relationship with the received first bit pattern in the second electronic module.

Preferably, each bit in the first bit pattern and the second bit pattern has a value of '0' or '1', and the second bit pattern is the complement of the received first bit pattern, such that a bit in the second bit pattern has a value different from the value of the corresponding bit in the received first bit pattern.

If the received second bit pattern has only one portion in which the pattern is complementary to a corresponding portion of the first bit pattern, the comparing step determines the available width of the data bus from the portion.

Method steps can also be performed in a second cycle, wherein the bit pattern transmitted to the second electronic module in the second cycle is the complement of the first bit pattern in the first cycle, and the response bit pattern sent back to the first electronic module in the second cycle also has a predetermined relationship to the bit pattern received by the second electronic module in the second cycle.

The second electronic module may be a memory card.

According to a second aspect of the invention, a software program in a first electronic module for checking the electronic functionality of a data bus between the first electronic module and a second electronic module is provided. The program includes:

first code for comparison

A first bit pattern provided to the second electronic module via the data bus

A second bit pattern received from the second electronic module in response to the first bit pattern received in the second electronic module, the second bit pattern having a predetermined relationship to the received first bit pattern; and

a second code determines an available bus width of a data bus that transfers data between the first electronic module and the second electronic module according to a predetermined relationship.

The program further includes third code for generating a first bit pattern.

The first code is also advantageously compared

A third bit pattern provided to the second electronic module via the data bus

A fourth bit pattern received from the second electronic module in response to a third bit pattern received in the second electronic module, wherein the third bit pattern is a complement of the first bit pattern and the fourth bit pattern has a predetermined relationship with the received third bit pattern to allow the second code to determine an available bus width of the data bus.

According to a third aspect of the present invention there is provided a storage unit for use in an electronic device having a host electronic module for processing data and a data bus operable to connect the host module to the storage unit. The memory cell includes:

means for receiving a first bit pattern from a host module over a data bus; and

means for providing a second bit pattern on the data bus in response to the received first bit pattern, wherein the second bit pattern has a predetermined relationship to the received first bit pattern so as to allow the host module to determine an available bus width of the data bus from the received second bit pattern in the host module.

According to a fourth aspect of the present invention, an electronic device having a component that receives a memory cell is provided. The electronic device includes:

a data processing unit;

a data bus linking the data processing unit to the memory unit; and

program for checking the electronic functionality of a data bus, the program comprising:

a first code for providing a first bit pattern to the memory cell through the data bus;

a second code for comparing the first bit pattern with a second bit pattern received from the memory cell, the second bit pattern being provided in response to the first bit pattern, the second bit pattern having a predetermined relationship with the first bit pattern received in the memory cell, an

A third code for determining an available width of the data bus based on the received second bit pattern.

The memory cell includes:

means for receiving a first bit pattern from a host module over a data bus; and

means for providing a second bit pattern on the data bus in response to the received first bit pattern.

The electronic device comprises a mobile phone.

The invention will become apparent upon reading the description taken in conjunction with figures 1 to 6.

Brief description of the drawings

FIG. 1 is a block diagram illustrating an electronic device having a host module connected to a memory card, wherein the host module is sending test bit patterns to the memory card.

Fig. 2 is a block diagram illustrating the same electronic device in which the memory card is sending a response bit pattern to the host module.

Fig. 3 is a schematic representation illustrating a mobile phone capable of checking a data bus according to the invention.

FIG. 4 is a schematic representation illustrating a memory cell having means for generating a response bit pattern in response to a test bit pattern.

Fig. 5 is a block diagram illustrating a pattern exchanged between a first electronic module and a second module for determining an available data bus width therebetween.

Fig. 6 is a flow chart illustrating a data bus width checking process according to the present invention.

Best Mode for Carrying Out The Invention

Fig. 1 and 2 illustrate an electronic device 100 that includes a host module 10 having one or more slots to allow one or more memory cards to be inserted into the module. The memory card is represented by a storage unit 30. The host module 10 also includes a processor or ASIC (application specific integrated circuit) 20 having a control port 22 and a data port 24, each of which has bus (110, 120) lines linking the memory units 30. According to the invention, the width of the data bus 120 is obtained during the booting of the memory unit 30.

According to one embodiment of the present invention, a memory bus checking method includes two steps. In a first step, as shown in FIG. 1, the host module 10 sends a test bit pattern to the memory cells 30. The test bit pattern preferably has the form of alternating 0's and 1's, e.g., (01010101 …) and (10101010 …). The pattern length or number of bits in the bit pattern is the same as the maximum data bus width of the host module 10. With an alternating bit pattern of 0 and 1, adjacent pins will have opposite values.

Upon receipt of the test bit pattern, the memory unit 30 sends back a response bit pattern to the host module 10, as shown in FIG. 2. Each bit in the response pattern is the complement of the corresponding bit in the test pattern. For example, if the test pattern is (01010101 …), the response pattern is (10101010 …). When the host module 10 receives the response pattern from the storage unit 30, it compares the response pattern with the test pattern. If the response pattern is an exact mirror of the test pattern, the width of the data bus is the maximum data bus width of the host module 10, assuming all "bits" on the data bus are functioning correctly. If a bit does not remain as a '1' or a '0', it functions correctly. However, if the memory unit 30 can only receive a smaller number of bits than in the test mode, the response pattern received by the host module 10 will not be a complete mirror of the test mode. In that case, the memory unit 30 sets its external data bus width according to the number of valid bits it receives.

There are at least two ways to set the bus width of the memory.

First, the memory cell 30 sets its bus width according to the valid bit it receives. Since memory cell 30 may receive a smaller number of bits than in the test mode, it provides a response mode according to the received bit pattern.

The second way is that the host module determines the card bus width and then passes this bus width to the memory unit through additional command cycles. In this case, the memory cell may receive the same number of bits as in the test mode, or it may receive more bits than in the test mode, as described below:

when the memory cell 30 can receive more bits than the number of bits in the test mode, the response pattern received by the host module 10 will be a mirror of the test mode, assuming all bits are functioning correctly. In that case, the host module 10 sets the bus width according to the number of test patterns.

When the memory cells 30 may receive the same number of bits as in the test mode, but one or more of the bits are defective, the response pattern received by the host module 10 may not be a complete mirror of the test mode. Thus, if the host module 10 determines through the comparison process that it receives fewer valid data bits than sent, the number of bits received defines the used data bus width during the memory access. Otherwise, the data bus width used is the same as the maximum data bus width of the host module 10.

For example, the host module 10 has an 8-bit data bus, and it issues to the memory unit 30(10101010). If the response pattern received by the host module 10 is (01011111), the "multi media card" may have an 8-pin data bus, but the last four bits remain "1". However, if the bus width is 2ⁿ(1, 2, 4 or 8 …), then the "multi media card" can also have a 4-bit data bus. In this case, it can be safely assumed that the number of significant bits of the memory access is 4. However, it is useful to perform a second test cycle so that the host module 10 issues a different test bit pattern (01010101) to make sure the response pattern is (10101111). In general, if the data bus is not necessarily a power of 2, a second cycle is required in order to determine whether the card has a 3-bit or 5-bit data bus when the response mode of the response test mode (10101010) is (01011111).

Similarly, when the host module 10 has a 4-bit data bus, but the width of the card's data bus is greater than 4, then a second cycle test mode needs to be issued to determine whether the card has a 3-bit or 4-bit data bus.

In any case, it is preferred that the test bit pattern of the second cycle is the complement of the bit pattern of the first cycle, and the response bit pattern is the complement of the corresponding test bit pattern. The test procedures of the above examples are summarized in tables I and II.

The test bit pattern may be generated by a software program 26 operatively connected to the ASIC 20. The software program 26 may include computer code for performing a bit pattern comparison to determine the width of the data bus. However, the test pattern and comparison algorithm may be part of the ASIC function.

The present invention provides an efficient way to check the electrical functionality of a data bus, including the case where certain bits on the bus remain "0" or "1". The width of the data bus may be determined by the host module 10 without accessing internal registers in the memory unit 30. Since the data bus width used is determined by the handshake protocol as described above, it is possible to mix various host unit data bus widths with various card memory bus widths.

The electronic device 100 may be a mobile phone, an imaging device, a personal computer, a notebook computer, a personal digital assistant device (PDA), a music storage and playback device such as an MP3 player, a multimedia streaming device, and the like. Fig. 3 is a schematic representation of a mobile phone having a slot 32 for receiving a memory unit 30, a transceiver 40 operatively connected to a host electronic module 10 and an antenna 42 for data communication, and a display 50 for displaying text and images. The memory unit 30 may be removed from the slot 32 and replaced with another memory unit.

Fig. 4 is a schematic representation of a memory cell 30 programmed to generate a response bit pattern 140 in response to a test bit pattern 130. The response bit pattern has a predetermined relationship with the test bit pattern. As shown in fig. 4, the memory unit 30 has pins 150 for insertion into the slots 32 (fig. 3) of the host module 10. The pins 150 include a pin to be connected to the control bus 110 and a pin to be connected to the data bus 120.

Generally, it is desirable to perform a two cycle test procedure as part of the boot process to determine the width of the data bus to be used to transfer data between the host module and the "multi media card" inserted in the electronic device. However, one test cycle can be used to determine the bus width. If the data bus is operating with a pull-up implementation (i.e., the bit is normally high), then the test bit pattern preferably begins at (1010 …). If the data bus is operating with a pull-down implementation (i.e., bits are normally low), then the test bit pattern preferably begins with (0101 …). Thus, the second period may not be required. However, if the data bus is operated with a high z (non-pull) implementation, two cycles with complementary bit patterns are preferred.

TABLE I

8-pin host and 4-pin card

Note that 1: in the first cycle, the last four bits do not change state- > remain as one (unknown pin count) or a 4-bit bus. In this case, the bus may be defined as 4 by using the assumption that the data bus is a multiple of 2. If an uneven data bus width is allowed, a second cycle is required.

Note that 2: none of the last 4 bits change state and the bus width is 4 because the last four bits are not active.

TABLE II

4-pin host and 8-pin card

Note that: in this case, the bus may be defined as 4 by using the assumption that the data bus is a multiple of 2. If an uneven data bus width is allowed, a second cycle is required to define whether the data bus width is 3.

The present invention has been disclosed with respect to a data bus linking a host electronic module with a memory card. However, the same checking procedure may also be used to determine the available width of the data bus linking the first electronic module to the second electronic module, as shown in fig. 5. As shown in fig. 5, the first electronic module 10 is a host module which sends test bit patterns to and receives response bit patterns from the second electronic module 10'. In particular, the control bus 110 and the data bus 120 are connected to a memory unit 30 'in the second electronic module 10'.

Fig. 6 is a flow chart illustrating a data bus width checking process according to the present invention. As shown in the flowchart 200, the host device sends a test bit pattern to the memory card via the data bus in step 210. The memory card inverts the received test bit pattern in step 220 and sends the inverted bit pattern to the host device in step 230. By comparing the test bit pattern with the received bit pattern from the memory cells in step 240, the host device determines the available width of the data bus in step 250. If necessary, a second cycle may be performed, similar to steps 220 through 240. The test bit pattern in the second cycle is preferably the complement of the test bit pattern in step 220. The second cycle may be used to ensure that no bit in the data bus is held at either a '0' or a '1'.

Thus, while the invention has been described with respect to one embodiment thereof, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.

Claims (28)

1. A method for checking the electronic functionality of a data bus between a first electronic module and a second electronic module operatively connected to the first electronic module, the method characterized by:

transmitting a first bit pattern to a second electronic module through the data bus;

providing a second bit pattern in the second electronic module according to the received first bit pattern in the second electronic module, wherein the second bit pattern is different from the received first bit pattern and has a predetermined relationship;

receiving, in the first electronic module, a second bit pattern from a second electronic module over the data bus; and

the received second bit pattern is compared with the first bit pattern to determine an available bus width of the data bus based on the predetermined relationship.

2. The method of claim 1, wherein the first bit pattern has an alternating pattern of '0' and '1'.

3. The method of claim 1, wherein each bit in the received first bit pattern and the second bit pattern has a value of either '0' or '1', and the second bit pattern is complementary to the received first bit pattern such that a bit in the second bit pattern has a value that is different from a value of a corresponding bit in the received first bit pattern.

4. The method of claim 1, wherein the first electronic module has a maximum bus width defined by a predetermined number of bits, the received second bit pattern has one portion in which the pattern is complementary to a corresponding portion of the first bit pattern, the portion having another number of bits less than the predetermined number of bits, and the comparing step determines the available width of the data bus from the portion of the received second bit pattern.

5. The method of claim 1, further characterized by:

transmitting a third bit pattern to the second electronic module through the data bus, wherein the third bit pattern is complementary to the first bit pattern; and

receiving a fourth bit pattern from the second electronic module over the data bus, the fourth bit pattern having a predetermined relationship to the third bit pattern received in the second electronic module.

6. The method of claim 5, further characterized by:

the fourth bit pattern received in the first electronic module is compared to the third bit pattern to determine the available bus width.

7. The method of any of claims 1-6, wherein the second electronic module comprises a memory card.

8. The method of claim 7, wherein the first electronic module has a maximum bus width and the memory card has a number of data pins equal to the number of bits transferable over the maximum bus width.

9. The method of claim 7, wherein the first electronic module has a maximum bus width and the memory card has a number of data pins that is less than the number of bits transferable over the maximum bus width.

10. The method of claim 7, wherein the first electronic module has a maximum bus width and the memory card has a number of data pins, the number of data pins being greater than the number of bits transferable over the maximum bus width.

11. An apparatus for use in a first electronic module to check electronic functionality of a data bus between the first electronic module and a second electronic module, the apparatus characterized by:

means for comparing a first bit pattern provided to the second electronic module over the data bus with a second bit pattern received from the second electronic module over the data bus, wherein the second bit pattern is provided in response to the first bit pattern received in the second electronic module, the second bit pattern being different from the received first bit pattern and having a predetermined relationship; and

means for determining an available bus width of a data bus for transferring data between the first electronic module and the second electronic module according to the predetermined relationship.

12. The apparatus of claim 11, wherein the received first bit pattern has an alternating pattern of '0' and '1' and the second bit pattern is complementary to the received first bit pattern.

13. The apparatus of claim 11, further characterized by means for generating a first bit pattern.

14. The apparatus of claim 11, wherein the first electronic module has a maximum bus width defined by a predetermined number of bits, the received second bit pattern has a portion in which the pattern is complementary to a corresponding portion of the first bit pattern, the portion having a further number of bits less than the predetermined number of bits, and the determining means determines the available width of the data bus from the portion of the received second bit pattern.

15. The apparatus of claim 11, further characterized in that,

means for comparing a third bit pattern provided to the second electronic module over the data bus with a fourth bit pattern received from the second electronic module over the data bus, wherein the third bit pattern is the complement of the first bit pattern, the fourth bit pattern is provided in response to the received third bit pattern in the second electronic module, and wherein the fourth bit pattern has a predetermined relationship to the received third bit pattern so as to allow the determining means to determine the available bus width of the data bus.

16. A storage unit for use in an electronic device having a host electronic module for processing data and a data bus for operatively connecting the host module to the storage unit, the storage unit characterized by:

means for receiving a first bit pattern from the host module over the data bus; and

means responsive to the received first bit pattern for providing a second bit pattern on the data bus, wherein the second bit pattern is different from the received first bit pattern and has a predetermined relationship;

wherein the host electronic module is adapted to compare a first bit pattern with a second bit pattern received in the host module in order to determine an available bus width of the data bus according to the predetermined relationship.

17. The memory cell of claim 16, wherein the received first bit pattern has an alternating pattern of '0' and '1' and the second bit pattern is complementary to the received first bit pattern.

18. The memory unit of claim 16, wherein the data bus has a maximum bus width, and the memory unit has a plurality of data pins for operatively connecting to the data bus, and the number of data pins is less than the number of data bits transferable over the maximum bus width.

19. The memory unit of claim 16, wherein the data bus has a maximum bus width, and the memory unit has a plurality of data pins for operatively connecting to the data bus, and the number of data pins is equal to the number of data bits transmittable over the maximum bus width.

20. The memory unit of claim 16, wherein the data bus has a maximum bus width, and the memory unit has a plurality of data pins for operatively connecting to the data bus, and the number of data pins is greater than the number of data bits transmittable over the maximum bus width.

21. An electronic device having a component that receives a memory cell, characterized by:

a data processing unit;

a data bus linking said data processing unit to said memory unit; and

a component for checking the electronic functionality of the data bus, the component comprising:

means for providing a first bit pattern to the memory cells through the data bus;

means for comparing the first bit pattern with a second bit pattern received from the memory cell over the data bus, wherein the second bit pattern is provided in the memory cell in response to the first bit pattern received in the memory cell, and wherein the second bit pattern is different from the received first bit pattern and has a predetermined relationship; and

means for determining an available width of the data bus according to the predetermined relationship according to the received second bit pattern.

22. The electronic device of claim 21, wherein the component for checking the electronic functionality of the data bus is performed during a boot process.

23. An electronic device according to claim 21 or 22, wherein the electronic device is a mobile telephone.

24. The electronic device according to claim 21, wherein the storage unit is provided in another electronic device.

25. The electronic device of claim 21, wherein the storage unit comprises:

means for receiving a first bit pattern from the data processing unit over the data bus; and

means for providing a second bit pattern on the data bus in response to the first bit pattern received through the data bus.

26. The electronic device of claim 21, wherein the first bit pattern has an alternating pattern of '0' and '1'.

27. The electronic device of claim 21, wherein each bit of the received first bit pattern and second bit pattern has a value of either '0' or '1', and the second bit pattern is complementary to the received first bit pattern.

28. The electronic device of claim 21, wherein the assembly further comprises:

means for providing a third bit pattern to the memory cells via the data bus, wherein the third bit pattern is complementary to the first bit pattern so as to allow the providing means to compare the third bit pattern with a fourth bit pattern received from the memory cells via the data bus, the fourth bit pattern being provided in response to the received third bit pattern in the memory cells and the fourth bit pattern having a predetermined relationship to the received third bit pattern, and wherein the determining means further determines the available width of the data bus based on the received fourth bit pattern.