HK1076199B - A multi-configuration processor-memory device - Google Patents

Description

Multi-configuration processor-memory device

Technical Field

The field herein relates to electronic integrated circuits. More particularly, the present disclosure relates to printed circuit board devices. This document relates to a multi-configuration processor storage substrate apparatus.

Background

Digital computer systems are used today to perform a wide range of tasks. Many different areas of business, industry, government, education, entertainment, and more recently homes are entering a large and rapidly growing list of applications developed for today's increasingly powerful computer devices.

Modern computer systems often feature powerful digital processor integrated circuit devices. The processor is used to execute software instructions to perform complex functions, such as 3-D image applications, speech recognition, data visualization, and the like. The performance of many of these applications directly benefits from more powerful, more powerful processors. In addition, powerful modern computer systems have reduced costs to make them more available to the average user than ever before.

A major feature of the growing capabilities of modern computer systems and their reduced cost is the smooth progress of integrated circuit device manufacturing techniques. Modern semiconductor manufacturing technologies have resulted in increased levels of integration, increased capabilities, and reduced costs for such computer devices (e.g., portable computer systems, desktop computer systems, workstations, servers, etc.).

Computer system device manufacturers have found compact size to be a desirable marketing feature. Typically, the more compact the device, the lower its manufacturing cost. In addition, compact size (e.g., increased integration) yields many other benefits, such as reduced power consumption and increased portability. Thus, a major goal of many computer system device manufacturers is to reduce the form factor of a given device while maintaining or even increasing the performance of the device.

The goal of reducing the form factor of computer system devices has resulted in several prior art integrated circuit packaging schemes. One prior art packaging scheme involves the implementation of a multi-chip module. A multi-chip module, or MCM, refers to a chip package that includes two or more "raw" chips closely connected to high-density wires, or signal traces embedded in or on the package. A raw chip is generally referred to as a semiconductor integrated circuit chip without an associated package. The original chip is typically mounted directly on a substrate or embedded therein. A prior art MCM implementation saves space and in some cases speeds up processing due to short wires between chips (e.g., as compared to several discrete chips conventionally mounted on a printed circuit board). Ceramic substrates are typically used with wire-on-chip bonding (MCM-C) or with deposited thin film interconnects (MCM-D). MCMs have been mounted on silicon substrates (MCM-S) and resin-based laminated printed circuit boards (MCM-L), which have evolved into multi-chip packages (MCP) at low cost.

Another prior art packaging scheme involves the implementation of a multi-chip package. A multi-chip package, or MCP, refers to a chip package that includes two or more packaged chips, as opposed to the original chips. It is important that the MCM uses a laminated, printed circuit board-like substrate (MCM-L) rather than ceramic (MCM-C).

However, the above prior art package implementations have a number of problems. Signal traces are difficult to route through the substrate or the substrate using MCMs and MCPs. For example, a modern processor integrated circuit die may have 500 or more interconnects that need to be coupled or routed through the substrate. In an MCM or MCP with many such chips, wiring issues may be important.

Other problems arise from the increased complexity of the design applied to the substrate. The routing problem leads to a more complex design of the substrate. For example, to route thousands of different traces, many substrates are implemented in multiple layers and signal traces are implemented in close groupings, which can in turn lead to another set of problems (e.g., crosstalk, uneven path delay, etc.). In addition, highly complex substrates are difficult to manufacture. For example, high performance MCMs that mount multiple chips have very tight manufacturing tolerances. The tight tolerances reduce the yield and reliability of the MCM. This increases the cost of the resulting computer system device. Another factor that increases cost is the use of raw chips. The raw chips must typically be mounted on the substrate and the equipment must be completed before testing. Therefore, it is difficult to detect a defective chip before the device is completed. This reduces the overall yield of the device fabrication process.

Another problem with prior art MCM and MCP package implementations is the fact that it is difficult to manage heat dissipation for a compactly packaged MCM/MCP device. It is more difficult to remove heat from the plurality of chips. In addition, the device may be thermally unbalanced, wherein heat can propagate from "hot" components to "cold" components, affecting their performance and reliability. In addition, the substrate and ceramic base of the device are not very good thermal conductors. As a result, prior art MCM/MCP devices may require complex heat sink devices to maintain a high level of performance. Most of the waste heat needs to be transferred to the surrounding air (e.g. heat pipes, high airflow, noise fans, etc. are needed). As component packing density increases and clock speeds increase, so does the thermal energy that must be dissipated. In order to maintain high performance, a stable operating temperature must be maintained. Therefore, high performance prior art MCM/MCP devices must be configured for use with elaborate heat dissipation devices (e.g., heat sink fans, liquid cooling, heat spreaders, etc.). This increases the size of the overall package and can offset the major benefits of using MCM/MCP designs.

What is needed, therefore, is a solution that efficiently packages multiple integrated circuit components while maintaining a cost effective package specification. What is needed is a solution that demonstrates features that contribute to yield and performance, and that has a small package footprint.

Disclosure of Invention

Embodiments of the present invention provide a multi-configurable processor-memory device having a standardized interface for coupling to a printed circuit board. Embodiments of the present invention provide a solution that efficiently packages multiple integrated circuit components while maintaining a cost effective packaging specification. In addition, embodiments of the present invention provide features that contribute to yield and performance, and have a small package footprint.

In one embodiment, the invention is implemented as a multi-configuration processor-memory device for coupling to a PCB interface of a printed circuit board. The apparatus includes a substrate, an arrangement supporting a plurality of memory components, and a processor having a single, common interface for connection with an interface region of the printed circuit board. (e.g., in one embodiment, an array of pads disposed on a surface of the printed circuit board). In a first configuration, the substrate supports a processor and a first number of memory components. In a second configuration, the substrate supports a processor and an additional number of memory components (e.g., four or more memory chips). The memory components may be pre-tested and the packaged memory components mounted on the substrate. The processor may be a surface mount (or wire bonded) processor die. In addition, the processor may be mounted in a flip-chip (flip-chip) configuration in one plane opposite the (side-address) memory component. In a first configuration (processor and memory components on the same side of the substrate), a heat sink may be mounted on the memory components and processor to dissipate heat. In a second flip-chip configuration (processor and memory components on opposite sides of the substrate), the processor face may be soldered to the non-electrically functional area of the PCB interface of the printed circuit board to dissipate heat, and a heat sink on the opposite side would simply dissipate heat for only the memory components.

In one embodiment, the processor may be a GPU (graphics processing Unit) and the memory component may be a DDR (double data Rate) memory component, depending on the particular configuration. The GPU may be a die mounted on the substrate while the memory components are being pretested, with packaged memory components mounted on the substrate.

In another embodiment, a multi-configuration processor-memory device includes a heat spreader coupled to a memory component to conduct heat from the memory component independent of heat from a GPU. The GPU is mounted on a substrate in a flip-chip configuration on a side of the substrate opposite the memory component. In this embodiment, the GPU includes a heat conduction surface configured for attachment to a heat sink, wherein the heat sink is configured to protrude through an opening of a printed circuit board and conduct heat from the GPU through the opening to a side of the printed circuit board opposite the GPU device, thereby providing a robust heat conduction path for the GPU that is independent of a heat spreader of the memory component.

In this manner, embodiments of the present invention implement a processor-memory device having a compact size and small form factor, resulting in lower manufacturing costs and a smaller application footprint. Since the heat dissipation from the memory components and the processor is decoupled, high performance can be maintained, allowing for higher clock speeds and more uniform heat dissipation. In addition, the use of pre-tested, pre-packaged memory components increases the yield of the device manufacturing process.

Drawings

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 is a diagram illustrating a first configuration and a second configuration of a processor-memory device, according to an embodiment of the present invention.

FIG. 2 is a side view showing a first configuration (configuration A) and a second configuration (configuration B) of a multi-configuration processor-memory device according to an embodiment of the present invention.

FIG. 3A is a side view of a substrate of configuration B in relation to a common PCB interface of a PCB (printed Circuit Board) according to an embodiment of the invention.

FIG. 3B is a top down view showing a common PCB interface according to an embodiment of the present invention.

Fig. 4 is a close-up side view illustrating a solder interconnection between a substrate and a common PCB interface according to an embodiment of the present invention.

Fig. 5A is a first side view illustrating solder interactions between a substrate, a flip-chip mounted processor, and a common PCB interface in accordance with an embodiment of the present invention.

Fig. 5B is a second side view of the PCB showing the relationship between a plurality of solder paste deposits and a plurality of solder balls according to an embodiment of the present invention.

Fig. 6 is a side view showing an alternative embodiment in which the solder balls are used for electrical interconnections and in which an adhesive layer is used to attach the processor to the nonfunctional area of the common PCB interface.

Fig. 7 is a diagram illustrating pads of a nonfunctional area of a common PCB interface arranged in a grid-like fashion, in accordance with one embodiment of the present invention.

Fig. 8 is a side view illustrating the mesh on the surface of the nonfunctional area according to an embodiment of the present invention.

Fig. 9 is a side view showing solder balls and a grid on the surface of the nonfunctional area according to an embodiment of the present invention.

Figure 10 is a diagram illustrating a processor-memory device in accordance with an alternative embodiment of the present invention wherein the flip-chip configuration of the processor-memory device is mounted to a heat sink designed to attach to the processor through an opening in the PCB.

Detailed Description

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these preferred embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, one of ordinary skill in the art will realize that the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments of the invention.

Embodiments of the present invention provide a multi-configuration processor-memory device having a standardized interface coupled to a printed circuit board. Embodiments of the present invention provide a solution that efficiently packages multiple integrated circuit components while maintaining a cost effective packaging specification. In addition, embodiments of the present invention provide features that facilitate yield and performance while having a small package footprint.

FIG. 1 is a first configuration and a second configuration of a processor-memory device in accordance with one embodiment of the present invention. As shown in FIG. 1, the first configuration, configuration A, includes a processor 130 and a plurality of memory components 121 and 124 mounted on a substrate 110. The second configuration, configuration B, includes a processor 150 and a plurality of memory components 141 and 142 mounted on the substrate 120. Both configuration a and configuration B are designed to be mounted on a common PCB interface 160.

Still referring to fig. 1, embodiments of the present invention are designed with a configurable substrate that is adapted to support a variety of combination mounting configurations of processor and memory components while still maintaining a common interface, for example, to an interface region of a printed circuit board (e.g., motherboard, etc.). As shown in FIG. 1, configuration A has 4 memory units 121 and 124 and a single processor 130. Configuration B has 2 memory components 141 and 142 and a single processor 150. Both configurations utilize a common substrate interface designed to couple to a common PCB interface 160. It is worthy to note that embodiments may be configured to support other combinations of memory components and processors (e.g., one processor and one memory component, eight memory components, 16 memory components, etc.).

In one embodiment, the memory components 121, 124, and 141, 142 are pre-packaged memory components. As used herein, prepackaged memory components refer to memory components that are not bare chips or original chips. The memory components are packaged in a conventional manner and tested prior to mounting on the substrate 110 or the substrate 120. The use of prepackaged pretested memory components increases the yield of the overall device fabrication process compared to prior art MCM or MCP devices that utilize raw chips. In addition, the use of prepackaged memory components simplifies their acquisition process. For example, prepackaged memory components can be purchased from a large number of suppliers, providing greater flexibility in price and/or quality.

In the configuration a and B embodiments shown in fig. 1, the memory component is surface-mounted on the substrate 110 or 120. In configuration B, the processor 150 is surface mounted on the substrate 120 along with the memory components. In configuration a, the processor 130 is mounted on the substrate 110 in a flip-chip configuration, as indicated by the dashed line representing the outline of the processor 130.

In one embodiment, processors 130 and 140 are GPUs (graphics processor units), and in other embodiments, processors 130 and 140 are other types of processors, such as DSPs (digital Signal processors), CPUs (Central processing Unit), and the like. Similarly, in one embodiment, memory components 121, 124, and 141, 142 are DDR memory components. In another embodiment, memory components 121, 124, and 141, 142 are other types of memory components, such as RDRAM memory components, SDRAM memory components, and the like.

FIG. 2 shows a side view of configurations A and B of a multi-configuration processor-memory device, according to one embodiment of the invention. As shown in fig. 2, in configuration B, the processor 150 is surface mounted on the same side of the substrate 120. In configuration a, the processor 130 is mounted on the substrate 110 in a flip-chip configuration. In configuration a, the memory components 121 and 124 are surface mounted on the substrate while the processor 130 is flip-chip mounted on the opposite side of the substrate from the memory components.

In configuration a, the flip-chip mounting of the processor 130 provides increased component density and a smaller form factor. By flip-chip mounting the processor 130 on the side opposite the memory components, an additional number of memory components may be included within the same form factor. Similarly, for a given number of parts, a smaller form factor with a smaller application footprint may be implemented. The smaller form factor and increased component density result in reduced manufacturing costs. In addition, the flip-chip configuration of the processor 130 simplifies signal trace routing implementation for the substrate.

The flip-chip mounting of processor 130 in configuration a allows processor 130 to be cooled independently of memory components 121 and 124. For example, the memory components 121 and 124 may be coupled to their respective heat spreaders or heat sinks. The processor 130 on the opposite side of the substrate 110 can utilize its own heat dissipation mechanism. More detailed features are described below in fig. 5A.

Fig. 3A shows a side view of the substrate 120 of configuration B relative to a common PCB interface 160 of a PCB (printed circuit board) 170. As described above, both configurations of the processor-memory device of this embodiment include one interface designed to couple to the common PCB interface 160. The common PCB interface 160 functions by providing an electrical interconnection to the PCB 170. The attachment between the interface of the substrate 120 and the common PCB interface 160 is typically implemented using solder. The common PCB interface may include an array of pads for receiving solder interconnections with the substrate 120.

It is noted that in this embodiment, the common PCB interface 160 is shown as being generally flush with the surface of the PCB 170 or having the same height as the surface of the PCB 170. In another embodiment, the common PCB interface 160 may have a different height than the surface of the PCB 170, for example, slightly above the surface of the PCB 170, as shown in fig. 5A and 6 below.

FIG. 3B illustrates a top view of the common PCB interface 160, according to one embodiment of the present invention. As shown in fig. 3B, the common PCB interface 160 includes an array of pads for receiving a plurality of solder interconnects (e.g., hundreds of interconnects) of the processor-memory device. In this embodiment, the common PCB interface 160 includes a nonfunctional area 165, which is located in the center of the pad array. The non-functional area 165 refers to the fact that: there are no pad interconnects in this region that are active or used by components on PCB 170.

Fig. 4 illustrates a proximal view of a solder interconnection between the substrate 120 and the common PCB interface 160 of the PCB 170, in accordance with one embodiment of the present invention. As known to those skilled in the art, a plurality of solder interconnects 401 (e.g., solder balls 401) are used to couple the interface of the substrate 120 to the pads of the common PCB interface 160. Once the solder interconnects, a discrete distance 410 between the substrate 120 and the common PCB interface 160 is maintained. In a typical implementation, distance 410 is about 500 microns. This distance is sufficient to accommodate a flip-chip mounted processor configuration, as shown in fig. 5A below.

Fig. 5A is a side view illustrating solder interaction between the substrate 110, the flip-chip mounted processor 130, and the common PCB interface 160 according to one embodiment of the invention. Fig. 5A shows solder interconnections for a processor-memory device configuration a embodiment.

In this embodiment, the plurality of solder balls 401 are used to connect the interface of the substrate 110 to the common PCB interface 160 in a manner similar to the connection between the substrate 120 and the common PCB interface 160 described above in fig. 4. However, in addition to the solder balls 401 that enable electrical interconnection between the interface and the common PCB interface 160, solder paste deposition (e.g., described in more detail below in fig. 5B) also attaches the surface of the processor 130 to the nonfunctional area 165 of the common PCB interface 160. In this embodiment, the surface of the processor 130 is soldered directly to the nonfunctional area 165 to provide a thermal conduction path, thereby conducting thermal energy directly out of the processor 130 into the common PCB interface 160 and the PCB 170.

In this manner, the surface of the processor 130 is configured for attachment to the PCB interface 160 of the printed circuit board so that heat is conducted from the processor through the attachment. This distance 410 (e.g., about 500 microns) provides sufficient space for the flip-chip mounted processor 130 to extend between the interface of the substrate 110 and the PCB interface 160, since the processor typically extends about 350 microns from the surface of the substrate 110.

The solder attachment shown in fig. 5A allows the reflowed solder paste to conduct most of the heat from the processor 130 directly to the PCB 170. This provides a heat conduction path for processor 130 that is independent of the memory components. The independent thermal conduction path thermally decouples the memory components from the processor allowing for separate thermal dissipation paths. Thus resulting in a more uniformly controlled low junction temperature in all of the mounted integrated circuit devices. Further, the PCB interface 160 is shown in fig. 5A and 6 as being slightly above the surface of the PCB 170, as compared to the flush, co-planar configuration described in fig. 3A.

Fig. 5B illustrates a side view of the PCB 170 showing the relationship between a plurality of solder paste deposits 502 and the solder balls 401 according to one embodiment of the present invention. In the embodiment depicted in fig. 5B, solder paste deposition 502 is used to achieve attachment to the processor 130. Upon reflow, the solder attachment shown in fig. 5A is generated from the solder paste deposit 502. In one embodiment, the solder balls 401 are typically standard size 63mm solder balls. The embodiment of fig. 5B also shows a plurality of thermal vias 501 embedded in PCB 501 to conduct heat from the attachment into processor 130.

Fig. 6 is a side view of an alternative embodiment in which solder balls 401 are used for electrical interconnection and in which an adhesive layer 601 is used to adhere the processor 130 to the nonfunctional area 165 of the common PCB interface 160. The embodiment depicted in fig. 6 is substantially similar to the embodiment shown in fig. 5A, except that a thermal adhesive layer 601 is used to attach the surface of the processor 130 and thus achieve a thermal conduction path, as opposed to solder. According to the embodiment shown in FIG. 5A, the thermal adhesive layer 601 provides an independent thermal conduction path for the processor 130.

Fig. 7, 8 and 9 show views of the nonfunctional area 165 of the common PCB interface 160 in greater detail, according to one embodiment of the present invention. As shown in fig. 7, the pads of the nonfunctional area 165 are arranged in a grid form. In this embodiment, the grid is implemented to prevent solder balls 401 used to connect the surface of the processor 130 from spreading and possibly detaching from the surface of the processor 401.

Referring to fig. 8, a side view of the grid on the surface of the nonfunctional area 165 is shown. Fig. 8 also shows a surface 131 of the processor 130, which is configured to be attached to the nonfunctional area 165. In one embodiment, the surface 131 is a metallized surface (e.g., copper, etc.), or a thermally conductive surface, adapted to facilitate thermal conduction from the processor 130. Alternatively, the surface 131 may be a die surface.

Referring to fig. 9, a side view of solder balls 401 and a grid on the surface of the nonfunctional area 165 is shown. As described above, the grid is implemented to prevent solder balls 401 from spreading and possibly detaching from surface 131 of processor 130. The "ridges" of the grid extend upward from the surface of region 165 by approximately 20 to 30 microns.

In one embodiment, the grid is implemented using a "solder-mask" material. The solder mask material may be applied to the surface of the nonfunctional area 165, and thus implement a grid pattern, during the same manufacturing steps as other solder mask features are implemented on the surface of the PCB 170. The material comprising the mesh may be a polymeric material, such as that used in a typical SMOBC (solder over copper solder mask). Alternatively, in another embodiment, the grid may be implemented by etching the surface of the nonfunctional area 165 (e.g., copper).

FIG. 10 illustrates a processor-memory device in accordance with an alternative embodiment of the present invention. In this embodiment, a flip-chip configuration (e.g., configuration a) of the processor-memory device is mounted through an opening (e.g., hole) in PCB 1070 to a heat sink 1025 designed to attach to processor 130.

In this embodiment, the multi-configuration processor-memory device includes a heat sink 1020 coupled to the memory components to conduct heat from the memory components independent of the processor 130. The processor 130 is mounted on the substrate in a flip-chip configuration on a side of the substrate opposite the memory components. In this embodiment, the processor 130 includes a thermally conductive surface configured for attachment to the heat sink 1025. The heat sink 1025 is configured to protrude through an opening of the 1070 and conduct heat from the processor 130 through the opening to a side of the PCB 1070 opposite the processor 130 device, thereby conducting heat away from the processor 130 in a manner that is independent of the memory component (which uses the heat spreader 1020). The surface of the processor is mounted to the heat sink 1025 opposite the nonfunctional area 165 of the common PCB interface 160. The electrical interconnections of the common PCB interface 160 will be disposed along the perimeter of the opening in the PCB 1070.

This embodiment provides the advantage of a very robust heat transfer device (e.g., heat sink 1025) coupled to processor 130. This allows the processor to generate a greater amount of heat than would otherwise be possible, thus allowing higher clock speeds, higher performance, etc. The heat sink 1025 may optionally include a fan to increase airflow, thereby dissipating a greater amount of heat from the processor 130.

Accordingly, embodiments of the present invention provide a multi-configuration processor-memory device with a standardized interface for coupling to a printed circuit board. Embodiments of the present invention provide a scheme for efficiently packaging multiple integrated circuit components while maintaining a cost-effective packaging specification. Furthermore, embodiments of the present invention provide satisfactory yield and performance characteristics and a small package area. Since heat dissipation from the storage components and the processor is decoupled, high performance can be maintained, which allows for higher clock speeds and more uniform heat dissipation. Furthermore, the use of pre-tested pre-packaged memory components increases the yield of the device manufacturing process.

Broadly speaking, this writing describes a multi-configuration processor-memory device for coupling to a PCB (printed circuit board) interface. The apparatus comprises: a substrate supporting a plurality of configurations of memory components; and a processor having a single, common interface with the PCB interface of the printed circuit board. In a first configuration, the substrate supports a processor and a first number of memory components. In a second configuration, the substrate supports a processor and an additional number of memory components. The memory components may be pre-tested, packaged memory components mounted on a substrate. The processor may be a surface mounted processor die. Further, the processor may be mounted in a flip-chip configuration, with the face opposite the memory component. In a first configuration, a heat sink may be mounted on the memory component and the processor to dissipate heat. In a second configuration, the flip chip, configuration, processor face may be soldered onto a non-electrically functional area of a PCB interface of a printed circuit board to dissipate heat.

The foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims (23)

1. A multi-configuration processor-memory device for coupling to a printed circuit board interface of a printed circuit board, comprising:

a substrate having a first configuration and a second configuration, wherein the substrate is configured to mount a processor and a first number of memory components in the first configuration and to mount the processor and an additional number of memory components in the second configuration; and

an interface, built into the substrate, for coupling to a printed circuit board interface of a printed circuit board.

2. The device of claim 1, wherein the memory component and the processor are surface mounted on a substrate.

3. The device of claim 1, wherein the processor is mounted on the substrate in a flip-chip configuration.

4. The device of claim 3, wherein the processor is mounted on the substrate in a flip-chip configuration on an opposite side of the substrate from where the memory components are mounted.

5. The apparatus of claim 1, wherein the processor is a graphics processor unit.

6. The apparatus of claim 1, wherein the storage element is a double data rate storage element.

7. The apparatus of claim 1, wherein the storage component is a packaged storage component.

8. The device of claim 1, wherein the processor is mounted in a flip-chip configuration on the same side of the substrate as the interface.

9. The device of claim 8, wherein the surface of the processor is configured to be attached to a region of a printed circuit board interface of the printed circuit board to conduct heat from the processor through the attachment.

10. The apparatus of claim 9, wherein the attachment is a solder attachment.

11. The apparatus of claim 9, wherein the attachment is a sticker attachment.

12. The device of claim 1, wherein the memory component is configured to receive a heat sink to conduct heat from the memory component.

13. The apparatus of claim 1, wherein the first number of memory units of the first configuration is two memory units and the second number of memory units of the second configuration is at least four memory units.

14. A multi-configuration graphics processor unit device for coupling to a printed circuit board, comprising:

a substrate having a first configuration and a second configuration, wherein the substrate is configured to mount a graphics processor unit and a first number of memory components in the first configuration and to mount the graphics processor unit and an additional number of memory components in the second configuration; and

a common interface built into the substrate for coupling to a printed circuit board interface of a printed circuit board, wherein the common interface is configured to provide standardized interconnection with the printed circuit board interface for the first configuration and the second configuration.

15. The device of claim 14, wherein the device is a package for coupling to a printed circuit board interface of a printed circuit board.

16. The device of claim 15, wherein the graphics processor unit is mounted on the substrate in a flip chip configuration on a side of the substrate opposite the memory component, and wherein the graphics processor unit includes a thermally conductive surface configured to attach to a printed circuit board interface of a printed circuit board for conducting heat from the graphics processor unit through the attachment.

17. The apparatus of claim 16, wherein the graphics processor unit is mounted on a substrate coplanar with the solder ball plane of the common interface to effect attachment of the printed circuit board interface to the printed circuit board.

18. The apparatus of claim 16, wherein the attaching is accomplished by using solder.

19. The device of claim 16, wherein said attaching is accomplished by using an adhesive.

20. The apparatus of claim 16, wherein the storage component is a packaged dual data rate storage component.

21. The device of claim 16, wherein the memory component is configured to receive a heat sink to conduct heat from the memory component.

22. The apparatus of claim 16, wherein said printed circuit board interface includes a non-electrically functional area for effecting attachment to a thermally conductive surface of said graphics processor unit, and wherein said non-electrically functional area is provided with a grid thereon for receiving a plurality of solder balls to effect said attachment.

23. The apparatus of claim 22, wherein the grid comprises a solder mask material deposited using a solder mask on bare copper process.