HK1069935A - Hybrid parallel/serial bus interface - Google Patents

Description

Hybrid parallel/serial bus interface

Technical Field

The present invention relates to bus data transfer. In particular, the present invention is directed to reducing the number of lines that carry bus data.

Background

An example of a bus for transferring data is shown in FIG. 1. Fig. 1 is an illustration of receive and transmit Gain Controllers (GCs) 30, 32, and a GC controller 38 for a wireless communication system. A communication station, such as a base station or user equipment, Transmits (TX) and Receives (RX) signals. To control the gain of these signals, which falls within the operating range of other receive/transmit components, the GCs 30, 32 adjust the gain on the RX and TX signals.

To control the gain parameters of the GCs 30, 32, a GC controller 38 is utilized. As shown in fig. 1, the GC controller 38 sends the gain values of the TX36 and RX 34 signals using a power control bus, such as 16-wire buses 34, 36, such as eight wires each. Although power control bus lines 34, 36 may allow for fast data transfers, they may require multiple pins on the GCs 30, 32 and the GC controller 38, or multiple connections between the GCs 30, 32 and the GC controller 38 on an Integrated Circuit (IC) such as an Application Specific Integrated Circuit (ASIC). Increasing the pin count requires additional board space and connections. Increasing IC connections takes up valuable IC space. The large number of pins or connections may increase the cost of the bus depending on the implementation.

Thus, it is desirable to have other data transfer means.

Disclosure of Invention

A hybrid parallel/serial bus interface having a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplex the data block into a plurality of nibbles. For each nibble, a parallel-to-serial converter may convert the nibble to serial data. A line may carry serial data for each nibble. A serial-to-parallel converter converts the serial data of each nibble to recover the nibble. The data block reconstruction device may merge the recovered nibbles into the data block. A base station (or UE) has a gain control controller. The gain control controller generates a data block having n bits representing a gain value. A data block demultiplexing device has an input configured to receive the data block and demultiplex the data block into a plurality of nibbles. Each nibble has a plurality of bits. For each nibble, a parallel-to-serial converter converts the nibble into serial data, a line transmits the nibble serial data, and a serial-to-parallel converter converts the nibble serial data to recover the nibble. A data block reconstruction device may merge the recovered nibbles into the data block. A gain controller receives the data block and adjusts the gain of the data block by using the gain value of the data block.

Drawings

Fig. 1 is a schematic illustration of RX and TX GC and GC controllers.

Fig. 2 is a block diagram of a hybrid parallel/serial bus interface.

FIG. 3 is a flow chart of a data block transfer operation using a hybrid parallel/serial bus interface.

Fig. 4 illustrates the demultiplexing of a block into most significant and least significant nibbles.

Fig. 5 illustrates demultiplexing a block using data interleaving.

Fig. 6 is a block diagram of a bi-directional hybrid parallel/serial bus interface.

Fig. 7 is a diagram of a bi-directional line implementation.

Fig. 8 is a timing diagram of start bits.

Fig. 9 is a block diagram of a function controllable hybrid parallel/serial bus interface.

FIG. 10 is a timing diagram of start bits for a function controllable hybrid parallel/serial bus interface.

Fig. 11 is a table showing the implementation of start bits for each function.

Fig. 12 is a block diagram of a destination controlled hybrid parallel/serial bus interface.

Fig. 13 is a list of start bit implementations indicating destinations.

Fig. 14 is a table showing the implementation of start bits for each destination/function.

Fig. 15 is a block diagram of a destination/function control hybrid parallel/serial bus interface.

Figure 16 is a flow chart of start bits representing destinations/functions.

FIG. 17 is a block diagram of a hybrid parallel/serial bus interface for positive and negative clock signal edges.

FIG. 18 is a timing diagram for a hybrid parallel/serial bus interface for positive and negative clock signal edges.

Figure 19 is a 2-wire GC/GC controller bus block diagram.

Figure 20 is a 3-wire GC/GC controller bus block diagram.

Detailed Description

FIG. 2 is a block diagram of a hybrid serial/parallel bus interface, and FIG. 3 is a flow chart of a data transfer operation of the hybrid serial/parallel bus interface. A data block is transmitted across the interface from node 150 to node 252 (54). A data block demultiplexing device 40 receives the block and demultiplexes it into i nibbles for transmission over i data transmission lines 44 (56). The value i is determined by a trade-off between the number of connections and the transfer speed. One way to determine the value of i is to first determine a maximum delay allowed to transmit the data block. Based on this maximum delay, the minimum number of lines required to transmit the block is determined. With a minimum number of lines, the lines used to transmit data are selected to be at least the minimum number. The traces 44 may be pins and their associated connections on a circuit board or on an IC connection. One way to demultiplex into nibbles is to slice the block into a most significant to a least significant nibble. To illustrate in fig. 4, an eight-bit block is transmitted on two lines, which is demultiplexed into a four-bit most significant nibble and a four-bit least significant nibble.

Another way is to interleave the block across i nibbles. The first i bits of the block become the first bit of each nibble. The next i bits become the second bit of each nibble, and so on until the last i bits. To illustrate an eight bit block on two connections as shown in fig. 5, the first bit would be mapped to the first bit of nibble 1. The second bit will be mapped to the first bit of nibble 2. The third bit is mapped to the second bit of nibble 1 and so on until the last bit is mapped to the last bit of nibble 2.

Each nibble is sent to a corresponding one of i parallel-to-serial (P/S) converters 42 (58), converted from parallel bits to serial bits, and serially transmitted in sequence on the line (60). On the opposite side of each line would be a serial-to-parallel (S/P) converter 46. Each S/P converter 46 converts the transmitted serial data into its original nibble (62). The ith recovered nibble is processed by a data block reconstruction device 48 to reconstruct the original data block (64).

On the other hand, bi-directional, i connections are used to transfer data in a bi-directional manner, i.e. as shown in fig. 6. The information data may be transmitted in both directions, or the information may be transmitted in a single direction and the acknowledgement signal may be sent back in the other direction. Here, a data block demultiplexing and reconstruction device 66 receives the data block transmitted from node 150 to node 252. The demultiplexing and reconstruction device 66 demultiplexes the block into i nibbles. The i P/S converters 68 convert each nibble into serial data. A set of Multiplexers (MUX)/DEMUX 71 couples each P/S converter 68 to a corresponding one of the i lines 44. At node 252, another set of multiplexers MUX/DEMUX 75 connects lines 44 to a set of S/P converters 72. The set of S/P converters 72 converts the received serial data of each nibble into the originally transmitted nibble. The received nibbles are reconstructed by a data block demultiplexing and reconstruction device 76 into the original data block and output as the received data block.

For each block transmitted from node 252 to node 150, the data block demultiplexing and reconstruction device 76 receives a data block. The block is demultiplexed into nibbles and each nibble is sent to a set of P/S converters 74. The P/S converter 74 converts each nibble into a serial format for transmission across the i lines 44. MUX/DEMUX 75 of node 2 would couple the P/S converter 74 to i lines 44, while MUX/DEMUX 71 of node 1 would couple lines 44 to i S/P converters 70. The S/P converter 70 converts the transmitted data into its original nibbles. The data block demultiplexing and reconstruction device 66 reconstructs the data block from the received nibbles to output the received data block. Since data is only transmitted in a single direction at a time, this implementation may operate in a half-duplex manner.

Fig. 7 is a simplified diagram of an implementation of a bidirectional switching circuit. The serial output of the node 1P/S converter 68 is input to a tri-state buffer 78. The buffer 78 has another input which is coupled to a voltage representing a high state. The output of the buffer 78 is serial data which is transmitted over line 85 to a node 2 tri-state buffer 84. Resistor 86 is coupled between line 85 and ground. The node 2 buffer 84 passes the serial data to a node 2S/P converter 74. Similarly, the serial output from the node 2P/S converter 74 is input to a tri-state buffer 72. The buffer 72 also has another input coupled to a high voltage. The serial output of the buffer 82 is transmitted to the node 1 tri-state buffer 80 over line 85. The node 1 buffer 80 passes the serial data to a node 1S/P converter 70.

In another implementation, some of the i lines 44 may transmit data in one direction, while other i lines 44 may transmit data in another direction. At node 150, a data block is received for transmission to node 252. Depending on the data throughput rate required for the block and the traffic demand in the other direction, the block is transmitted using j connections, where j is between 1 and i. The block is divided into j nibbles and converted into j sets of serial data using j of the i P/S converters 68. Corresponding j node 2S/P converters 72, and node 2 data block distinguishing and reconstruction device 76, restore the data blocks. In the opposite direction, up to i-j or k lines are used to transmit the data block.

In a preferred implementation of a bi-directional bus for a gain control bus, a gain control value is sent in one direction and an acknowledgement signal is sent back. Alternatively, a gain control value is sent in one direction and a gain control device status signal is sent in the other direction.

A hybrid parallel/serial interface implementation is within a synchronous system and may be as illustrated with reference to fig. 8. A synchronous clock signal is used to synchronize the timing of the various components. To indicate the start of the data block transfer operation, a start bit is sent. I.e., as shown in fig. 8, each line will be at its normal zero level. A start bit is then sent indicating the start of the block transfer operation. In this example, all lines send a start bit, but only one line needs to send a start bit. If the start bit is sent on any line, such as a 1 value, the receiving node knows to start the block data transfer operation. Here, each serial nibble is sent out through its corresponding line. After each nibble is transmitted, the lines return to their normal state, e.g., all low.

In other implementations, the start bits are also used as an indicator of the function to be performed. Such an implementation may be illustrated in fig. 9. As shown in fig. 10, if the first bit of any connection is a 1 value, the receiving node will know that the block data is to be transmitted. I.e., as set forth in the table implemented by the GC controller of fig. 11, three starting byte combinations are utilized: 01. 10 and 11. 00 indicates that no start bits have been sent. Each combination represents a function. In this example, 01 indicates that a relative reduction function should be performed, such as reducing the data block value by 1. 10 indicates that a relative increase function should be performed, such as increasing the data block value by 1. 11 indicates that an absolute value function should be performed while the block remains at the same value. To increase the number of functions available, additional bits may be utilized, e.g., 2 start bits per line may be mapped to seven (7) functions, or n start bits of i lines may be mapped to iⁿ⁺¹-1 function. The processing device 86 follows the start bitThe function is executed on the received data block.

In another implementation as shown in fig. 12, the start bit indicates a destination device. That is, as shown in fig. 13, which is a two destination device/two line implementation, the combination of start bits is associated with the destination device 88-92 for the transferred data block. 01 denotes an apparatus 1; 10 denotes a device 2; and 11 denotes the device 3. After receiving the start bits of the data block reconstruction device 48, the reconstructed block is sent to the corresponding device 88-92. To increase the number of potential destination devices, additional start bits may be utilized. For n start bits on each i lines, up to i may be selectedⁿ⁺¹-1 device.

That is, as shown in fig. 14, both the function and the destination device may be represented by start bits. Fig. 14 shows a three connection system with two devices such as RX and TX GC. Three functions for two devices are plotted in the figure using the start bits on each line. In this example, the start bit of line 1 represents the target device, with "0" being device 1 and "1" being device 2. The bits of connections 2 and 3 represent the function performed. "11" represents an absolute value function; "10" represents the relative increase function; and "01" represents a relative reduction function. All three start bits are zero, i.e., "000", which is a normal non-data-transfer state, and "001" is not used here. Additional bits may be utilized to add more functions or devices. For n start bits on each i lines, up to i may be selectedⁿ⁺¹-1 function/device combination

Fig. 15 is a system block diagram implementing start bits representing both functions and destination devices. The recovered nibbles are received by the data block reconstruction device 48. Based on the received start bits, the processing device 86 performs the function to send the processed block to the destination device 88-92

That is, as shown in the flow chart of fig. 16, start bits indicating the function/destination are added to each nibble (94). Here, the nibbles (96) are sent out via the i-line. Using the start bit, the appropriate function is performed on the data block, which is sent to the appropriate destination or both (98)

To increase throughput in synchronous systems, both the positive (double) and negative (single) edges of the clock signal are utilized to transfer block data. One implementation of which can be seen in fig. 17. The data block demultiplexing device 100 receives the data block and demultiplexes it into two (dual and single) sets of i nibbles. Here, each set of i nibbles is sent to i P/S devices 102, 104 of each respective set. That is, as shown in FIG. 17, a group of single P/S devices 102 will have i P/S devices that have their clock signals inverted by the inverter 118. Thus, the inverted clock signal will be one-half clock signal period delayed relative to the system clock signal. A set of i MUXs 106 selects between the set of dual P/S devices 104 and the set of single P/S devices 102 at twice the clock rate. The production data transmitted over each connection will be twice the clock signal rate. At the other end of each connection is a corresponding DEMUX 108. The DEMUXs 108 sequentially couple each line 44 to a double 112 and single 110 buffer at twice the clock rate. Each buffer 112, 110 receives a corresponding dual and single bit and holds that value for a full clock cycle. A pair 116 and a single 114 set of S/P devices recover the pair and single nibbles. A data block reconstruction device 122 reconstructs the data block from each transmitted nibble.

FIG. 18 illustrates data transfer operations on a system line using the positive and negative clock edges. The icons are double data and single data to be transmitted on line 1. The tapered portion represents the negative clock signal edge in the combined signal, while the non-tapered portion represents the positive. That is, as shown, the data transfer rate is doubled.

FIG. 19 is a preferred implementation of a hybrid parallel/serial interface for use between a GC controller 38 and a GC 124. A data block, such as 16-bit GC control data (8-bit RX and 8-bit TX), is sent from the GC controller 38 to a data block demultiplexing device 40. The data block is demultiplexed into two nibbles, such as two 8-bit nibbles. A start bit is added to each nibble, such as 9 bits for each nibble. Here, the two nibbles are transmitted over two lines using two P/S converters 42. When the S/P converter 46 detects the start bit, it converts the received nibble into a parallel format. The data block reconstruction device reconstructs the original 16 bits to control the gain of the GC 124. As indicated by the start bits, the AGC 124 performs the function on the received block before adjusting the gain, as shown in fig. 11.

Fig. 20 is another preferred implementation of a hybrid parallel/serial bus converter, which is located between the GC controller 38 and an RX GC 30 and TX GC 32, and utilizes three (3) lines. The GC controller 38 sends a data block to the GCs 30, 32 with the appropriate RX and TX gain values and start bits, as shown in fig. 14. If the start bits according to fig. 14 are used, device 1 is RX GC 30 and device 2 is TX GC 32. The data block demultiplexing device 40 demultiplexes the data block into three nibbles for transmission over the three lines. Using three P/S converters 42 and three S/P converters 46, each nibble is serially transmitted over each line and converted to the original nibble. The data block reconstruction device 48 reconstructs the original data block and performs the functions described by the start bits, such as relative increase, relative decrease, and absolute value. The resulting data is sent to the RX or TX GC 30, 32 as described in the start bits.

Claims (57)

1. A hybrid parallel/serial bus interface, comprising:

a data block demultiplexing device having an input configured to receive a data block and capable of demultiplexing the data block into a plurality of nibbles, each nibble having a plurality of bits;

for each nibble:

a parallel-to-serial converter for converting the nibble into serial data;

a line for transmitting the nibble serial data; and

a serial-to-parallel converter for converting the nibble serial data to recover the nibble; and

a data block reconstruction device for merging the recovered nibbles into the data block.

2. The interface of claim 1, wherein the number of bits in a data block is N, the number of lines is i, and 1 < i < N.

3. The interface of claim 1 wherein the number of bits in a nibble is four and the number of lines is two.

4. A hybrid parallel/serial bus interface, comprising:

a device having an input configured to receive a data block to demultiplex the data block into a plurality of nibbles, each nibble having a plurality of bits;

for each nibble:

means for converting the nibbles to serial data;

means for transmitting the nibble serial data; and

means for converting the nibble serial data to recover the nibble; and

means for merging the recovered nibbles into the data block.

5. The interface of claim 4, wherein the number of bits in a data block is N, the number of lines is i, and 1 < i < N.

6. The interface of claim 4 wherein the number of bits in a nibble is four and the number of lines is two.

7. A method for transmitting data, wherein the method comprises:

providing a data block;

demultiplexing the data block into a plurality of nibbles, each nibble having a plurality of bits;

for each nibble:

converting the nibble into serial data;

providing a line and transmitting the nibble serial data on the line;

converting the nibble serial data into parallel data to recover the nibble; and

the recovered nibbles are combined into the data block.

8. The method of claim 7, wherein the number of bits in the data block is N, the number of lines is i, and 1 < i < N.

9. The method of claim 7 wherein the number of bits in a nibble is four and the number of lines is two.

10. A method for transferring a data block over an interface connecting a first node to a second node, the method comprising:

demultiplexing the data block into m sets of n bits;

adding a start bit to the m groups, wherein the m start bits collectively represent a specific mathematical function or destination;

transmitting each of the m sets from the first node over a respective line;

receiving the transmitted m groups at the second node; and

the received m groups are utilized based on these m start bits.

11. The method of claim 10 wherein at least one of the m start bits is in a 1 state and all respective lines are in a 0 state when the interface is not transmitting data.

12. The method of claim 10 wherein the m start bits represent a start of a data transfer operation.

13. The method of claim 10 wherein the m start bits collectively represent a particular mathematical function and not a destination.

14. The method of claim 10 wherein the m start bits collectively represent a function that includes a relative increase, a relative decrease, and an absolute value.

15. The method of claim 10 wherein the m start bits collectively represent a particular destination and not a mathematical function.

16. The method of claim 15 wherein the m start bits collectively represent an RX and TX gain controller.

17. The method of claim 10 wherein the m start bits collectively represent a particular mathematical function and a particular destination.

18. A hybrid parallel/serial bus interface for transferring data from a first node to a second node, wherein the interface comprises:

a data block demultiplexing device for demultiplexing the data block from the first node into m groups of n bits, and adding a start bit to each of the m groups, the m start bits collectively representing a particular mathematical function or destination;

for each of the m groups, a respective line for transmitting the one of the m groups from the first node to the second node; and

a data block reconstruction device for receiving the m groups, combining the m groups into the data block, and utilizing the received m groups according to m start bits.

19. The interface of claim 18 wherein at least one of the m start bits is in the 1 state and all respective lines are in the 0 state when the interface is not transmitting data.

20. The interface of claim 18 wherein the m start bits represent a start of a data transfer operation.

21. The interface of claim 18 wherein the m start bits collectively represent a particular mathematical function and not a destination.

22. The interface of claim 18 wherein the m start bits collectively represent a function that includes a relative increase, a relative decrease, and an absolute value.

23. The interface of claim 18 wherein the m start bits collectively represent a particular destination and not a mathematical function.

24. The interface of claim 23 wherein the m start bits collectively represent includes an RX and TX gain controller.

25. The interface of claim 18 wherein the m start bits collectively represent a particular mathematical function and a particular destination.

26. A hybrid parallel/serial bus interface for transferring data from a first node to a second node, wherein the interface comprises:

means for demultiplexing the block of data into m sets of n bits;

means for appending a start bit to each of the m sets, the m start bits collectively representing a particular mathematical function or destination;

means for transmitting each of said m sets from the first node over a respective line;

means for receiving, at the second node, each of the transmitted m groups; and

means for utilizing the received m groups according to m start bits.

27. The interface of claim 26 wherein at least one of the m start bits is in the 1 state and all respective lines are in the 0 state when the interface is not transmitting data.

28. The interface of claim 26 wherein the m start bits represent a start of a data transfer operation.

29. The interface of claim 26 wherein the m start bits collectively represent a particular mathematical function and not a destination.

30. The interface of claim 26 wherein the m start bits collectively represent a function that includes a relative increase, a relative decrease, and an absolute value.

31. The interface of claim 26 wherein the m start bits collectively represent a particular destination and not a mathematical function.

32. The interface of claim 31 wherein the m start bits collectively represent includes an RX and TX gain controller.

33. The interface of claim 26 wherein the m start bits collectively represent a particular mathematical function and a particular destination.

34. A hybrid parallel/serial bus interface for use in a synchronous system having an associated clock signal, the bus comprising:

a data block demultiplexing device having an input configured to receive a data block and to demultiplex the data block into a plurality of nibbles, each nibble having a plurality of bits;

a pair and a single set of parallel-to-serial (P/S) converters, each set of P/S converters receiving respective nibbles at a clock signal rate synchronized to the clock signal and converting the respective nibbles into a serial data;

a first set of i multiplexers to transfer the dual P/S converter bank serial data at the positive edge of the clock signal on i lines and the single P/S converter bank serial data at the negative edge of the clock signal on i lines;

a second set of i de-multiplexers for receiving the dual and single transmitted serial data and sending the received dual serial data to a dual buffer and the single serial data to a single buffer;

dual and single buffers;

a double and single set of serial-to-parallel (S/P) converters for converting the received double serial data into double parallel data and outputting the double parallel data in synchronization with the clock signal; and

the single set of S/P converters to convert the received single serial data into single parallel data and output the single parallel data in synchronization with the clock signal, an

A data block reconstruction device for merging the dual and single parallel data into the data block.

35. The interface of claim 34, wherein each data block has N bits, and

36. the interface of claim 34 wherein said dual and single buffers buffer said dual and single bank S/P converter inputs so that said dual and single bank S/P converters receive dual and single received serial data in synchronization with said clock signal.

37. A method for determining the number of i bus connections required to transfer block data over a bus, each block of the block data having N bits, the method comprising:

determining a maximum delay allowable for transmitting the data block;

determining a maximum number of connections required to transfer the data block according to the maximum delay; and

the value of i is determined, where i is a value of at least the minimum number of required connections.

38. The method of claim 37 wherein the i bus connections correspond to i pins on a chip.

39. The method of claim 38, wherein 1 < i < N.

40. A system for utilizing a bi-directional serial/parallel bus interface, comprising:

a plurality of lines for transmitting data blocks, the number of the plurality of lines being lower than the number of bits of each data block;

a first node capable of sending data blocks over the plurality of lines to a second node, the first node capable of demultiplexing the data blocks into a plurality of first nibbles, the number of first nibbles being the same as the plurality of lines, each nibble having a plurality of bits; and

the second node sends a second data block to the first node over the plurality of lines, the second node capable of demultiplexing the data block into a plurality of second nibbles, the plurality of second nibbles being the same number as the plurality of lines, each nibble having a plurality of bits.

41. The system of claim 40 wherein the first node is capable of demultiplexing the data block into a plurality of third nibbles, the number j of the third nibbles being lower than the number N of lines, and transmitting the third nibbles over j lines.

42. The system of claim 41 wherein the second node is capable of demultiplexing each fourth block of data into K bits where K is less than or equal to N-j lines and transmitting the fourth block over K lines.

43. The system of claim 40 wherein the first node data block includes gain control information.

44. The system of claim 43 wherein the second node data block includes a gain control information reception acknowledgement.

45. The system of claim 43 wherein the second node data block includes a status information associated with the second node.

46. A Gain Control (GC) system comprising:

a GC controller for generating a data block having n bits representing a gain value;

i lines to transfer the data block from the GC controller to a GC, wherein 1 < i < n; and

the GC is used for receiving the data block and adjusting the gain value of the GC by utilizing the gain value of the data block.

47. The GC system of claim 46, further comprising:

a data block demultiplexing device for demultiplexing the data block into a plurality of nibbles, each nibble being transmitted on a different one of the i lines; and

a data block reconstruction device for merging the nibbles into the data block.

48. The GC system of claim 47 wherein appended to each nibble is a start bit.

49. The GC system of claim 48 wherein the start bits represent a mathematical function.

50. The GC system of claim 49 wherein the mathematical functions represented by the start bits include a relative increase, a relative decrease and an absolute value function.

51. The GC system of claim 48 wherein the GC includes a RX GC and a TX GC and the start bits indicate that the block is to be sent to either the RX GC or the TX GC.

52. A method, comprising:

generating a data block having n bits representing a gain value using a Gain Control (GC) controller;

transmitting the data block from the GC controller to a GC over i lines, where 1 < i < n;

receiving the data block at the GC; and

the GC gain is adjusted by using the gain value of the data block.

53. The method of claim 52, further comprising:

demultiplexing the data block into a plurality of nibbles prior to transmitting the data, each nibble being transmitted on a different one of the i lines; and

after receiving the data block, the nibbles are merged into the data block.

54. The method of claim 53 wherein the appended to each nibble is a start bit.

55. The method of claim 54 wherein the start bits represent a mathematical function.

56. The method of claim 56 wherein the mathematical functions represented by the start bits include a relative increase, a relative decrease, and an absolute value function.

57. The method of claim 53 wherein the GC includes an RX GC and a TXGC, and the start bits indicate that the block is to be sent to either the RX GC or the TX GC.