HK1069905B - User equipment (ue) having a hybrid parallel/serial bus interface - Google Patents

Description

User equipment with hybrid parallel/serial bus interface

Technical Field

The present invention relates to bus data transfer. In particular, the present invention is directed to reducing the number of lines that carry bus data.

Background

An example of a bus for transferring data is shown in FIG. 1. Fig. 1 is an illustration of receive and transmit Gain Controllers (GCs) 30, 32, and a GC controller 38 for a wireless communication system. A communication station, such as a base station or user equipment, Transmits (TX) and Receives (RX) signals. To control the gain of these signals, which falls within the operating range of other receive/transmit components, the GCs 30, 32 adjust the gain on the RX and TX signals.

To control the gain parameters of the GCs 30, 32, a GC controller 38 is utilized. As shown in fig. 1, the GC controller 38 sends the gain values of the TX 36 and RX 34 signals using a power control bus, such as 16-wire buses 34, 36, for example, eight wires each. Although power control bus lines 34, 36 may allow for fast data transfers, they may require multiple pins on the GCs 30, 32 and the GC controller 38, or multiple connections between the GCs 30, 32 and the GC controller 38 on an Integrated Circuit (IC) such as an Application Specific Integrated Circuit (ASIC). Increasing the pin count requires additional board space and connections. Increasing IC connections takes up valuable IC space. The large number of pins or connections may increase the cost of the bus depending on the implementation.

Thus, it is desirable to have other data transfer means.

Disclosure of Invention

According to a first aspect of the present invention there is provided a hybrid parallel/serial bus interface, the bus interface comprising: a data block demultiplexing device having an input configured to receive a data block and to demultiplex the data block into two groups of i nibbles (nibbles), each nibble having a plurality of bits; i even and odd groups of parallel-to-serial converters, each group of i nibbles being sent to a respective group of parallel-to-serial converters synchronized to the clock signal rate of the second clock signal to convert each nibble into a serial data; a first set of i multiplexers serially transfers the even set of parallel-to-serial converters at the positive edge of the second clock signal on i lines and serially transfers data from the odd set of parallel-to-serial converters at the negative edge of the second clock signal on i lines; a second set of i de-multiplexers for receiving the even and odd serial data, and sending the received even serial data to an even buffer, and sending the odd serial data to an odd buffer; even and odd buffers; i an even and an odd set of serial-to-parallel converters for converting the received even serial data into even parallel data and outputting the even parallel data in synchronization with the second clock signal; and a serial-to-parallel converter of the i-odd array for converting the received odd serial data into odd parallel data and outputting the odd parallel data in synchronization with the second clock signal, and a data block reconstruction device for merging the even and odd parallel data into the data block.

According to a second aspect of the present invention there is provided a base station comprising the hybrid parallel/serial bus interface of the first aspect described above.

According to a third aspect of the present invention there is provided a user device comprising the hybrid parallel/serial bus interface of the first aspect described above.

Drawings

Fig. 1 is a schematic illustration of RX and TXGC and GC controllers.

Fig. 2 is a block diagram of a hybrid parallel/serial bus interface.

FIG. 3 is a flow chart of a data block transfer operation using a hybrid parallel/serial bus interface.

Fig. 4 illustrates the demultiplexing of a block into most significant and least significant nibbles.

Fig. 5 illustrates demultiplexing a block using data interleaving.

Fig. 6 is a block diagram of a bi-directional hybrid parallel/serial bus interface.

Fig. 7 is a diagram of a bi-directional line implementation.

Fig. 8 is a timing diagram of start bits.

Fig. 9 is a block diagram of a function controllable hybrid parallel/serial bus interface.

FIG. 10 is a timing diagram of start bits for a function controllable hybrid parallel/serial bus interface.

Fig. 11 is a table showing the implementation of start bits for each function.

Fig. 12 is a block diagram of a destination controlled hybrid parallel/serial bus interface.

Fig. 13 is a list of start bit implementations indicating destinations.

Fig. 14 is a table showing the implementation of start bits for each destination/function.

Fig. 15 is a block diagram of a destination/function control hybrid parallel/serial bus interface.

Figure 16 is a flow chart showing start bits for destinations/functions.

FIG. 17 is a block diagram of a hybrid parallel/serial bus interface for positive and negative clock signal edges.

FIG. 18 is a timing diagram for a hybrid parallel/serial bus interface for positive and negative clock signal edges.

Figure 19 is a 2-wire GC/GC controller bus block diagram.

Figure 20 is a 3-wire GC/GC controller bus block diagram.

Detailed Description

FIG. 2 is a block diagram of a hybrid serial/parallel bus interface, and FIG. 3 is a flow chart of a data transfer operation of the hybrid serial/parallel bus interface. A data block is transmitted across the interface from node 150 to node 252 (54). A data block demultiplexing device 40 receives the block and demultiplexes it into i nibbles for transmission over i data transmission lines 44 (56). The value i is determined by a trade-off between the number of connections and the transfer speed. One way to determine the value of i is to first determine a maximum delay allowed to transmit the data block. Based on this maximum delay, the minimum number of lines required to transmit the block is determined. With a minimum number of lines, the lines used to transmit data are selected to be at least the minimum number. The traces 44 may be pins and their associated connections on a circuit board or on an IC connection. One way to demultiplex into nibbles is to slice the block into a most significant to a least significant nibble. To illustrate in fig. 4, an eight-bit block is transmitted on two lines, which is demultiplexed into a four-bit most significant nibble and a four-bit least significant nibble.

Another way is to interleave the block across i nibbles. The first i bits of the block become the first bit of each nibble. The next i bits become the second bit of each nibble, and so on until the last i bits. To illustrate an eight bit block on two connections as shown in fig. 5, the first bit would be mapped to the first bit of nibble 1. The second bit will be mapped to the first bit of nibble 2. The third bit is mapped to the second bit of nibble 1 and so on until the last bit is mapped to the last bit of nibble 2.

Each nibble is sent to a corresponding one of i parallel-to-serial (P/S) converters 42 (58), converted from parallel bits to serial bits, and serially transmitted in sequence on the line (60). On the opposite side of each line would be a serial-to-parallel (S/P) converter 46. Each S/P converter 46 converts the transmitted serial data into its original nibble (62). The ith recovered nibble is processed by a data block reconstruction device 48 to reconstruct the original data block (64).

On the other hand, bi-directional, i connections are used to transfer data in a bi-directional manner, i.e. as shown in fig. 6. The information data may be transmitted in both directions, or the information may be transmitted in a single direction and the acknowledgement signal may be sent back in the other direction. Here, a data block demultiplexing and reconstruction device 66 receives the data block transmitted from node 150 to node 252. The demultiplexing and reconstruction device 66 demultiplexes the block into i nibbles. The i P/S converters 68 convert each nibble into serial data. A set of Multiplexers (MUX)/DEMUX 71 couples each P/S converter 68 to a corresponding one of the i lines 44. At node 252, another set of multiplexers MUX/DEMUX 75 connects lines 44 to a set of S/P converters 72. The set of S/P converters 72 converts the received serial data of each nibble into the originally transmitted nibble. The received nibbles are reconstructed by a data block demultiplexing and reconstruction device 76 into the original data block and output as the received data block.

For each block transmitted from node 252 to node 150, the data block demultiplexing and reconstruction device 76 receives a data block. The block is demultiplexed into nibbles and each nibble is sent to a set of P/S converters 74. The P/S converter 74 converts each nibble into a serial format for transmission across the i lines 44. MUX/DEMUX 75 of node 2 would couple the P/S converter 74 to i lines 44, while MUX/DEMUX 71 of node 1 would couple lines 44 to i S/P converters 70. The S/P converter 70 converts the transmitted data into its original nibbles. The data block demultiplexing and reconstruction device 66 reconstructs the data block from the received nibbles to output the received data block. Since data is only transmitted in a single direction at a time, this implementation may operate in a half-duplex manner.

Fig. 7 is a simplified diagram of an implementation of a bidirectional switching circuit. The serial output of the node 1P/S converter 68 is input to a tri-state buffer 78. The buffer 78 has another input which is coupled to a voltage representing a high state. The output of the buffer 78 is serial data which is transmitted over line 85 to a node 2 tri-state buffer 84. Resistor 86 is coupled between line 85 and ground. The node 2 buffer 84 passes the serial data to a node 2S/P converter 74. Similarly, the serial output from the node 2P/S converter 74 is input to a tri-state buffer 72. The buffer 72 also has another input coupled to a high voltage. The serial output of the buffer 82 is transmitted to the node 1 tri-state buffer 80 over line 85. The node 1 buffer 80 passes the serial data to a node 1S/P converter 70.

In another implementation, some of the i lines 44 may transmit data in one direction, while other i lines 44 may transmit data in another direction. At node 150, a data block is received for transmission to node 252. Depending on the data throughput rate required for the block and the traffic demand in the other direction, the block is transmitted using j connections, where j is between 1 and i. The block is divided into j nibbles and converted into j sets of serial data using j of the i P/S converters 68. Corresponding j node 2S/P converters 72, and node 2 data block distinguishing and reconstruction device 76, restore the data blocks. In the opposite direction, up to i-j or k lines are used to transmit the data block.

In a preferred implementation of a bi-directional bus for a gain control bus, a gain control value is sent in one direction and an acknowledgement signal is sent back. Alternatively, a gain control value is sent in one direction and a gain control device status signal is sent in the other direction.

A hybrid parallel/serial interface implementation is within a synchronous system and may be as illustrated with reference to fig. 8. A synchronous clock signal is used to synchronize the timing of the various components. To indicate the start of the data block transfer operation, a start bit is sent. I.e., as shown in fig. 8, each line will be at its normal zero level. A start bit is then sent indicating the start of the block transfer operation. In this example, all lines send a start bit, but only one line needs to send a start bit. If the start bit is sent on any line, such as a 1 value, the receiving node knows to start the block data transfer operation. Here, each serial nibble is sent out through its corresponding line. After each nibble is transmitted, the lines return to their normal state, e.g., all low.

In other implementations, the start bits are also used as an indicator of the function to be performed. Such an implementation may be illustrated in fig. 9. As shown in fig. 10, if the first bit of any connection is a 1 value, the receiving node will know that the block data is to be transmitted. I.e., as set forth in the table implemented by the GC controller of fig. 11, three starting byte combinations are utilized: 01. 10 and 11. 00 indicates that no start bits have been sent. Each combination represents a function. In this example, 01 indicates that a relative reduction function should be performed, such as reducing the data block value by 1. 10 indicates that a relative increase function should be performed, such as increasing the data block value by 1. 11 indicates that an absolute value function should be performed while the block remains at the same value. To increase the number of functions available, additional bits may be utilized, e.g., 2 start bits per line may be mapped to seven (7) functions, or n start bits of i lines may be mapped to the shape iⁿ⁺¹-1 function. The processing device 86 performs the function on the received data block as described by the start bits.

In another implementation as shown in fig. 12, the start bit indicates a destination device. That is, as shown in FIG. 13, which is a two-destination device/two-line implementation, the combination of start bits is associated with the destination of the transferred data blockAnd ground devices 88-92. 01 denotes an apparatus 1; 10 denotes a device 2; and 11 denotes the device 3. After receiving the start bits of the data block reconstruction device 48, the reconstructed block is sent to the corresponding device 88-92. To increase the number of potential destination devices, additional start bits may be utilized. For n start bits on each i lines, up to i may be selectedⁿ⁺¹-1 device.

That is, as shown in fig. 14, both the function and the destination device may be represented by start bits. Fig. 14 shows a three connection system with two devices such as RX and TX GC. Three functions for two devices are plotted in the figure using the start bits on each line. In this example, the start bit of line 1 represents the target device, with "0" being device 1 and "1" being device 2. The bits of connections 2 and 3 represent the function performed. "11" represents an absolute value function; "10" represents the relative increase function; and "01" represents a relative reduction function. All three start bits are zero, i.e., "000", which is a normal non-data-transfer state, and "001" is not used here. Additional bits may be utilized to add more functions or devices. For n start bits on each i lines, up to i may be selectedⁿ⁺¹1 function/device combination.

Fig. 15 is a system block diagram implementing start bits representing both functions and destination devices. The recovered nibbles are received by the data block reconstruction device 48. Based on the received start bits, the processing device 86 performs the function to send the processed block to the destination devices 88-92.

That is, as shown in the flow chart of fig. 16, start bits indicating the function/destination are added to each nibble (94). Here, the nibbles (96) are sent out via the i-line. With the start bits, the appropriate function is performed on the data block, which is sent to the appropriate destination or both (98).

To increase throughput in synchronous systems, both the positive (double) and negative (single) edges of the clock signal are utilized to transfer block data. One implementation of which can be seen in fig. 17. The data block demultiplexing device 100 receives the data block and demultiplexes it into two (dual and single) sets of i nibbles. Here, each set of i nibbles is sent to i P/S devices 102, 104 of each respective set. That is, as shown in FIG. 17, a group of single P/S devices 102 will have i P/S devices that have their clock signals inverted by the inverter 118. Thus, the inverted clock signal will be one-half clock signal period delayed relative to the system clock signal. A set of i MUXs 106 selects between the set of dual P/S devices 104 and the set of single P/S devices 102 at twice the clock rate. The production data transmitted over each connection will be twice the clock signal rate. At the other end of each connection is a corresponding DEMUX 108. The DEMUXs 108 sequentially couple each line 44 to a double 112 and single 110 buffer at twice the clock rate. Each buffer 112, 110 receives a corresponding dual and single bit and holds that value for a full clock cycle. A pair 116 and a single 114 set of S/P devices recover the pair and single nibbles. A data block reconstruction device 122 reconstructs the data block from each transmitted nibble.

FIG. 18 illustrates data transfer operations on a system line using the positive and negative clock edges. The icons are double data and single data to be transmitted on line 1. The tapered portion represents the negative clock signal edge in the combined signal, while the non-tapered portion represents the positive. That is, as shown, the data transfer rate is doubled.

FIG. 19 is a preferred implementation of a hybrid parallel/serial interface for use between a GC controller 38 and a GC 124. A data block, such as 16-bit GC control data (8-bit RX and 8-bit TX), is sent from the GC controller 38 to a data block demultiplexing device 40. The data block is demultiplexed into two nibbles, such as two 8-bit nibbles. A start bit is added to each nibble, such as 9 bits for each nibble. Here, the two nibbles are transmitted over two lines using two P/S converters 42. When the S/P converter 46 detects the start bit, it converts the received nibble into a parallel format. The data block reconstruction device reconstructs the original 16 bits to control the gain of the GC 124. As indicated by the start bits, the AGC 124 performs the function on the received block before adjusting the gain, as shown in fig. 11.

Fig. 20 is another preferred implementation of a hybrid parallel/serial bus converter, which is located between the GC controller 38 and an RX GC 30 and TX GC 32, and utilizes three (3) lines. The GC controller 38 sends a data block to the GCs 30, 32 with the appropriate RX and TX gain values and start bits, as shown in fig. 14. If the start bits according to fig. 14 are used, device 1 is RX GC 30 and device 2 is TX GC 32. The data block demultiplexing device 40 demultiplexes the data block into three nibbles for transmission over the three lines. Using three P/S converters 42 and three S/P converters 46, each nibble is serially transmitted over each line and converted to the original nibble. The data block reconstruction device 48 reconstructs the original data block and performs the functions described by the start bits, such as relative increase, relative decrease, and absolute value. The resulting data is sent to the RX or TX GC 30, 32 as described in the start bits.

Claims (3)

1. An interface for a hybrid parallel/serial bus in a synchronous system having an associated first clock signal, the bus interface comprising:

a data area demultiplexing device having an input to receive a data block and to demultiplex the data block into two groups of i nibbles, each nibble having a plurality of bits;

an even group and an odd group of parallel-to-serial converters each having i parallel-to-serial converters, the i nibbles of each group being sent to a corresponding group of parallel-to-serial converters synchronized to a clock signal rate of a second clock signal to convert the received i nibbles to serial data, wherein the second clock signal is a delayed clock signal of the first clock signal;

a first set of i multiplexers to serially transfer the even set of parallel-to-serial converters at the positive edge of the second clock signal over i lines and to serially transfer data from the odd set of parallel-to-serial converters at the negative edge of the second clock signal over i lines;

a second set of i demultiplexers for receiving the even and odd serial data, and sending the received even serial data to an even buffer and the odd serial data to an odd buffer;

an even group and an odd group of serial-to-parallel converters each having i serial-to-parallel converters, the i serial-to-parallel converters of the even group converting the received even serial data into even parallel data and outputting the even parallel data synchronized with the second clock signal; and

the odd set of i serial-to-parallel converters converts the received odd serial data into odd parallel data and outputs the odd parallel data synchronized with the second clock signal, an

A data block reconstruction device for merging the even and odd parallel data into the data block.

2. The interface of claim 1, wherein each data block has N bits, and

3. the interface of claim 1, wherein the even and odd buffers buffer the even and odd sets of deserializers, respectively, such that the even and odd sets of deserializers receive the received even and odd serial data, wherein the received even and odd serial data are synchronized to the second clock signal.