HK1069030A - Automatic frequency correction method and apparatus for time division duplex modes of 3g wireless communications - Google Patents

Description

Automatic frequency correction method and device for time division duplex mode of 3G wireless communication

Technical Field

The invention belongs to the field of wireless communication. More particularly, the present invention pertains to the field of Time Division Duplex (TDD) in the field of third generation wireless communications, and to frequency offset detection and correction correlation in a wireless communication system receiver.

Background

In a typical wireless communication system, the local oscillator frequencies of the transmitter and receiver do not coincide, resulting in data transfer failure. In addition, since many systems utilize the functionality of the same local oscillator for both the receiver and the transmitter, large frequency deviations can result in significant out-of-band interference.

To overcome this problem, previous systems have used phase offset detection or the application of a discrete Fourier transform to estimate the frequency offset and make an operating frequency update to the local oscillator. However, these previous systems either neglect the effects of multipath interference or combine AFC with a RAKE receiver. Therefore, these prior art techniques are not applicable to systems using multi-user detection without a RAKE receiver.

Disclosure of Invention

The present invention can be used to detect and correct oscillator frequency offset in a receiver in a wireless communication system. In addition, the present invention has robust performance in the presence of multipath interference. Also, the present invention can take advantage of the dispersion gain associated with the large amount of delay spread while overcoming the interference. Furthermore, the invention can also be used for resisting interference sources between cells and in the cells, and can still effectively operate under the condition of simultaneous radio frequency carrier deviation and sampling clock deviation. At the same time, the present invention has adaptive adaptation speed and functionality for systems that use multi-user detection algorithms without a RAKE receiver and can operate with intermittent pilot signals.

The invention comprises a frequency estimator having a block correlator, a conjugate product and sum block, an accumulation block, multipath detection, and a loop filter (adaptive bandwidth). Multipath detection comprises a search block, a threshold detection block and a block for combining multipath components.

Drawings

The invention may be understood from the following description and drawings, in which like elements are designated with like reference numerals and in which:

fig. 1 is a block diagram of an Automatic Frequency Control (AFC) algorithm employing the techniques of the present invention.

FIG. 2 is a block diagram illustrating a frequency estimation algorithm according to the present invention.

Fig. 3 and 4 are diagrams illustrating the structure included in each block correlator in fig. 2.

Fig. 5 is a diagram illustrating in detail the conjugate product and sum block of fig. 2.

Fig. 6 is a schematic diagram showing details of the loop filter block of fig. 1.

FIG. 7 is a flow chart showing an algorithm executed by the apparatus of FIG. 2.

Detailed Description

Fig. 1 is a block diagram of a closed loop Automatic Frequency Control (AFC)10 in which a receive signal Rx is reduced to baseband by a Voltage Controlled Oscillator (VCO)14 at a multiplier 12. The receive baseband signal Rx is converted from analog to digital (ADC) at 16, subjected to Automatic Gain Control (AGC) at 18, and then passed through a square cosine root (RRC) filter 20.

After cell search at 22 and frequency estimation at 24, the frequency estimate is applied to loop filter 26. This digital output is converted from digital to analog (DAC) at 28 to adjust the frequency of the voltage controlled oscillator VCO 14, which is also used for transmission, wherein the baseband (BB) Tx data is converted by a digital-to-analog converter (DAC)30 to an analog signal that is used to modulate the carrier frequency provided by the voltage controlled oscillator VCO 14 at multiplier 32.

Fig. 2 is a block diagram showing the steps performed by the frequency estimation block 24, which details the frequency estimation algorithm.

Initially, the frequency estimation algorithm performs four (4) block-related operations on the received signal samples at 24-1 using a known reference value (midamble). The output values of the four block correlators are successively conjugate multiplied at 24-2 to produce three (3) complex numbers whose angles represent the phase shift from one correlator to another in sequence. The three conjugate products are then added to produce a phase change estimate with a smaller variance. The output value of the accumulation block 24-3 is a function of the window lag, i.e., the value accumulated after N frames. After data processing of N frames, the three values with the largest absolute value, D0 (max), D1 and D2, are searched out from the accumulated values D (i) at 24-4. The magnitude of these values is calculated at 24-5 to yield the three largest values of D (i).

A detection threshold is then provided at 24-6 based on the magnitude of the peak (D0). If the magnitude of the second and third largest component values exceeds the threshold, they are considered large enough to be included in the frequency estimation calculation.

After threshold detection is performed, the remaining multipath components are summed uniformly at 24-7 to obtain a complex number whose angle can be used as an estimate of the phase change between correlator blocks. The frequency estimation calculation is performed by blocks 24-8 and 24-9 using two (2) approximation calculations, described below, which avoid direct triangulation.

Fig. 3 illustrates the operation associated with sliding window-blocks. Since the first part of the midamble (midamble) may be bad due to multipath interference of the first data burst (burst), the last 456 chips of the midamble (midamble) are used for frequency estimation. The window sought includes 49 leading, 49 lagging and 0 lagging calibrations. The total number of samples to be processed by the sliding-window block correlator is 1108. In a 3GPP TDD communication system, a 10 millisecond, equal length frame has fifteen (15) equal length slots, each of which has 2560 chips.

In each lag phase, four B chips (2B samples) are correlated, as shown in fig. 3.

The first block correlator generated is shown in detail in figure 4. As shown in fig. 4, each received sample is correlated with a known midamble (midamble) and summed with the next correlation value.

Fig. 5 shows the conjugate product and sum operations at 24-2, which are the processing of the output of the sliding-block window correlator at 24-1. The correlator output R is a complex vector representing the center of the received sample, from which midamble modulation is removed. The next step is to estimate the phase change from one correlator to the next by calculating the conjugate product of two successive correlator outputs. The output of each conjugate product operation is a vector of complex numbers whose angle is approximately equal to the phase change from one correlation center to the next. The three conjugate products from product circuits P1, P2, and P3 are summed at S1 and S2, resulting in a small variance estimate of the phase change from one correlator to the next

The value of d (i) of the conjugate product sum block 24-2 is accumulated after N midambles (midambles) to compute a frequency estimate.

The initial value of the accumulation time constant N is set to 10 and then determined according to the absolute value of the frequency deviation that was last estimated. The value of N is chosen to minimize the variance of the frequency estimate while avoiding significant drift in the estimation interval.

After the N midambles (midambles) have been processed by the sliding-window correlator 24-1, the conjugate product, and sum 24-2, and the accumulator 24-3, a search is made to find a lag i to maximize the value of D (i). Since there may be multiple solvable multipath components, three (3) largest paths will be found, the number of path searches depending somewhat on a trade-off between improvement in signal-to-noise ratio (SNR) and increased hardware complexity.

The second (D1) and third largest (D2) components will be tested as not valid since there is likely only one solvable multipath component. D1 and D2 are considered valid if their squares are greater than half the squares of the DO sizes. Therefore, if D1 and D2 are larger thanThey are accepted, otherwise they are not accepted.

Multipath components meeting the above requirements will then be combined at 24-7 into a phasor whose angle is an estimate of the change in phase of the carrier offset over a block time.

To resolve angle information from the multi-path combined output, the complex variable is scaled to unity and the absolute value of the complex is approximated by an approximation performed such that the imaginary part of the complex vector is equal to the argument of the complex vector, which is equal to θ, and if θ is much less than 1(θ < 1) and the absolute value of the complex vector is 1.

The approximation method simplifies the implementation of the algorithm and alleviates the necessity of performing trigonometric calculations, while the error caused by the approximation method is close to zero due to the convergence of the AFC algorithm (θ → 1).

Loop filter 26 processes the estimated frequency deviation epsilon and performs an integration operation to obtain v (t), which is expressed as follows: v (t) ═ v (t-1) + λ ∈ (t).

This is also depicted in FIG. 6, where the input ε is applied to an amplifier with a gain of-1 and summed at summer S with the previous D_NThe values obtained at v (t-1) are added.

It is noted that the integration operation is only performed after the error epsilon has been discarded in the previous block. Therefore, the value of v changes after being processed by N intermediate codes (midambles). A Convergence Detection Algorithm (CDA) may be used to determine convergence.

One method is to compare the frequency estimate produced at the 24-9 output to a threshold and assume convergence if the estimated frequency deviation is less than a. The algorithm should be memoryless, since convergence is based only on the current estimate of the frequency deviation.

Alternatively, convergence is considered when both (2) successive frequency estimates are below the detection threshold α. Alternatively, the two frequency estimates may not necessarily be consecutive.

Alternatively, if the two-point moving average of the frequency estimates is below the detection threshold, convergence is assumed, or the two most recent frequency estimates obtained at 24-9 are continuously averaged and compared to a threshold.

As for the optimal detection threshold used in block 24-6, the optimal choice of relative detection threshold is 0.56 (i.e., 0.56d (o)) according to the tests already performed, which provides an improvement in the convergence time of 0.65 seconds with a probability of p ═ o.99.

The best choice of loop gain λ depends on the signal-to-noise ratio SNR and the channel conditions. The optimum value of the loop gain is 0.26, which results in a significant improvement in the probability of success for an AWGN channel having a signal-to-noise ratio SNR of-3 dB and two (2) active midambles (midambles).

To prevent loss of consistency during the accumulation interval, the relationship between N and the estimated frequency deviation has been adjusted. The increased value prevents the clock from drifting beyond 0.25 chips during the accumulation period, the value of N being a function of the absolute frequency deviation, the frequency deviation being between 6000 and 0, and N varying between 1 and 30. The lower the absolute frequency deviation, the greater the number N of midambles (midambles) accumulated.

Based on a comparison of 456 chips with 512 chips using a midamble (midamble) in the correlator operation phase, it has been determined that it is better to use all 512 midamble (midamble) chips for all 3 WG4 test channels. The first 56 chips of the midamble (midamble) cancellation are compensated by a 0.5dB reduction in signal-to-noise ratio SNR, since the first 56 chips received may be corrupted by multipath interference due to the initial data burst (burst). For example, for a burst (burst) type 1, there are two groups of data symbols per slot, each group having 976 chips, two (2) groups separated by 512 chips of midamble, and a 96-chip guard segment between each two (2) groups of data symbols.

Previously, the window searched would have 49 leading chips, 49 lagging chips, but no (i.e., 0) lagging calibration chips. The look-ahead path search is more reasonable when there are a total of 10 chips, in which case the total number of samples that the sliding-window block correlator needs to process is 1142 samples, and the window size reduction is acceptable even in the worst-case (case 2) multipath WG4 channel mode, in which case the maximum resolvable path is 46Tc, compared to the direct path delay.

One of the multipath combining schemes used in blocks 24-6 and 24-7, in which the largest path, D0, is weighted twice the second largest in the case where only two paths remain, is to subject the two paths to the same gain, and a comparison of the two schemes shows that the same gain combining scheme performs slightly better in WG4 case 1, but otherwise the two schemes perform equally, so that the second scheme would be preferred when only D (0) and D (1) are combined.

The invention can also be implemented using another method of estimating the phase difference (which is based on a complex of multiple multipath components). In this case, the phase estimate will still include a quality measure of similar magnitude to the correlation used in the invention.

The method for adjusting the accumulation period (adaptive adjustment rate) can also be applied to the adjustment of the relevant block size. For larger frequency deviations, it is preferable to use smaller correlation block sizes, which reduces the likelihood of aliasing and loss of consistency in the estimation process. As the frequency offset decreases, the size of the correlation block may increase to improve the processing gain of the correlation and obtain a more accurate frequency offset estimate.

Claims (43)

1. A method of obtaining a frequency estimate for adjusting a local oscillator, comprising:

a) receiving a communication signal comprising time slots, which comprise data symbols and a midamble;

b) performing a predetermined number N of block correlations of the received signal samples with reference to a known midamble;

c) forming a conjugate product of the N block correlations to form N-1 conjugate products;

d) forming a sum of N-1 conjugate products;

e) accumulating a number of the sums of the N-1 conjugate products obtained in step (d);

f) judging the size of each accumulated value;

g) finding a certain number of maximum values;

h) performing a threshold detection on a number of maxima, none of the maxima including a maximum using a threshold that is a function of the maximum;

i) combining the maximum value with a number of those maximum values, not including the maximum values greater than the critical values mentioned above;

j) (ii) calculating the magnitude of the sum obtained in step (i);

k) (ii) using the magnitude obtained in step (j) to normalise the complex values obtained in step (i); and

l) using the parameters of the standard values obtained in step (k) as a frequency estimate.

2. The method of claim 1, further comprising:

m) supplying the frequency estimation obtained in step (1) to a loop filter to obtain a voltage value for adjusting the operating frequency of a voltage controlled oscillator.

3. The method of claim 2 wherein the frequency estimate obtained in step (m) is in a digital format and further comprising:

n) converting the digital format to an analog voltage.

4. The method of claim 3, further comprising:

o) applying the analog voltage to a voltage controlled oscillator.

5. The method of claim 1, wherein step (b) comprises performing four (4) block-related operations, i.e., N-4.

6. The method of claim 1, wherein step (e) comprises adjusting the number of accumulated sums based on an absolute frequency deviation, wherein the smaller the frequency deviation, the smaller the number of accumulated sums.

7. A method as claimed in claim 6, characterised in that the absolute frequency deviation is in the range of typically 6000 and 0 Hz.

8. The method of claim 7, wherein the number of accumulated sums is between 1 and 30.

9. The method of claim 1, wherein the (f) th to (l) th steps are performed when the number of accumulated sums reaches a predetermined number in the (e) th step.

10. The method of claim 1 wherein the threshold used in step (h) is between 0.707 times the maximum D value and 0.56 times the maximum threshold.

11. The method of claim 1 wherein the received signal in step (a) has a midamble length of 512 chips, all of which are correlated in step (b).

12. The method of claim 1, wherein the received signal in step (a) has a midamble length of 512 chips and the first 56 chips are ignored in performing the correlation operation of step (b).

13. The method of claim 1 wherein if only one path meets the threshold of step (i), step (i) further comprises combining the two paths using the same gain

14. The method of claim 1 wherein convergence to a desired accuracy with a probability of 0.99 for a given number of frames depends on comparing the estimated frequency deviation to a threshold, wherein convergence is indicated when the estimated frequency deviation is below a given detection limit threshold.

15. The method of claim 1 wherein if both frequency offset estimates are below a given detection threshold, it indicates that the required accuracy has been determined with a probability of 0.99 over a given number of frames.

16. The method of claim 1 wherein if two consecutive frequency offset estimates are below a given detection threshold, it indicates that the required accuracy has been determined with a probability of 0.99 over a given number of frames.

17. The method of claim 1 wherein if a two-point moving average frequency offset estimate falls below the given detection threshold, it indicates that the required accuracy has been determined with a probability of 0.99 over a given number of frames.

18. The method of claim 1, wherein a frequency offset is measured and the Broadcast Channel (BCH) is read when the frequency offset is less than 400 Hz.

19. The method of claim 18 further comprising preventing detection of BCH when the absolute frequency offset threshold is equal to or greater than 465 Hz.

20. The method of claim 1, wherein the loop filter has a loop gain between 0.1 and 0.3.

21. The method of claim 20 wherein the desired loop gain is 0.26.

22. A method as claimed in claim 1, wherein the estimate of the angle θ is determined in step (i) by the following equation:

23. the method of claim 1, wherein the loop filter generates a value v (t), wherein:

v(t)＝v(t-1)+λε(t)，

where v (t-1) is the previous estimate, ε is the frequency estimate, and λ is a constant.

24. The method of claim 1 wherein the communication system is a wireless communication system and wherein the received signal is comprised of a plurality of equal length frames, each frame having a predetermined fixed number of time slots, each time slot having a fixed number of chips.

25. The method of claim 24, wherein each slot has 2560 chips and comprises first and second sets of data symbols separated by an intermediate code.

26. The method of claim 25 wherein each group of data symbols comprises 976 data symbols and the midamble has 512 chips and the group of data symbols after the midamble has a guard period of 96 chips.

27. An apparatus for obtaining a frequency estimate for adjusting a local oscillator, comprising:

means for receiving a communication signal, the communication signal comprising time slots, the time slots comprising data symbols and a midamble;

means for performing a predetermined number, N, of block correlations of the received signal samples with reference to a known midamble;

means for forming a conjugate product from the N block-related products to form N-1 conjugate products;

means for forming a sum of N-1 conjugate products;

means for accumulating a given number of sums of the N-1 conjugate products derived from the sum forming means;

means for determining the magnitude of each cumulative value;

means for finding a given number of maxima;

means for performing threshold detection for a given number of maxima, none of the maxima including the maximum using a threshold that is a function of that maximum;

means for combining a given number of maxima, those maxima not comprising a maximum greater than the above-mentioned threshold;

means for summing the values obtained from the combining means;

means for normalizing the complex values from the combining means using the magnitudes from the computing means; and

means for generating a parameter as a frequency estimate from the normalized value obtained by the normalizing means.

28. The apparatus of claim 27, further comprising:

the generating means supplies the frequency estimate to a loop filter for adjusting the operating frequency of a voltage controlled oscillator.

29. The apparatus of claim 28 wherein the means for generating the frequency estimate generates an output in a digital format, and the means for converting converts the output in the digital format to an analog signal and applies it to the vco.

30. The apparatus of claim 27 wherein the block correlation means comprises means for performing four (4) block correlation operations.

31. The apparatus of claim 27, wherein the accumulating means includes means for adjusting the number of accumulated sums, and the adjustment of the number of sums is based on the magnitude of the absolute value of the frequency deviation, and the smaller the frequency deviation, the smaller the number of accumulated sums.

32. The apparatus of claim 27 wherein the threshold detection means uses a threshold value between 0.707 times the maximum D value and 0.56 times the maximum threshold value.

33. The apparatus of claim 27 wherein the received signal has a midamble length of 512 chips, all of the chips being correlated at the correlating means.

34. The apparatus of claim 27 wherein means determines whether only one path meets the threshold, the threshold being provided by threshold detection means, and means responsive to the determining means for combining the two paths with the same gain.

35. The apparatus of claim 27 wherein convergence to a desired accuracy with a probability of 0.99 over a given number of frames is determined by a means for comparing the estimated frequency offset to a threshold, wherein convergence is indicated if the estimated frequency offset is below a given detection threshold.

36. The apparatus of claim 27 wherein convergence to a desired accuracy with a probability of 0.99 for a given number of frames is determined by means for identifying convergence when two (2) frequency offset estimates are below a given detection threshold.

37. The apparatus of claim 27 wherein convergence to a desired accuracy with a probability of 0.99 for a given number of frames is determined by means for identifying convergence when two (2) consecutive frequency offset estimates are below a given detection threshold.

38. The method of claim 27 wherein convergence to a desired accuracy over a given number of frames with a probability of 0.99 is determined by means for identifying convergence when a two-point moving average frequency offset estimate is below a given detection threshold.

39. The apparatus of claim 27, further comprising means for measuring a frequency offset and means for reading a Broadcast Channel (BCH) when the frequency offset is less than 400 Hz.

40. The method of claim 1, wherein the given number of maxima sought in step (g) is three (3).

41. The apparatus of claim 27 wherein said searching means is adapted to search for three (3) maximum values.

42. The method of claim 1, wherein step (b) comprises adjusting the size of the block correlation based on the magnitude of the frequency offset, wherein the larger the offset, the smaller the size of the block correlation.

43. The method of claim 27 wherein the performing means includes means for adjusting the size of the block correlations based on the magnitude of the frequency offset, the larger the offset, the smaller the size of the block correlations.