HK1069031A

HK1069031A - Code tracking loop with automatic power normalization

Info

Publication number: HK1069031A
Application number: HK05101383.8A
Authority: HK
Inventors: Aykut Bultan; Donald Grieco
Original assignee: Interdigital Technology Corporation
Priority date: 2001-10-01
Filing date: 2002-04-15
Publication date: 2005-05-06

Description

Code tracking loop with automatic power normalization

Technical Field

The invention relates to a code tracking system, which is applied to a receiving device of a Code Division Multiple Access (CDMA) communication system. More particularly, the present invention relates to a two-level code tracking system for more efficiently removing timing differences between transmitted codes and received codes.

Background

Synchronization is an important task in any type of telecommunications. Synchronization is of a variety of levels, such as: carrier, frequency, code, symbol, frame, and network synchronization. In all levels, synchronization can be divided into two phases, namely: acquisition (initial synchronization) and tracking (fine synchronization) stages.

A typical wireless communication system transmits a downlink from a base station to one or more User Equipments (UEs) and transmits an uplink from the User Equipments (UEs) to the base station. A receiving device within the User Equipment (UE) uses correlation, or despreading (desread), to receive the downlink signal and a known code sequence for its operation. The sequence must be precisely synchronized to the received sequence to obtain maximum output from the correlation device. The receiving device should be able to easily adapt to a change in the environment of a radio line change without halting operation. To achieve this, the receiving device collects as much transmitted signal energy as possible to maximize the signal-to-noise ratio (SNR). However, in a multipath fading channel, the signal energy is despread (despred) for a certain amount of time due to the different echo paths and scattering. Therefore, a crucial task of the receiving device is to estimate the channel to improve its performance. If the receiving device has information about the channel profile, then one method of harvesting signal energy is to assign multiple associated devices to branch on different echo paths and constructively combine their outputs, i.e.: a structure of a RAKE receiving apparatus is known.

The RAKE receiver has a plurality of fingers, one for each echo path, and in each finger, the path delay with respect to a partial reference delay, such as a direct or earliest receive path, must be estimated and tracked over the entire transmission. The estimate of the starting position of the path in time can be obtained by using a multi-path search algorithm. The multi-path search algorithm performs an extended search through correlation devices to place the paths with a chip accuracy. After the start positions are found, the tracking units generate accurate estimates of the delays of the multipath components by means of early delay timing error detection devices and apply the estimates of the different delays to shift the phase of the codes. This type of tracking unit is known as an early delay gate (gate) synchronizer. A Delay Locked Loop (DLL) is often used to implement this early delay gate synchronization device. A block diagram of the Delay Locked Loop (DLL) is presented in fig. 1. The bandwidth of the Code Tracking Loop (CTL) determines the noise filtering capability of the synchronization device. The narrower the bandwidth, the higher the robustness of the synchronization device against noise distortions and the lower the sensitivity to small signal variations. The bandwidth of the loop is determined by the parameters (alpha, beta) of the loop filter, the overall loop gain (K)_T) And input signal power level (P)_in). The damping ratio of this circuit is also dependent on the same parameters. The damping ratio of the circuit determines the stability of the circuit. Although the parameters of the loop can be fixed, it is difficult to fix the input signal level.

Most discontinuous reception devices apply a partial form of Automatic Gain Control (AGC) in their physical layer. Although Automatic Gain Control (AGC) limits the input signal level (level), the dynamic level of this signal level is still broad. This is due to the fact that Automatic Gain Control (AGC) is actually designed to avoid the analog discontinuous conversion device (ADC) going into saturation.

Since the dynamic range of the input signal level is not efficiently limited, the bandwidth and damping ratio of the code tracking loop vary with the input signal power. This will lead to a degradation of the performance of the code tracking loop.

Thus, there is a need for a code tracking loop that maintains the bandwidth and damping ratio of the loop regardless of changes in the input signal power level.

Other objects and advantages of the present invention will become more apparent after a reading of the preferred embodiments of the present invention.

Disclosure of Invention

The present invention is a receiving device of a Code Division Multiple Access (CDMA) communication system, which is included in a User Equipment (UE), the CDMA communication system comprising: the User Equipment (UE) and a plurality of base stations. The User Equipment (UE) communicates with one of the base stations and receives a communication signal from the base station via the receiving device. The communication signal is correlated with the receiving device using a delay locked code tracking loop that estimates and tracks a channel delay of the communication signal. The tracking loop comprises: a reference code generating device for generating a reference code signal; and an interpolation device for generating the timing signal version in response to the receipt of the communication signal. A timing signal correlation device, also included in the tracking loop, correlates at least two of the versions of the timing signal with the code reference signal. The result of the correlation step is used to generate an error signal. An automatic power normalization loop (APN) responsive to the interpolation means generates a power error signal for normalizing the error signal via a normalization circuit.

Drawings

Fig. 1 is a block diagram of a conventional dll.

FIG. 2 is a block diagram of a delay locked code tracking loop with automatic power normalization in accordance with the present invention.

FIG. 3 is a flowchart of the delayed locking tracking loop of the present invention.

FIG. 4 is a block diagram of an exemplary loop filter apparatus included in the delay locked code tracking loop of the present invention.

Detailed Description

The preferred embodiments are described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout.

Illustrated in fig. 2 is a block diagram of a delayed code lock tracking loop (DCTL)10 in accordance with a preferred embodiment of the present invention. The Delayed Code Tracking Loop (DCTL)10 includes: an interpolation means 11, two integrating and damping means 12a, 12b, two squaring means 13a, 13b, a normalizing means 14, a loop filter means 15, a code generating means 16, an accumulating means 17, a limiting means 18, a quantizing means 19, a gain circuit 9, and an automatic power normalization loop (APN) 20. The delay locked code tracking loop (DCTL)10 receives an input signal x (T-T), where T is the timing error in the received signal. Since the timing error is limited to-Tc to Tc, where Tc is the chip period of the multipath searching algorithm, the only way to shift the incoming signal is by mathematical interpolation. Thus, the interpolation means 11, which is coupled to the integration means 12a, 12b, the code generation means 16, and the automatic power normalization loop (APN)20, receives the input signal x (T-T) and generates three outputs: accurate, early, and delayed. As is well known to those skilled in the art, these early and delayed outputs are a half-chip early version and a half-chip late version of the incoming signal x (T-T), respectively. These versions are obtained by interpolation of the incoming signal x (T-T). After the interpolation means 11 down-sampling is performed, the three outputs are down-sampled preferably by an up-sampling ratio of the transmitted signal. The precise outputs of the delay locked code tracking loop (DCTL)10, these early and delayed outputs are used only within the algorithm of the code tracking loop 10.

The early and delayed signals are correlated with the output of the reference code generating device 16, such as a pilot code generating device, in the lower and upper branches of the Delayed Code Tracking Loop (DCTL)10 by the integrating devices 12a, 12b, respectively. Once the output of the code generation means 16 and the early and late outputs have been correlated, the correlation signals are forwarded to squaring means 13a, 13b, respectively. Since phase synchronization is not required at this stage, squaring is used to obtain a non-coherent Code Tracking Loop (CTL).

After correlation and squaring, the difference between the two branches (early and delayed) is used to generate an error signal e (t) that is proportional to the timing error. The error signal e (t) is then power normalized with respect to a power error signal (Pe) by the normalization circuit 14 (described further below) and output to the loop filter 15.

The loop filter means 15, which are coupled to the normalizing circuit 14 and to the accumulating means 17, filter the normalized error signal e (t) and forward it to the accumulating means 17. An exemplary loop filter device is a conventional proportional integral device (PI) filter device, but any first order low pass filter device may be suitable for use in the present invention. The proportional integral device (PI) filter, which includes a loop filter summation device 41, has two branches, as shown in FIG. 4. One branch generates a control signal proportional to the current value of the error signal, and the other branch generates a signal proportional to the average value of the error signal. These signals are combined after multiplying two different constants (alpha and beta). The summation device 41 in the filter device of the proportional integral device (PI) is performed in exactly the same way as the summation device 17 described below.

The summation device 17, coupled to a gain circuit 9, receives the filtered error signal of the loop filter device 15 and processes the signal. Those skilled in the art will appreciate that the summation device 17 simply adds its current input to its previous output. At the start, the output of the summation device 17 is set to zero. Inside the accumulation device, there is an overflow (overflow) detection to limit the output value. The summation action of the summation device 17 is used together with the loop filter device 15 to obtain a second order feedback loop response. The summation means 17 then forwards the error signal e (t) to the gain circuit 9.

The gain circuit 9, which is coupled to the summing device 17 and a limiting device circuit 18, receives the output of the summing device 17 and adjusts the level of the filtered signal to match the interpolation device 11 timing shift value. This circuit changes the sign in the timing air (air) signal to correct the timing delay/lead of the incoming signal referenced by the code generation device 16. Once this is done, the gain circuit 9 forwards the adjusted error signal e (t) to a limiting device circuit 18, which limits the overshoot of the error signal when it exceeds the chip period (-Tc to Tc). The limiting means 18 forward the error signal to the quantizing means 19, wherein discrete values of the delay estimate are taken and returned to the interpolating means 11. In this design, a thirty-second quantization device is used to achieve an accuracy of Tc/16. Although any level of quantization may be used with varying levels of delay estimation accuracy.

The delay locked code tracking loop (DCTL) is a second order feedback loop. In the control system signature, the system function of a second order feedback loop, h(s), can be expressed as:

equation (1)

Where ζ is the damping ratio (damping ratio) and ω is_nIs the natural frequency of the system. These are parametric representations of the delay locked code tracking loop (DCTL) that can be used, as follows:

equation (2)

Equation (3)

Wherein, alpha and beta are the parameters of the loop filter, K_T＝K_SK is the overall loop gain, which includes: s-curve gain and external gain, and P_inIs the input signal power.

The bilateral noise bandwidth of this system is expressed as:

equation (4)

For example, a Universal Mobile Telecommunications System (UMTS) Frequency Division Duplex (FDD) User Equipment (UE) receiver design with a chip rate of 3.84MHz and twice upsampling uses the following values: the spreading factor 256 of the pilot code, the loop gain K is 0.01, α is 0.0141, and β is 0.00001. The value of the natural frequency and the damping ratio (damping ratio) are the main characteristics that determine this loop, such as: stability, gain and phase boundaries, bandwidth, convergence time, and steady state jitter. These features are fixed during design and should not change as a result of input. Otherwise, the delay locked code tracking loop (DCTL) may malfunction and produce unexpected results. However, as seen in equations (2), (3), (4), these characteristics are dependent on the input signal power, P_inWhich may vary considerably during the communication process.

To overcome the effect of the power level variation of the input signal x (T-T), an automatic power normalization loop (APN)20 is included in the delay-locked tracking loop 10 of the present invention. The automatic power normalization loop (APN)20, coupled to the interpolation device 11, includes: an integrating and damping circuit 21, a squaring device 22, an adding device 24, and a Moving Average (MA) filtering device 23. The precise output of the interpolation means 11 is the input of the automatic power normalization loop (APN) 20. The accurate signal is received by the integrating and damping circuit 21 following the signal from the code generating device 16. The integrating and damping circuit 21 is coupled to the code generating device 16, the interpolating device 11, and the squaring device 22. Similar to the integration and damping circuits 12a, 12b disclosed previously, the integration and damping circuit 21 correlates the accurate signal received by the interpolation means 11 and the signal received by the reference code generation means 16. Once the two signals are correlated, the integration circuit 21 forwards the correlated signal to the squaring device 22.

The squaring device 22, coupled to the integrating circuit 21 and the adding device 24, squares the correlation signal and forwards the squared signal to the adding device 24. The summing device 24 subtracts the squared output of the squaring device 22 from a reference signal power (P), which is a predetermined value and is used in the design of the Delay Locked Loop (DLL)10 to set parameters. As will be appreciated by those skilled in the art, the reference power level (P) may be any predetermined value. Subtracting the squared signal by the adding means 24 results in a power difference signal which is forwarded to the Moving Average (MA) filtering means 23.

The Moving Average (MA) filter 23, which is coupled to the summing device 24 and the normalization circuit 14, receives and filters the difference signal. The Moving Average (MA) filter 23 includes: a real number register of size N, an adder, and a constant multiplier with a factor of 1/N. The register elements are shifted one element to the right each time a new input is passed to the Moving Average (MA) filter 23. The earliest arriving component (on the far right) is cleared and the current number of inputs is placed in the far left position of the register. After the translation, each component in the register is added. The overall value is multiplied by 1/N to produce an average value of the power error signal (Pe). In some embodiments, the value N is preferably chosen to be twenty, which corresponds to twenty processed symbols. The size of the Moving Average (MA) filtering means is selected so that it is insensitive to real-time power variations due to fading, yet compensates for average input signal level variations. Once the power difference signal is filtered by the Moving Average (MA) filter 23, a filtered power error signal Pe is forwarded to the normalization circuit 14.

The normalization circuit 14, which is coupled to the squaring means 13a, 13b and the automatic power normalization loop (APN)20, receives the error signal e (t), which corresponds to the difference between the delayed and early output of the interpolation means 11 and the power error signal Pe of the automatic power normalization loop (APN) 20. To normalize the error signal e (t) with respect to the power error signal Pe, the normalization circuit 14 multiplies the error signal e (t) by (P)/(P + Pe), where P is the reference signal power level used in the automatic power normalization loop (APN) 20.

Normalization of the error signal (rather than the input signal) results in a reduced number of multiplications (normalizations) by a factor equal to the expansion factor. In the preferred embodiment, a limiting device (not shown) can be minimally integrated into the normalization circuit to limit the multiplication factor to 0.1 to 10 or-20 dB to 20 dB. The limiting device is used to avoid noise amplification.

FIG. 3 is a flow chart illustrating a delay locked code tracking loop according to a preferred embodiment of the present invention. An input signal is received by the Delay Locked Loop (DLL)10 (step 301). The interpolation device 11 of the Delay Locked Loop (DLL)10 generates a delayed, early, accurate output (step 302). The delayed and early outputs are correlated by the code generation means 16 (step 303a) and the difference between the correlated signals is determined, thereby generating an error signal e (t) (step 304 a). In synchronization with the delayed and early outputs, the accurate output is correlated by the code generation means (step 303b) and subtracted from a predetermined reference power level to generate a power level difference signal (step 304 b). The power level difference signal is then filtered to generate a power level error signal Pe (step 305 b). The error signals corresponding to these delays and early outputs are normalized against the power level error signal Pe of the automatic power normalization loop (APN)20 (step 306). The normalized error signal is then processed and a delay estimate is generated (step 307), which is forwarded back to the input of the Delay Locked Loop (DLL) tracking loop 10 (step 308).

While the invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made without departing from the scope of the invention, which is set forth in the following claims.

Claims

1. A Code Division Multiple Access (CDMA) communication system, comprising: a plurality of communication base stations, at least one base station comprising: a receiver for receiving a communication signal from another base station, wherein the communication signal is correlated with the receiver using a delay locked code tracking loop for estimating and tracking a channel delay of the communication, the tracking loop comprising:

a reference code generating device for generating a reference code signal;

an interpolation device for generating a base version and time-shifted versions of the received communication signal;

a timing signal correlation device for correlating each of the versions of the time shifted signal with the code reference signal and combining the correlations to generate an error signal;

an automatic power normalization loop (APN) for generating a power error signal according to the version of the basic signal and the reference code signal; and

a normalization circuit for normalizing the error signal by the power error signal to generate a normalized error signal, which is applied to control the generation of the version of the base signal by the interpolation means.

2. The system of claim 1, wherein the automatic power normalization loop (APN) comprises:

an automatic power normalization loop (APN) correlation device for correlating the base signal version with the reference code signal to generate a correlation signal;

an adder for subtracting the correlation signal from a power reference signal to generate a power difference signal; and

a filter responsive to the adder for filtering the power difference to generate the power error signal.

3. The system of claim 2 wherein the tracking loop further comprises:

a loop filter coupled to the normalization circuit for filtering the normalized error signal;

an accumulation device, responsive to the loop filter, for accumulating the error signal;

a gain circuit, coupled to the summing device, for changing a sign of the error signal to correct a timing delay/lead of the received communication signal to the reference code signal; and

a quantization device for generating a discrete value of the delay/lead, thereby controlling the generation of the basic signal by the interpolation device.

4. The system of claim 2, wherein the time-shifted versions are an early version and a late version of the base version.

5. The system of claim 4 wherein the early version is a half-chip early version of the base version and the late version is a half-chip late version of the base version.

6. A delay locked code tracking loop for estimating and tracking a channel delay of a communication in a Code Division Multiple Access (CDMA) communication system, the CDMA communication system comprising: a plurality of communication base stations, at least one base station comprising: a receiver including the tracking loop for receiving the communication from another base station, wherein the communication signal is correlated with the receiver using the tracking loop, the tracking loop comprising:

a reference code generating device for generating a reference code signal;

7. The tracking loop of claim 6 wherein said automatic power normalization loop (APN) comprises:

8. The tracking loop of claim 7 further comprising:

9. The tracking loop of claim 7 wherein said time-shifted versions are an early version and a late version of said base version.

10. The tracking loop of claim 9 wherein said early version is a half-chip early version of said base version and said late version is a half-chip late version of said base version.

11. A method of estimating and tracking a channel delay of a communication in a Code Division Multiple Access (CDMA) communication system, the CDMA communication system comprising: a plurality of communication base stations, at least one base station comprising: a receiver for receiving the communication signal from another base station, wherein the communication signal is correlated with the receiver using the delay locked tracking loop, the method comprising:

generating a reference code signal;

interpolating the received communication signal to generate a base version of the communication signal and time-shifted versions thereof;

correlating each of the time-shifted signal versions with the code reference signal and combining the correlations to generate an error signal;

generating a power error signal according to the version of the basic signal and the reference code signal; and

the error signal is normalized by the power error signal to generate a normalized error signal, which is used to control generation of the version of the base signal.

12. The method of claim 11 wherein the step of generating a power error signal comprises the steps of:

correlating the version of the basic signal with the reference code signal to generate a correlation signal;

subtracting the correlation signal from a power reference signal to generate a power difference signal; and

the power difference is filtered to generate the power error signal.

13. The method of claim 12, further comprising the steps of:

filtering the normalized error signal;

accumulating the error signals;

changing the sign of the error signal to correct a timing delay/lead of the received communication to the reference code signal; and

generating a discrete value of the delay/lead to control generation of the version of the base signal.

14. The method of claim 11, wherein the time-shifted versions are an early version and a late version of the base version.

15. The method of claim 14 wherein the early version is a half-chip early version of the base version and the late version is a half-chip late version of the base version.