HK1067788B - A semiconductor device and its manufacturing method - Google Patents

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device incorporating a chip-size semiconductor element and a method for manufacturing the same.

Background

In recent years, semiconductor devices called CSPs (chip size packages) have been developed for the miniaturization of portable electronic devices such as mobile phones. The CSP is the following device: a passivation film (intermediate insulating film) is provided on the upper surface of a bare semiconductor device on which a plurality of connection pads (pads) for external connection are formed, an opening is formed in a corresponding portion of each connection pad of the passivation film, rewirings connected to the connection pads through the openings are formed, columnar external connection electrodes are formed on the other end portions of the rewirings, and a sealing member is filled in the external connection electrodes. Thus, if the CSP is used, the solder balls (solder balls) are formed on the columnar external connection electrodes, so that the circuit board having the connection terminals can be bonded face down, and the mounting area can be made the same as the size of the bare semiconductor device. As described above, in the CSP, for example, USP6467674 is known, and in order to improve productivity, there is a CSP in which a passivation film, a rewiring, an electrode for external connection, and a sealing member are formed on a semiconductor substrate in a wafer state, and a solder ball is formed on an upper surface of the electrode for external connection exposed without being covered with the sealing member, and then the semiconductor substrate is cut in a dicing line.

However, in the above conventional semiconductor device, as integration progresses, the number of external connection electrodes increases, which causes the following problems. That is, as described above, since the CSP has the external connection electrodes arranged on the upper surface of the bare semiconductor device, it is generally arranged in a matrix, and therefore, in the case of a semiconductor device having a large number of external connection electrodes, there is a disadvantage that the size and pitch of the external connection electrodes are extremely small. That is, if the size and pitch of the external connection electrodes are extremely small, it is difficult to fit the positions of the external connection electrodes to the circuit board, and there are fatal problems such as insufficient bonding strength, short circuit between the electrodes during bonding, and breakage of the external connection electrodes due to stress caused by a difference in linear expansion coefficient between the semiconductor substrate, which is usually a silicon substrate, and the circuit board.

Disclosure of Invention

Accordingly, an object of the present invention is to provide a novel semiconductor device in which the size and pitch can be made necessary even if the number of external connection electrodes is increased.

The semiconductor device according to the present invention includes: a semiconductor construct (3) having a plurality of external connection sections (11) on the upper surface; an insulating member (13) which is provided on the side of the semiconductor construct (3) and is made of a resin containing a reinforcing material; an insulating film (14) provided on the upper surface of the semiconductor construct (3) except for the external connection portion (11) and on the upper surface of the insulating member (13); and a plurality of upper layer re-wirings (16 or 19) which are provided on the insulating film (14) so as to be connected to the external connection portions (11) of the semiconductor construct (3), respectively, and which have at least one connection pad portion; at least a part of the connection pad portion of the uppermost upper redistribution layer (19) among the upper redistribution layers (16 or 19) is provided in a region corresponding to the insulating member (13).

Drawings

Fig. 1 is a sectional view of a semiconductor device which is embodiment 1 of the present invention.

Fig. 2 is a cross-sectional view of a device prepared in an initial stage in one example of a method of manufacturing the semiconductor device shown in fig. 1.

Fig. 3 is a cross-sectional view of the device following the manufacturing process of fig. 2.

Fig. 4 is a cross-sectional view of the device following the manufacturing process of fig. 3.

Fig. 5 is a cross-sectional view of the device following the manufacturing process of fig. 4.

Fig. 6 is a cross-sectional view of the device following the manufacturing process of fig. 5.

Fig. 7 is a cross-sectional view of the device following the manufacturing process of fig. 6.

Fig. 8 is a cross-sectional view of the device following the manufacturing process of fig. 7.

Fig. 9 is a cross-sectional view of the device following the manufacturing process of fig. 8.

Fig. 10 is a device cross-sectional view of the manufacturing process of the upper connection 9.

Fig. 11 is a cross-sectional view of the device following the manufacturing process of fig. 10.

Fig. 12 is a cross-sectional view of the device following the manufacturing process of fig. 11.

Fig. 13 is a cross-sectional view of the device following the manufacturing process of fig. 12.

Fig. 14 is a cross-sectional view of the device following the manufacturing process of fig. 13.

Fig. 15 is a cross-sectional view of the device following the manufacturing process of fig. 14.

Fig. 16 is a cross-sectional view of the device following the manufacturing process of fig. 15.

Fig. 17 is a cross-sectional view of the device following the manufacturing process of fig. 16.

Fig. 18 is a sectional view of a substrate prepared in an initial stage, showing modification 1 of the method for manufacturing the semiconductor device shown in fig. 1.

Fig. 19 relates to modification 1 shown in fig. 18, and is a device cross-sectional view of a main part of a manufacturing process.

Fig. 20 is a device cross-sectional view showing a main part of a manufacturing process in modification 2 of the method for manufacturing the semiconductor device shown in fig. 1.

Fig. 21 is a sectional view of the manufacturing process in the above fig. 20.

Fig. 22 is a device cross-sectional view showing a main part of a manufacturing process in modification 3 of the method for manufacturing the semiconductor device shown in fig. 1.

Fig. 23 is a device cross-sectional view showing a main part of a manufacturing process of modification 4 of the method for manufacturing the semiconductor device shown in fig. 1.

Fig. 24 is a sectional view of the manufacturing process in the step up to fig. 23.

Fig. 25 is a sectional view of a semiconductor device which is embodiment 2 of the present invention.

Fig. 26 is a sectional view of a semiconductor device which is embodiment 3 of the present invention.

Fig. 27 is a sectional view of a semiconductor device which is embodiment 4 of the present invention.

Fig. 28 is a sectional view of a semiconductor device which is embodiment 5 of the present invention.

Fig. 29 is a sectional view of a semiconductor device which is embodiment 6 of the present invention.

Fig. 30 is a device cross-sectional view showing a main part of a manufacturing process of the semiconductor device shown in fig. 29.

Fig. 31 is a sectional view of the manufacturing process in the above fig. 30.

Fig. 32 is a sectional view of the manufacturing process immediately following fig. 31.

Fig. 33 is a sectional view of the manufacturing process in the above-described fig. 32.

Fig. 34 is a sectional view of a semiconductor device which is embodiment 7 of the present invention.

Fig. 35 is a sectional view of a semiconductor device which is embodiment 8 of the present invention.

Fig. 36 is a sectional view of a semiconductor device which is embodiment 9 of the present invention.

Fig. 37 is a device cross-sectional view for explaining a method of manufacturing a semiconductor device as another embodiment of the present invention.

Detailed Description

(embodiment mode 1)

Fig. 1 is a sectional view of a semiconductor device which is embodiment 1 of the present invention. The semiconductor device includes a substrate 1 having a planar rectangular shape made of silicon, glass, ceramic, or the like. An adhesive layer 2 composed of an adhesive, an adhesive sheet, and a double-sided adhesive tape is provided on the upper surface of the substrate 1.

The lower surface of a semiconductor construct 3 having a flat rectangular shape with a size slightly smaller than that of the substrate 1 is bonded to the center of the upper surface of the adhesive layer 2. In this case, the semiconductor construct 3 is called CSP, and includes a silicon substrate (semiconductor substrate) 4 bonded to the center portion of the upper surface of the adhesive layer 2.

An integrated circuit (not shown) is provided in the central portion of the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of an aluminum-based metal are provided in the peripheral portion of the upper surface so as to be connected to the integrated circuit. An insulating film 6 made of silicon oxide is provided on the upper surface of the silicon substrate 4 except for the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6.

Here, the structure in which the connection pads 5 and the insulating film 6 are provided on the silicon substrate 4 is generally obtained when the silicon substrate 4 in a wafer state is diced to form individual chips. However, in this embodiment, the silicon substrate 4 in a wafer state is not sliced in a state where the connection pads 5 and the insulating film 6 are formed on the silicon substrate 4 in a wafer state, but the silicon substrate 4 in a wafer state is sliced in a state where the semiconductor construct 3 having the rewiring 10 and the columnar electrodes 11 is obtained as described below.

Next, a structure of the semiconductor construct 3 called CSP will be described. A protective film (insulating film) 8 made of epoxy resin, polyimide, or the like is formed on the upper surface of the insulating film 6 provided on the silicon substrate 4. At this time, an opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6. A rewiring 10 composed of an underlying metal layer 10a and an upper metal layer 10b provided on the underlying metal layer 10a is provided from the upper surface of the connection pad 5 exposed through the openings 7 and 9 to a predetermined portion of the upper surface of the protective film 8.

On the upper surface of the connection pad portion of the rewiring 10, a columnar electrode 11 made of copper is provided. A sealing film (insulating film) 12 made of epoxy resin, polyimide, or the like is provided on the upper surface of the protective film 8 including the rewiring 10, and the upper surface of the sealing film 12 and the upper surface of the columnar electrode 11 are flush with each other. Thus, the semiconductor construct 3 called CSP includes the silicon substrate 4, the connection pad 5, the insulating film 6, the protective film 8, the rewiring 10, the columnar electrode 11, and the sealing film 12.

A rectangular frame-shaped insulating member 13 is provided on the upper surface of the adhesive layer 2 around the semiconductor construct 3. The insulating member 13 is made of a thermosetting resin such as an epoxy resin or a BT resin, and a reinforcing material such as a fiber or a filler. The fibers are glass fibers, aramid fibers, and the like. The filler is silica filler, ceramic filler, etc. The thickness of the insulating member 13 is substantially the same as that of the semiconductor construct 3.

A1 st upper insulating film 14 made of epoxy resin, polyimide, or the like is provided on the upper surfaces of the semiconductor construct 3 and the insulating member 13. An opening 15 is provided in the 1 st upper insulating film 14 at a portion corresponding to the central portion of the upper surface of the columnar electrode 11. A1 st upper redistribution line 16 composed of a 1 st base metal layer 16a and a 1 st upper metal layer 16b provided on the 1 st base metal layer 16a is provided from the upper surface of the columnar electrode 11 exposed through the opening 15 to a predetermined portion of the upper surface of the 1 st upper insulating film 14.

A2 nd upper insulating film 17 made of epoxy resin, polyimide or the like is provided on the upper surface of the 1 st upper insulating film 14 including the 1 st upper rewiring 16. An opening 18 is provided in the 2 nd upper insulating film 17 at a portion corresponding to the connection pad portion of the 1 st upper re-wiring 16. A2 nd upper layer rewiring 19 composed of a 2 nd base metal layer 19a and a 2 nd upper layer metal layer 19b provided on the 2 nd base metal layer 19a is provided at a predetermined position from the upper surface of the connection pad portion of the 1 st upper layer rewiring 16 exposed through the opening 18 to the upper surface of the 2 nd upper layer insulating film 17.

A3 rd upper insulating film 20 made of epoxy resin, polyimide or the like is provided on the upper surface of the 2 nd upper insulating film 17 including the 2 nd upper rewiring 19. An opening 21 is provided in the 3 rd upper insulating film 20 at a portion corresponding to the connection pad portion of the 2 nd upper re-wiring 19. Solder balls 22 are provided in and above the opening 21 so as to be connected to the connection pad portions of the 2 nd upper rewiring 19. A plurality of solder balls 22 are arranged in a matrix on the 3 rd upper insulating film 20.

However, the reason why the size of the substrate 1 is made slightly larger than the size of the semiconductor construct 3 is that the size and pitch of the connection pad portion (portion inside the opening portion 21 of the 3 rd upper-layer insulating film 20) of the 2 nd upper-layer re-wiring 19 are made slightly larger than the size and pitch of the columnar electrode 11 by making the arrangement region of the solder ball 22 slightly larger than the size of the semiconductor construct 3 in accordance with the increase in the number of the connection pads 5 on the silicon substrate 4.

Therefore, the connection pad portions of the 2 nd upper layer re-wiring 19 arranged in a matrix are arranged not only in the region corresponding to the semiconductor construct 3 but also in the region corresponding to the insulating member 13 provided outside the periphery of the semiconductor construct 3. That is, at least the outermost solder balls 22 among the solder balls 22 arranged in a matrix are arranged around the outer side of the semiconductor construct 3.

In this case, as a modified example, the entire connection pad portion of the 2 nd upper layer re-wiring 19 may be arranged around the outer side of the semiconductor construct 3. Further, the upper layer rewiring may be 1 layer, that is, only the 1 st upper layer rewiring 16, and at least the outermost connection pad portion may be arranged around the periphery located outside the semiconductor construct 3.

As described above, the semiconductor device is characterized in that the semiconductor device has not only the connection pad 5 and the insulating film 6 on the silicon substrate 4 but also the insulating member 13 is provided around the semiconductor construct 3 in which the protective film 8, the rewiring 10, the columnar electrode 11, the sealing film 12, and the like are further formed, and at least the 1 st upper-layer insulating film 14 and the 1 st upper-layer rewiring 16 connected to the columnar electrode 11 through the opening 15 formed in the 1 st upper-layer insulating film 14 are formed on the upper surface thereof.

In this case, the rectangular frame-shaped insulating member 13 disposed around the semiconductor construct 3 is made of a thermosetting resin containing a reinforcing material such as a fiber or a filler, and therefore, compared with the case of only a thermosetting resin, it is possible to reduce stress caused by shrinkage when the thermosetting resin is cured, and it is possible to make the substrate 1 less likely to warp. Further, by flattening the upper surface by using the insulating member 13, as will be described later, the height positions of the upper surfaces of the upper layer re-wirings 16 and 19 and the solder ball 22 formed in the subsequent steps are made uniform, and the reliability at the time of bonding can be improved.

(production method)

Next, in order to explain an example of a method for manufacturing the semiconductor device, an example of a method for manufacturing the semiconductor construct 3 will be explained first. At this time, first, as shown in fig. 2, a semiconductor construct is prepared as follows: on a silicon substrate (semiconductor substrate) 4 in a wafer state, a connection pad 5 made of an aluminum-based metal or the like, an insulating film 6 made of silicon oxide or the like, and a protective film 8 made of an epoxy-based resin, polyimide or the like are provided, and the center portion of the connection pad 5 is exposed through openings 7, 9 formed in the insulating film 6 and the protective film 8.

Next, as shown in fig. 3, a base metal layer 10a is formed on the entire upper surface of the protective film 8 including the upper surfaces of the connection pads 5 exposed through the openings 7 and 9. In this case, the base metal layer 10a may be a copper layer formed by electroless plating alone, a copper layer formed by sputtering alone, or a copper layer formed by sputtering on a thin film layer of titanium or the like formed by sputtering. The same applies to the upper base metal layers 16a and 19a described later.

Next, the plating resist film 31 is patterned on the upper surface of the base metal layer 10 a. At this time, the opening 32 is formed in the plating resist 31 at a portion corresponding to the region where the rewiring 10 is formed. Next, electrolytic plating of copper is performed using the base metal layer 10a as a plating current path, whereby an upper metal layer 10b is formed on the upper surface of the base metal layer 10a in the opening 32 of the plating resist 31. Subsequently, the plating resist film 31 is peeled off.

Next, as shown in fig. 4, a plating resist film 33 is patterned and formed on the upper surface of the base metal layer 10a including the upper metal layer 10 b. At this time, the opening 34 is formed in the plating resist film 33 at a portion corresponding to the formation region of the columnar electrode 11. Next, electrolytic plating of copper is performed using the base metal layer 10a as a plating current path, whereby the columnar electrode 11 is formed on the upper surface of the connection pad portion of the upper metal layer 10b in the opening 34 of the plating resist 33.

Next, the plating resist film 33 is peeled off, and then, unnecessary portions of the base metal layer 10a are etched and removed with the columnar electrodes 11 and the upper metal layer 10b as masks. As shown in fig. 5, the base metal layer 10a remains only under the upper metal layer 10b, and the rewiring 10 is formed by the remaining base metal layer 10a and the upper metal layer 10b formed on the entire upper surface thereof.

Next, as shown in fig. 6, a sealing film 12 made of epoxy resin, polyimide, or the like is formed on the entire upper surface of the protective film 8 including the columnar electrodes 11 and the rewirings 10 by screen printing, spin coating, or the like, and the thickness of the sealing film 12 is larger than the height of the columnar electrodes 11. Therefore, in this state, the upper surface of the columnar electrode 11 is covered with the sealing film 12.

Next, the upper surfaces of the sealing film 12 and the columnar electrodes 11 are appropriately polished to expose the upper surfaces of the columnar electrodes 11, and the upper surface of the sealing film 12 including the exposed upper surfaces of the columnar electrodes 11 is planarized as shown in fig. 7. Subsequently, as shown in fig. 8, a plurality of semiconductor constructs 3 shown in fig. 1 are obtained through a dicing step.

Further, the purpose of appropriately polishing the upper surface side of the columnar electrode 11 is to eliminate variations in the height of the columnar electrode 11 formed by electrolytic plating and to make the height of the columnar electrode 11 uniform, since there are variations in the height of the columnar electrode 11. In this case, a grinder having a grinding stone with an appropriate thickness is used to simultaneously grind the columnar electrode 11 made of soft copper and the sealing film 12 made of epoxy resin.

Next, an example of a case where the semiconductor device shown in fig. 1 is manufactured using the semiconductor construct 3 obtained as described above will be described. First, as shown in fig. 9, the adhesive layer 2 is formed on the entire upper surface of the substrate 1 by utilizing the dimensions of the substrate 1 shown in fig. 1, but the planar shape of the substrate 1 is rectangular, preferably substantially square, although not limited thereto. Next, the lower surface of the silicon substrate 4 of each semiconductor construct 3 is bonded to a predetermined plurality of portions on the upper surface of the adhesive layer 2.

Next, an insulating member material 13A made of a semi-cured thermosetting resin such as an epoxy resin or a BT resin containing a reinforcing material such as a fiber or a filler is arranged on the upper surface of the adhesive layer 2 on the outer side of the semiconductor construct 3 arranged between the semiconductor constructs 3 and on the outermost periphery, and the insulating member material 13A is arranged slightly over the upper surface of the semiconductor construct 3.

Next, as shown in fig. 10, the insulating member material 13A is heated and pressed by using a pair of heating and pressing plates 35, 36, whereby the insulating member 13 is formed on the upper surface of the adhesive layer 2 on the outer side of the semiconductor construct 3 disposed between the semiconductor constructs 3 and on the outermost periphery, and the upper surface of the insulating member 13 is substantially flush with the upper surface of the semiconductor construct 3.

At this time, as shown in fig. 7, in the wafer state, the height of the columnar electrode 11 of the semiconductor construct 3 is made uniform, and the upper surface of the sealing film 12 including the upper surface of the columnar electrode 11 is flattened, so that the thickness of each of the plurality of semiconductor constructs 3 is the same in the state shown in fig. 10.

Here, in the state shown in fig. 10, when the upper surface of the semiconductor construct 3 is heated and pressurized as a pressurization limiting surface, the thickness of the insulating member 13 is substantially the same as the thickness of the semiconductor construct 3. In addition, as the pressing device including the pair of heating and pressing plates 35, 36, if an open type flat pressing device is used, the remaining thermosetting resin in the insulating member material 13A is pressed out to the outside of the pair of heating and pressing plates 35, 36. Then, in this state, when the thermosetting resin semi-cured in the insulating member 13 is cured, the upper surface of the insulating member 13 is substantially flush with the upper surface of the semiconductor construct 3. In the manufacturing process shown in FIG 10, heating and pressing may be performed by different devices so that only the upper surface side is pressed, and heating may be performed by a heater or the like on the lower surface side of the semiconductor construct 3, or pressing and heating may be performed in different processes.

Thus, the thickness of the insulating member 13 can be substantially the same as the thickness of the semiconductor construct 3 by heating and pressing or only by pressing, and therefore, a polishing step is not required. Therefore, even if the size of the substrate 1 is relatively large, for example, about 500 × 500mm, the planarization process of the insulating members 13 can be easily performed uniformly for the plurality of semiconductor constructs 3 arranged thereon.

Here, even if the remaining thermosetting resin in the insulating member material 13A slightly flows out onto the semiconductor construct 3, the thickness of the thermosetting resin layer formed by the flowing-out is negligibly small, which is not a hindrance. On the other hand, when the thickness of the thermosetting resin layer formed by the flow-out is too thick to be ignored, it may be removed by buffing.

That is, in this case, since the upper surface of the semiconductor construct 3, that is, the upper surface of the columnar electrode 11 made of copper is not polished, but the thermosetting resin layer covering the upper surface of the semiconductor construct 3 and the upper surface of the insulating member 13 to be formed in a thickness is removed, and the thermosetting resin layer does not contain a reinforcing material such as a fiber or a filler, polishing can be easily performed using an inexpensive and low-precision polishing and polishing apparatus.

As another example of polishing, a part of an inexpensive and low-precision endless polishing tape may be planarized, the upper surface of the semiconductor construct 3 may be used as a polishing-restricting surface, and the planarized part may be used to perform smooth polishing of a thermosetting resin layer covering the upper surface of the semiconductor construct 3 and the upper surface of the insulating member 13 to be formed with a thickness.

In addition, in the polishing apparatus using the polishing and circulating polishing tape, even if the size of the substrate 1 is relatively large, for example, about 500 × 500mm, the polishing process can be easily performed at one time, and the substrate can be easily polished in a short time. In this way, in this step, it is expected that polishing not causing sag (ダレ) on the upper surface side of the columnar electrode 11 is achieved in terms of productivity, unlike polishing with a grindstone or the like.

However, since the square frame-shaped insulating member 13 disposed around the semiconductor construct 3 is made of a thermosetting resin containing a reinforcing material such as a fiber or a filler, stress caused by shrinkage of the thermosetting resin at the time of curing can be reduced as compared with the case of only the thermosetting resin, and the substrate 1 can be made less likely to warp. Further, the insulating member 13A may be a sheet material having an opening portion having substantially the same size as the semiconductor construct 3 or a slightly larger size, depending on the position where each semiconductor construct 3 is arranged. In addition, in the above-described embodiment, the case where the insulating member material 13A is disposed after disposing the plurality of semiconductor constructs 3 on the substrate 1 is explained, but the semiconductor constructs 3 may be disposed after disposing the insulating member material 13A in which the openings corresponding to the respective semiconductor constructs 3 are formed on the substrate 1.

After the process shown in fig. 10 is completed, a 1 st upper insulating film 14 is formed on the entire upper surfaces of the semiconductor construct 3 and the insulating member 13 which are substantially flush with each other, as shown in fig. 11. In this case, the 1 st upper insulating film 14 may be formed by laminating a resin film or by applying a liquid resin. When the 1 st upper insulating film 14 is formed of a photosensitive resin such as an epoxy resin or a resin such as a karl (カルド), the opening 15 is formed by photolithography on the 1 st upper insulating film 14 at a portion corresponding to the center of the upper surface of the columnar electrode 11.

When the 1 st upper-layer insulating film 14 is formed of a non-photosensitive resin such as an epoxy resin or a BT resin, the opening 15 is formed in the 1 st upper-layer insulating film 14 by laser processing by irradiating a laser beam. In this case, in the manufacturing process shown in fig. 10, the thermosetting resin remaining in the insulating member material 13A slightly flows out onto the semiconductor construct 3, and even if the thickness of the thermosetting resin layer formed by the flowing-out is not negligible, the polishing process can be omitted when the thickness is so thin that an opening can be formed by laser processing.

Next, as shown in fig. 12, a 1 st base metal layer 16a is formed on the entire upper surface of the 1 st upper-layer insulating film 14 including the upper surface of the columnar electrode 11 exposed through the opening 15. Then, an anti-plating film 37 is patterned on the upper surface of the 1 st base metal layer 16 a. At this time, an opening 38 is formed in the plating resist film 37 at a portion corresponding to the 1 st upper rewiring 16 formation region. Next, electrolytic plating of copper is performed using the 1 st base metal layer 16a as a plating current path, whereby the 1 st upper metal layer 16b is formed on the upper surface of the 1 st base metal layer 16a in the opening 38 of the plating resist 37.

Next, when the plating resist 37 is peeled off and then the 1 st upper metal layer 16b is used as a mask to etch and remove an unnecessary portion of the 1 st base metal layer 16a, as shown in fig. 13, the 1 st base metal layer 16a remains only under the 1 st upper metal layer 16b, and the 1 st upper rewiring 16 is formed from the 1 st base metal layer 16a remaining and the 1 st upper metal layer 16b formed on the entire upper surface thereof.

Next, as shown in fig. 14, a 2 nd upper insulating film 17 made of an epoxy resin, polyimide, or the like is formed on the entire upper surface of the 1 st upper insulating film 14 including the 1 st upper rewiring 16 by screen printing, spin coating, or the like. At this time, the opening 18 is formed in the 2 nd upper insulating film 17 at a portion corresponding to the connection pad portion of the 1 st upper re-wiring 16. Next, a 2 nd underlying metal layer 19a is formed on the entire upper surface of the 2 nd upper insulating film 17 including the connection pad portion of the 1 st upper rewiring 16 exposed through the opening 18.

Next, an anti-plating film 39 is patterned on the upper surface of the 2 nd base metal layer 19 a. At this time, an opening 40 is formed in the plating resist film 39 in a portion corresponding to the 2 nd upper rewiring 19 formation region. Next, electrolytic plating of copper is performed using the 2 nd foundation metal layer 19a as a plating current path, whereby the 2 nd upper metal layer 19b is formed on the upper surface of the 2 nd foundation metal layer 19a in the opening 40 of the plating resist 39.

Then, the plating resist film 39 is peeled off, and thereafter, unnecessary portions of the 2 nd foundation metal layer 19a are etched and removed using the 2 nd upper metal layer 19b as a mask, whereby the 2 nd foundation metal layer 19a remains only under the 2 nd upper metal layer 19b, and the 2 nd upper rewiring 19 is formed from the remaining 2 nd foundation metal layer 19a and the 2 nd upper metal layer 19b formed on the entire upper surface thereof, as shown in fig. 15.

Next, as shown in fig. 16, a 3 rd upper insulating film 20 made of an epoxy resin, polyimide, or the like is formed on the entire upper surface of the 2 nd upper insulating film 17 including the 2 nd upper rewiring 19 by screen printing, spin coating, or the like. At this time, the opening 21 is formed in the 3 rd upper insulating film 20 at a portion corresponding to the connection pad portion of the 2 nd upper re-wiring 19. Next, solder balls 22 are formed in and above the openings 21 so as to be connected to the connection pad portions of the 2 nd upper rewiring 19.

Next, as shown in fig. 17, the 3 insulating films 20, 17, and 14, the insulating member 13, the adhesive layer 2, and the substrate 1 are cut between the adjacent semiconductor constructs 3, and a plurality of semiconductor devices shown in fig. 1 can be obtained.

In the semiconductor device thus obtained, the 1 st foundation metal layer 16a and the 1 st upper metal layer 16b connected to the columnar electrode 11 of the semiconductor construct 3 are formed by electroless plating (or sputtering) and electrolytic plating, and the 2 nd foundation metal layer 19a and the 2 nd upper metal layer 19b connected to the connection pad portion of the 1 st upper rewiring 16 are formed by electroless plating (or sputtering) and electrolytic plating, so that it is possible to secure the conductive connection between the columnar electrode 11 of the semiconductor construct 3 and the 1 st upper rewiring 16 and the conductive connection between the 1 st upper rewiring 16 and the 2 nd upper rewiring 19.

In the above manufacturing method, since the plurality of semiconductor constructs 3 are arranged on the adhesive layer 2 on the substrate 1, the insulating member 13, the 1 st to 3 rd upper insulating films 14, 17, 20, the 1 st and 2 nd base metal layers 16a, 19a, the 1 st and 2 nd upper metal layers 16b, 19b and the solder ball 22 are collectively formed on the plurality of semiconductor constructs 3, and then the plurality of semiconductor devices are obtained by dividing the semiconductor constructs, the manufacturing process can be simplified.

Further, since a plurality of semiconductor constructs 3 can be carried together with the substrate 1, the manufacturing process can be simplified. Furthermore, if the outer dimensions of the substrate 1 are made constant, the transfer system can be made common regardless of the outer dimensions of the semiconductor device to be manufactured.

Furthermore, in the above-described manufacturing method, since the CSP type semiconductor construct 3 including the rewiring 10 and the columnar electrode 11 is bonded to the adhesive layer 2 as shown in fig. 9, the cost can be reduced as compared with a case where, for example, a normal semiconductor chip having the connection pad 5 and the insulating film 6 provided on the silicon substrate 4 is bonded to the adhesive layer 2, and then the rewiring and the columnar electrode are formed on a sealing film or the like provided around the semiconductor chip.

For example, when the substrate 1 before cutting is formed into a substantially circular shape having a predetermined size like a silicon wafer, if rewiring and columnar electrodes are formed on a sealing film or the like provided around the semiconductor chip bonded to the adhesive layer 2, the processing area increases. In other words, in order to perform low-density processing, the number of processing sheets per one time is reduced, and the production amount is reduced, so that the cost is increased.

In contrast, in the above-described manufacturing method, since the CSP type semiconductor construct 3 including the rewiring 10 and the columnar electrode 11 is bonded to the adhesive layer 2 and then assembled (built up), although the number of steps is increased, high-density processing is performed before the columnar electrode 11 is formed, so that efficiency is improved, and the overall price can be reduced in consideration of the increase in the number of steps.

In the above embodiment, the solder balls 22 are arranged in a matrix shape corresponding to the entire surface of the semiconductor construct 3 and the insulating member 13, but the solder balls 22 may be provided only in the region corresponding to the insulating member 13 around the semiconductor construct 3. In this case, the solder balls 33 may be provided not only on the entire periphery of the semiconductor construct 3 but also on the side of 1 to 3 sides among 4 sides of the semiconductor construct 3. In this case, the insulating member 13 does not need to be formed in a rectangular frame shape, and may be disposed only on the side of the side where the solder ball 22 is provided.

(modification 1 of the production method)

Next, a modified example 1 of the method for manufacturing the semiconductor device shown in fig. 1 will be described. First, as shown in fig. 18, the following preparation is performed: an adhesive layer 42 made of an ultraviolet-curable adhesive sheet or the like is bonded to the entire upper surface of another substrate 41 made of an ultraviolet-transmitting transparent resin plate, a glass plate, or the like, and the substrate 21 and the adhesive layer 22 described above are bonded to the upper surface of the adhesive layer 42.

After the manufacturing steps shown in fig. 9 to 16, the 3 insulating films 20, 17, and 14, the insulating member 13, the adhesive layer 2, the substrate 1, and the adhesive layer 42 are cut, and the other substrate 41 is not cut, as shown in fig. 19. Next, ultraviolet rays are irradiated from the lower surface side of the other substrate 41 to cure the adhesive layer 42. In this way, the adhesiveness of the adhesive layer 42 to the lower surface of the substrate 1 to be cut is reduced. Here, if the products in a single piece present on the adhesive layer 42 are peeled one by one and picked up, a plurality of semiconductor devices shown in fig. 1 can be obtained.

In the manufacturing method, in the state shown in fig. 19, the semiconductor devices in individual pieces existing on the adhesive layer 42 are not scattered, and therefore, it is possible to pick up the semiconductor devices one by one without using a dedicated tray for placing the semiconductor devices when mounting the semiconductor devices on a circuit board not shown. After the adhesive layer 42 remaining on the upper surface of the other substrate 41 and having a reduced adhesiveness is peeled off, the other substrate 41 can be reused. Further, if the outer dimensions of the other substrate 41 are set to be constant, the transfer system can be made common regardless of the outer dimensions of the semiconductor device to be manufactured.

Here, as the other substrate 41, a general dicing tape from which a semiconductor device is taken out by expansion may be used, and in this case, the adhesive layer may not be of an ultraviolet curing type. In addition, the other substrate 41 may be removed by polishing or etching.

(modification 2 of the production method)

Next, a modified example 2 of the method for manufacturing the semiconductor device shown in fig. 1 will be described. In this manufacturing method, after the manufacturing step shown in fig. 11, as shown in fig. 20, a 1 st base metal layer 16a is formed by electroless copper plating on the entire upper surface of the 1 st upper insulating film 14 including the upper surface of the columnar electrode 11 exposed through the opening 15. Next, electrolytic plating of copper is performed using the 1 st base metal layer 16a as a plating current path, thereby forming a 1 st upper metal layer 16c on the entire upper surface of the 1 st base metal layer 16 a. Next, a resist film 43 is patterned and formed on the upper surface of the 1 st upper layer metal formation layer 16c at a portion corresponding to the 1 st upper layer rewiring formation region.

Next, when unnecessary portions of the 1 st upper metal layer 16c and the 1 st underlying metal layer 16a are etched and removed using the resist film 43 as a mask, the 1 st upper rewiring layer 16 remains only under the resist film 43 as shown in fig. 21. After that, the resist film 43 is peeled off. Further, the 2 nd upper layer rewiring 19 may be formed by the same forming method as described above.

However, the substrate 1 shown in fig. 9 or the other substrate 41 shown in fig. 19 may be formed in a plate shape. That is, the substrate is formed in a tray shape in which the region where the semiconductor constructs 3 are arranged is lower than the surrounding. Then, electrolytic plating may be performed by providing a metal layer for a plating current path on the upper surface of the plate-like substrate surrounding the area where the semiconductor construct 3 is arranged, and connecting the metal layer for a plating current path and the base metal layers (16a, 19a) for a plating current path with a conductive member. In this case, by making the outer dimensions of the trays the same, even if the semiconductor devices to be manufactured are different in size, the same manufacturing apparatus can be used, and efficiency is high.

(modification 3 of the production method)

Next, a modified example 3 of the method for manufacturing the semiconductor device shown in fig. 1 will be described. In this manufacturing method, as shown in fig. 22, a sheet-like insulating member material 13B made of a semi-cured epoxy resin containing a reinforcing material such as a fiber or a filler and a thermosetting resin such as a BT resin is arranged on a plurality of semiconductor constructs 3 arranged on an adhesive layer 2 on a substrate 1.

Next, by heating and pressing the upper surface of the semiconductor construct 3 as a pressing restriction surface using the pair of heating and pressing plates 35 and 36, the thermosetting resin in the sheet-like insulating member material 13B is pressed together with the reinforcing material into the adhesive layer 2 between the semiconductor constructs 3 and on the outer side of the semiconductor construct 3 arranged outermost, and the insulating member 13 having an upper surface substantially flush with the upper surface of the semiconductor construct 3 is formed as in the case shown in fig. 10.

(modification 4 of the production method)

Next, a modified example 4 of the method for manufacturing the semiconductor device shown in fig. 1 will be described. In this manufacturing method, after the manufacturing step shown in fig. 9, as shown in fig. 23, a sheet-like 1 st upper-layer insulating film material 14A made of a photosensitive resin such as an epoxy resin and a resin such as a kardel (カルド) is temporarily bonded to the upper surfaces of the plurality of semiconductor constructs 3 and the upper surface of the insulating member material 13A by lamination processing or the like. In this case, as the photosensitive resin for forming the 1 st upper insulating film material 14A in a sheet form, a resin having relatively low fluidity is preferably used.

Next, the 1 st upper insulating film material 14A is temporarily cured by light irradiation. The purpose of this temporary curing is to prevent the thermosetting resin in the insulating member material 13A from flowing out onto the semiconductor construct 3 and to prevent the thermosetting resin in the insulating member material 13A from being mixed with the photosensitive resin forming the 1 st upper insulating film material 14A in the subsequent heating and pressing step.

Next, as shown in fig. 24, by heating and pressing the upper surface of the 1 st upper insulating film 14 to be formed using a pair of heating and pressing plates 35, 36 as a heating limiting surface, the insulating film 13 is formed on the upper surface of the adhesive layer 2 outside the semiconductor construct 3 disposed between the semiconductor constructs 3 and the outermost periphery, the upper surface of the insulating film 13 is substantially flush with the upper surface of the semiconductor construct 3, and the 1 st upper insulating film 14 is formed on the entire upper surfaces of the semiconductor construct 3 and the insulating member 13 substantially flush with each other.

In the heat and pressure treatment, since the semiconductor construct 3 is pressurized by the 1 st upper insulating film material 14A made of a photosensitive resin, the pressure applied to the semiconductor construct 3 can be reduced. Next, since the 1 st upper insulating film 14 made of a photosensitive resin is already irradiated with light for temporary curing, the opening 15 can be formed in the 1 st upper insulating film 14 at a portion corresponding to the central portion of the upper surface of the electrode 11 by laser processing without photolithography (see fig. 11).

(embodiment mode 2)

In the manufacturing process shown in fig. 9, when the adhesive layers 2 are provided on the lower surface of the silicon substrate 4 of the semiconductor construct 3, respectively, and these adhesive layers 2 are adhered to the predetermined portions on the upper surface of the substrate 1, the lower surface of the insulating member 13 is bonded to the lower surface of the substrate 1 in the manufacturing process shown in fig. 10, and therefore, the semiconductor device according to embodiment 2 of the present invention shown in fig. 25 can be obtained.

In the semiconductor device thus obtained, for example, the lower surface of the silicon substrate 4 is bonded to the upper surface of the substrate 1 via the adhesive layer 2, and the side surface of the silicon substrate 4 is bonded to the upper surface of the substrate 1 via the insulating member 13, so that the bonding strength of the semiconductor construct 3 to the substrate 1 can be increased to some extent.

(embodiment mode 3)

Fig. 26 is a sectional view showing a semiconductor device according to embodiment 3 of the present invention. This semiconductor device is different from the semiconductor device shown in fig. 1 in that the substrate 1 and the adhesive layer 2 are not provided.

In manufacturing the semiconductor device of embodiment 3, for example, as shown in fig. 16, after forming the solder ball 22, the substrate 1 and the adhesive layer 2 are removed by polishing, etching, or the like, and then the insulating films 20, 17, 14 and the insulating member 13 of 3 layers are cut between the mutually adjacent semiconductor constructs 3, whereby a plurality of semiconductor devices shown in fig. 26 can be obtained. In the semiconductor device thus obtained, since the substrate 1 and the adhesive layer 2 are not provided, only this portion can be thinned.

(embodiment mode 4)

Further, after removing the substrate 1 and the adhesive layer 2 by polishing, etching, or the like, the lower surface sides of the silicon substrate 4 and the insulating member 13 are appropriately polished, and then the 3-layer insulating films 20, 17, 14 and the insulating member 13 are cut between the mutually adjacent semiconductor constructs 3, whereby a plurality of semiconductor devices according to embodiment 4 of the present invention shown in fig. 27 can be obtained. The semiconductor device thus obtained can be further thinned.

Before forming the solder balls 22, the substrate 1 and the adhesive layer 2 may be removed by polishing, etching, or the like (if necessary, the lower surfaces of the silicon substrate 4 and the insulating member 13 may be polished appropriately), the solder balls 22 may be formed, and the 3-layer insulating films 20, 17, 14 and the insulating member 13 may be cut between the mutually adjacent semiconductor constructs 3.

(embodiment 5)

Fig. 28 is a sectional view showing a semiconductor device according to embodiment 5 of the present invention. This semiconductor device is different from the semiconductor device shown in fig. 1 in that a metal layer 44 for heat dissipation is bonded to the lower surface of the adhesive layer 2. The metal layer 44 is made of copper foil having a thickness of several tens of μm or the like.

In the case of manufacturing the semiconductor device of embodiment 5, for example, as shown in fig. 16, after the solder balls 22 are formed, the substrate 1 is removed by polishing, etching or the like, the metal layer 44 is then adhered to the entire lower surface of the adhesive layer 2, and then the 3-layer insulating films 20, 17, 14, the insulating member 13, the adhesive layer 2 and the metal layer 44 are cut between the mutually adjacent semiconductor constructs 3, whereby a plurality of semiconductor devices shown in fig. 28 can be obtained.

Alternatively, the adhesive layer 2 may be removed by polishing, etching, or the like (if necessary, the lower surfaces of the silicon substrate 4 and the insulating member 13 may be further polished appropriately), and the metal layer 44 may be bonded to the lower surfaces of the silicon substrate 4 and the insulating member 13 via a new adhesive layer.

(embodiment mode 6)

Fig. 29 is a sectional view showing a semiconductor device according to embodiment 6 of the present invention. This semiconductor device is largely different from the semiconductor device shown in fig. 1 in that the 1 st upper-layer insulating film 14 is formed using the same material as the insulating member 13, a gap 23 is formed between the semiconductor construct 3 and the insulating member 13, and an insulating film 24 made of resin is provided in the gap 23.

Next, an example of a method for manufacturing the semiconductor device will be described. First, as shown in fig. 30, the lower surface of the lattice-shaped insulating member 3 is bonded to a predetermined portion of the upper surface of the adhesive layer 2 provided on the substrate 1. The lattice-shaped insulating member 13 is obtained by forming a plurality of rectangular openings 25 in a sheet-shaped insulating member material (for example, prepreg) made of a thermosetting resin containing a reinforcing material such as fibers and fillers by press working, etching, or the like. The size of the opening 25 is slightly larger than that of the semiconductor construct 3.

Next, the lower surface of the silicon substrate 4 of the semiconductor construct 3 is bonded to the center portion of the upper surface of the adhesive layer 2 in each opening 25 of the lattice-shaped insulating member 13. Here, the thickness of the lattice-like insulating member 13 is slightly thinner than the thickness of the semiconductor construct 3. For this reason, the upper surface of the lattice-like insulating member 13 is disposed slightly below the upper surface of the semiconductor construct 3. In addition, since the size of the opening 25 of the insulating member 13 is slightly larger than the size of the semiconductor construct 3, a gap 23 is formed between the insulating member 13 and the semiconductor construct 3.

Next, as shown in fig. 31, only a sheet-like 1 st upper-layer insulating film material (for example, prepreg) 14B made of a semi-cured thermosetting resin containing a reinforcing material such as a fiber or a filler is simply placed on the upper surfaces of the plurality of semiconductor constructs 3. Here, the gap 23 between the insulating member 13 and the semiconductor construct 3 is smaller in diameter than the reinforcing material made of fibers, fillers, and the like in the 1 st upper insulating film material 14B.

Subsequently, the heating and pressing are performed by using the pair of heating and pressing plates 35 and 36. As described above, since the diameter of the reinforcing material made of fibers, fillers, and the like in the 1 st upper insulating film material 14B is larger than the interval of the gap 23 between the insulating member 13 and the semiconductor construct 3, only the thermosetting resin in the 1 st upper insulating film material 14B is pushed into the gap 23 between the insulating member 13 and the semiconductor construct 3 to form the insulating film 24, and the 1 st upper insulating film material 14 made of the thermosetting resin containing the reinforcing material is formed on the upper surfaces of the insulating film 24, the insulating member 13, and the semiconductor construct 3, as shown in fig. 32.

At this time, if an imaginary plane higher than the upper surface of the semiconductor construct 3 by only the diameter of the reinforcing material in the 1 st upper-layer insulating film material 14 is taken as a pressurization limiting plane, the thickness of the 1 st upper-layer insulating film 14 on the semiconductor construct 3 is the same as the diameter of the reinforcing material therein. Here, the reason why the upper surface of the insulating film 13 is disposed slightly below the upper surface of the semiconductor construct 3 is that an imaginary plane which is higher than the upper surface of the insulating member 13 by the diameter of the reinforcing material in the 1 st upper-layer insulating film material 14 cannot be used as a pressure-restricting plane. The upper surface of the 1 st upper insulating film material 14 is pressed by the lower surface of the upper heating and pressing plate 36, and thus becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the 1 st upper insulating film material 14 is not required.

Next, as shown in fig. 33, since the 1 st upper insulating film material 14 contains a reinforcing material, the opening 15 is formed in the 1 st upper insulating film material 14 at a portion corresponding to the central portion of the upper surface of the columnar electrode 11 by laser processing. Hereinafter, a plurality of semiconductor devices shown in fig. 29 can be obtained through the manufacturing steps shown in fig. 12 to 17, for example.

(embodiment 7)

For example, in the case shown in fig. 1, the solder ball 22 is also arranged on the 3 rd upper insulating film 20 on the semiconductor construct 3, but is not limited thereto. For example, as in embodiment 7 of the present invention shown in fig. 34, the solder balls 22 may be arranged only on the 3 rd upper insulating film 20 on the insulating member 13, and the light shielding film 26 made of a light shielding metal for preventing light from entering the integrated circuit on the silicon substrate 4 may be provided on the 3 rd upper insulating film 20 on the semiconductor construct 3. The light shielding film 26 may be a metal sheet, or may be formed by sputtering, electroless plating, or the like.

(embodiment mode 8)

Fig. 35 is a sectional view showing a semiconductor device according to embodiment 8 of the present invention. In this semiconductor device, as compared with the semiconductor construct 3 shown in fig. 1, the semiconductor construct 3 does not include the columnar electrode 11 and the sealing film 12. At this time, for example, through the manufacturing steps shown in fig. 23 and 24, the square frame-shaped insulating member 13 is formed on the upper surface of the adhesive layer 2 around the semiconductor construct 3, and the 1 st upper insulating film 14 is formed on the upper surfaces of the protective film 8 and the insulating member 13 including the rewiring 10. Then, an opening 15 is formed in the 1 st upper insulating film 14 at a portion corresponding to the connection pad portion of the re-wiring 10 by laser processing, and the 1 st upper re-wiring 16 is connected to the connection pad portion of the re-wiring 10 through the opening 15.

However, although the semiconductor construct 3 in this case does not include the columnar electrodes 11 and the sealing film 12, for example, as described with reference to fig. 23, since the pressure is applied by the 1 st upper insulating film material 14A made of a photosensitive resin at the time of heat-pressure treatment, the pressure applied to the semiconductor construct 3 is reduced, and there is no other problem.

(embodiment mode 9)

For example, in the case shown in fig. 17, the semiconductor constructs 3 adjacent to each other are cut, but the present invention is not limited thereto, and the semiconductor constructs 3 may be cut in 1 group of 2 or more, and for example, as in embodiment 9 of the present invention shown in fig. 36, the semiconductor device of the multi-chip module type may be obtained by cutting in 1 group of 3 semiconductor constructs 3. In this case, the 3 semiconductor constructs 3 of 1 group may be of the same kind or of different kinds.

(other embodiments)

In the above embodiments, the case where the insulating member 13 is formed of the thermosetting resin containing the reinforcing material has been described, but the present invention is not limited to this, and may be formed of only the thermosetting resin, or may be formed of only the thermoplastic resin such as liquid crystal polymer or PEET (polyether ketone).

In the case where the insulating member 13 is formed only of thermoplastic resin, for example, as shown by reference numeral 13A in fig. 9, liquid thermoplastic resin may be printed by a screen printing method. As shown by reference numeral 13C in fig. 37, for example, a liquid thermoplastic resin may be applied so as to cover the semiconductor construct 3, and the insulation member 13 may be formed between the semiconductor constructs 3 or the like by applying heat and pressure with the upper surface of the semiconductor construct 3 as a pressure regulation surface.

For example, in the case shown in fig. 1, the 1 st upper rewiring 16 is provided on the upper surface of the 1 st upper insulating film 14 provided on the upper surfaces of the semiconductor construct 3 and the insulating member 13, but the present invention is not limited thereto, and the 1 st upper insulating film 14 may be omitted, and the upper rewiring 16 may be provided on the upper surfaces of the semiconductor construct 3 and the insulating member 13.

ADVANTAGEOUS EFFECTS OF INVENTION

As described above, according to the present invention, since at least a part of the connection pad portion of the upper layer rewiring of the uppermost layer is provided on the insulating member provided on the side surface of the semiconductor construct, even if the number of connection pad portions of the upper layer rewiring of the uppermost layer is increased, the size and the pitch thereof can be set to a desired size.

Claims (19)

1. A semiconductor device is characterized by comprising:

a semiconductor construct (3) having a plurality of external connection sections (11) on the upper surface;

an insulating member (13) which is provided on the side of the semiconductor construct (3) and is made of a resin containing a reinforcing material;

an insulating film (14) provided on the upper surface of the semiconductor construct (3) except for the external connection portion (11) and on the upper surface of the insulating member (13); and

a plurality of upper layer re-wirings (16 or 19) which are provided on the insulating film (14) so as to be connected to the external connection portions (11) of the semiconductor construct (3), respectively, and which have at least one connection pad portion;

at least a part of the connection pad portion of the uppermost upper redistribution layer (19) among the upper redistribution layers (16 or 19) is provided in a region corresponding to the insulating member (13).

2. The semiconductor device according to claim 1, characterized by having a plurality of the semiconductor constructs (3).

3. The semiconductor device according to claim 1, wherein an upper surface of the insulating member (13) is substantially flush with an upper surface of the semiconductor construct (3).

4. The semiconductor device according to claim 1, wherein an upper surface of the insulating member (13) is arranged at a position slightly lower than an upper surface of the semiconductor construct (3).

5. The semiconductor device according to claim 1, wherein the insulating member (13) is made of a resin containing a reinforcing material.

6. The semiconductor device according to claim 5, wherein an insulating film (24) is provided between the semiconductor construct (3) and the insulating member (13), and the insulating film (24) is made of the same resin as that in the insulating film (14) without including a reinforcing material in the insulating film (14).

7. The semiconductor device according to claim 1, wherein the insulating member (13) has a frame shape.

8. The semiconductor device according to claim 1, wherein the semiconductor construct (3) comprises: a semiconductor substrate (4) having a plurality of connection pads on an upper surface thereof; an insulating film (6) having an opening (9) for exposing the connection pad (5) and formed to cover the semiconductor substrate (4); a plurality of rewirings (10) connected through the openings (9) of the insulating film (6) and having connection pad portions; a plurality of columnar electrodes (11) formed on the connection pad portions of the rewirings (10); and a sealing film (12) provided around the columnar electrode (11) on the semiconductor substrate (4).

9. The semiconductor device according to claim 1, wherein a solder ball (22) is provided on the connection pad portion of the upper rewiring (19) of the uppermost layer.

10. A method of manufacturing a semiconductor device, characterized in that,

on a substrate (1), a plurality of semiconductor constructs (3) each having a plurality of external connection parts (11, 5) on the upper surface and an insulating member (13) between the adjacent semiconductor constructs (3) are arranged;

flattening the insulating member (13) disposed on the substrate (1) by heating or pressing;

a plurality of upper layer re-wirings (19) are provided on the insulating member (13), and the upper layer re-wirings (19) have at least one connection pad portion connected to at least one of the external connection portions (11, 5); and

the insulating member (13) between the semiconductor constructs (3) is cut to obtain each semiconductor device comprising one semiconductor device, in the semiconductor device, at least one connection pad part is arranged on the region corresponding to the insulating member (13) arranged at the side of the semiconductor constructs (3).

11. The method of manufacturing a semiconductor device according to claim 10, wherein the step of cutting the insulating member (13) between the semiconductor constructs (3) is as follows: the substrate (1) is divided into blocks each composed of a plurality of the semiconductor constructs (3) arranged in series, and each block, which is separated by cutting the insulating member (13) located at the boundary of each block, contains a plurality of the semiconductor constructs (3).

12. The method of manufacturing a semiconductor device according to claim 10, wherein the insulating member (13) is made of a resin containing a reinforcing material.

13. The method of manufacturing a semiconductor device according to claim 10, wherein the planarization is performed such that an upper surface of the insulating member (13) disposed between the semiconductor constructs (3) and an upper surface of the semiconductor constructs (3) are substantially flush with each other.

14. The method for manufacturing a semiconductor device according to claim 10, wherein after the insulating member (13) is arranged, an insulating film (14) is formed on the insulating member (13), and the planarization is performed by heating and pressing the insulating film (14).

15. The method of manufacturing a semiconductor device according to claim 10, wherein the planarization is performed with an upper surface of the semiconductor construct (3) being a pressure-restricting surface.

16. The method of manufacturing a semiconductor device according to claim 10, wherein after the planarization, an upper surface of the semiconductor construct (3) and an upper surface of the insulating member (13) are polished.

17. The method of manufacturing a semiconductor device according to claim 10, comprising a step of forming a solder ball (22) on the connection pad portion.

18. The method for manufacturing a semiconductor device according to claim 10, wherein the step of cutting the insulating member (13) includes a step of cutting the substrate (1).

19. The method for manufacturing a semiconductor device according to claim 18, comprising the steps of disposing another substrate (41) under the substrate (1) before cutting, and removing the other substrate (41) after cutting the substrate (1).