HK1085052B - Semiconductor device and method of manufacturing the same - Google Patents

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device belonging to a small semiconductor package called CSP (chip size package) and a method of manufacturing the same.

Background

In recent years, as portable electronic devices typified by cellular phones have been reduced in size, semiconductor devices called CSP (chip size package) have been developed. In the CSP, a passivation film (intermediate insulating film) is formed on the upper surface of a bare semiconductor device having a plurality of connection pads for external connection. An opening portion is formed in the passivation film and corresponds to the connection pad. The interconnect is connected to one end side of the connection pad through the opening portion. A columnar electrode for external connection is formed on the other end side of the interconnect. The space between the columnar electrodes for external connection is filled with a sealing material. According to such a CSP, when a solder ball is formed on a columnar electrode for external connection, the device can be advantageously connected to a circuit board having a connection terminal by a face-down method. The mounting area may be almost the same as the size of the bare semiconductor device. The CSP thus greatly reduces the size of the electronic device as compared to conventional face-up connection methods that use wire bonding. US patent US6467674 discloses a method in which a passivation film, interconnections, external connection electrodes, and a sealing material are formed on a semiconductor substrate in a wafer state in order to increase the yield. And then solder balls are formed on the upper surfaces of the external connection electrodes exposed without being covered with the sealing material. Then, the wafer is cut along the dicing lines, thereby forming individual semiconductor devices.

The conventional semiconductor device has the following problems: as the integration degree becomes higher, the number of external connection electrodes increases. As described above, in the CSP, the external connection electrode is arranged on the upper surface of the bare semiconductor device. Therefore, the external connection electrodes are generally arranged in a matrix. In a semiconductor device having many external connection electrodes, the size and pitch of the external connection electrodes become particularly small. Due to this drawback, the CSP technique cannot be applied to devices having a large number of external connection electrodes relative to the size of the bare semiconductor device. If the external connection electrodes have an extremely small size and pitch, alignment with the circuit board is very difficult. There are also fatal problems such as low connection strength, short circuit between electrodes in connection, and damage of external connection electrodes caused by stress generated by a difference in linear expansion coefficient between a circuit board and a semiconductor substrate, which is generally formed of a silicon substrate.

Disclosure of Invention

An object of the present invention is to provide a novel semiconductor device and a method of manufacturing the same, which can secure a desired size and pitch of external connection electrodes even if the number of electrodes is increased.

According to an aspect of the present invention, there is provided a semiconductor device including: at least one semiconductor member having a semiconductor substrate and a plurality of external connection electrodes formed on the semiconductor substrate; an insulating plate member disposed on one side of the semiconductor member; and a plurality of upper interconnections having connection pad portions, wherein the connection pad portions are disposed on the insulating sheet member and correspond to the upper interconnections, and are electrically connected to the external connection electrodes of the semiconductor member.

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method including: providing a plurality of semiconductor members on a base plate, each semiconductor member having a semiconductor substrate and a plurality of connection pads while separating the semiconductor members from each other, and providing at least one insulating sheet member at positions corresponding to the semiconductor members, heating and pressing the insulating sheet member from an upper side of the insulating sheet member to melt and solidify the insulating sheet member between the semiconductor members, forming at least one layer of upper interconnections having connection pad portions connected to respective ones of the plurality of connection pads of one of the plurality of semiconductor members so as to provide the connection pad portions corresponding to the upper interconnections on the insulating sheet member, and cutting the insulating sheet member between the semiconductor members, thereby obtaining a plurality of semiconductor devices, wherein the connection pad portions of the upper interconnections are provided on the insulating sheet member.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

fig. 2 is a sectional view of an initial prepared structure in an example of a manufacturing method of the semiconductor device shown in fig. 1;

FIG. 3 is a cross-sectional view showing a manufacturing step subsequent to FIG. 2;

FIG. 4 is a sectional view showing a manufacturing step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step subsequent to FIG. 4;

FIG. 6 is a sectional view showing a manufacturing step subsequent to FIG. 5;

FIG. 7 is a sectional view showing a manufacturing step subsequent to FIG. 6;

FIG. 8 is a sectional view showing a manufacturing step subsequent to FIG. 7;

FIG. 9 is a sectional view showing a manufacturing step subsequent to FIG. 8;

FIG. 10 is a sectional view showing a manufacturing step subsequent to FIG. 9;

FIG. 11 is a sectional view showing a manufacturing step subsequent to FIG. 10;

fig. 12 is a sectional view showing a manufacturing step subsequent to fig. 11;

fig. 13 is a sectional view showing a manufacturing step subsequent to fig. 12;

fig. 14 is a sectional view showing a manufacturing step subsequent to fig. 13;

fig. 15 is a sectional view showing a manufacturing step subsequent to fig. 14;

fig. 16 is a sectional view showing a manufacturing step subsequent to fig. 15;

fig. 17 is a sectional view of a semiconductor device according to a second embodiment of the present invention;

fig. 18 is a sectional view of a semiconductor device according to a third embodiment of the present invention;

fig. 19 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention;

fig. 20 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention;

fig. 21 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention;

fig. 22 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention;

fig. 23 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention;

fig. 24 is a sectional view showing a predetermined manufacturing step in the example of the manufacturing method of the semiconductor device shown in fig. 23;

fig. 25 is a sectional view showing a manufacturing step subsequent to fig. 24;

fig. 26 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention;

fig. 27 is a sectional view showing a predetermined manufacturing step in the example of the manufacturing method of the semiconductor device shown in fig. 26;

fig. 28 is a sectional view showing a manufacturing step subsequent to fig. 27;

fig. 29 is a sectional view showing a manufacturing step subsequent to fig. 28;

fig. 30 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention;

fig. 31 is a sectional view of a semiconductor device according to an eleventh embodiment of the present invention;

fig. 32 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention;

fig. 33 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention;

fig. 34 is a sectional view of a semiconductor device according to a fourteenth embodiment of the present invention;

fig. 35 is a sectional view of a semiconductor device according to a fifteenth embodiment of the present invention;

fig. 36 is a sectional view for explaining a manufacturing step of the semiconductor device shown in fig. 35;

fig. 37 is a sectional view showing a manufacturing step subsequent to that of fig. 36;

fig. 38 is a sectional view showing a manufacturing step subsequent to fig. 37;

fig. 39 is a sectional view showing a manufacturing step subsequent to fig. 38;

FIG. 40 is a sectional view showing a manufacturing step subsequent to FIG. 39;

fig. 41 is a sectional view showing a manufacturing step subsequent to fig. 40;

fig. 42 is a sectional view showing a manufacturing step subsequent to fig. 41;

FIG. 43 is a sectional view showing a manufacturing step subsequent to FIG. 42;

fig. 44 is a sectional view of a semiconductor device according to a sixteenth embodiment of the present invention;

fig. 45 is a cross-sectional view of a semiconductor device according to a seventeenth embodiment of the present invention;

fig. 46 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention;

fig. 47 is a sectional view for explaining a manufacturing step of the semiconductor device shown in fig. 46;

FIG. 48 is a cross-sectional view illustrating a subsequent manufacturing step from FIG. 47;

FIG. 49 is a sectional view showing a manufacturing step subsequent to FIG. 48; and

fig. 50 is a sectional view showing a manufacturing step subsequent to fig. 49.

Detailed Description

(first embodiment)

Fig. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. The semiconductor device has a rectangular planar shape and a metal layer 1 made of copper or the like and an insulating layer 2 formed on the lower surface of the metal layer 1 and made of a solder resist. The metal layer prevents the electrification or light from impinging on the integrated circuit of the silicon substrate 5 (described below). The insulating layer 2 protects the metal layer 1.

The lower surface of the semiconductor member 3 having a rectangular planar shape and slightly smaller than the metal layer 1 is connected to the central portion of the upper surface of the metal layer 1 via an adhesive layer 4 made of a die bonding material. The semiconductor member 3 has interconnects, columnar electrodes, and a sealing film (to be described below) and is generally referred to as CSP. In particular, since a method of forming interconnects, columnar electrodes, and a sealing film on a silicon wafer and then performing dicing to obtain individual semiconductor members 3 is employed, as described later, the semiconductor members 3 are also particularly referred to as wafer level CSPs (W-CSPs). The structure of the semiconductor member 3 will be described below.

The semiconductor member 3 has a silicon substrate (semiconductor substrate) 5, and the silicon substrate 5 has a rectangular planar shape and is connected to the metal layer 1 via an adhesive layer 4. An integrated circuit (not shown) is formed on a central portion of the upper surface of the silicon substrate 5. A plurality of connection pads (external connection electrodes) 6 made of an aluminum-based metal and connected to the integrated circuit are formed on the peripheral portion of the upper surface of the silicon substrate 5. An insulating film 7 made of silicon oxide is formed on the upper surface of the silicon substrate 5 and on the connection pads 6 except for the central portion of each connection pad. A central portion of each connection pad 6 is exposed through an opening portion 8 formed in the insulating film 7.

A protective film (insulating film) 9 made of epoxy resin or polyimide resin is formed on the upper surface of the insulating film 7 on the silicon substrate 5. An opening portion 10 is formed in the protective film 9 at a position corresponding to the opening portion 8 of the insulating film 7. An interconnect 11 made of copper extends from the upper surface of each connection pad 6 exposed through the opening portions 8 and 10 to a predetermined portion of the upper surface of the protective film 9.

A columnar electrode (external connection electrode) 12 made of copper is formed on the upper surface of the connection pad portion of each interconnect 11. A sealing film (insulating film) 13 made of an epoxy resin or a polyimide resin is formed on the upper surfaces of the protective film 9 and the interconnects 11. The upper surface of the sealing film 13 is flush with the upper surfaces of the columnar electrodes 12. As described above, the semiconductor member 3 of the so-called W-CSP includes the silicon substrate 5, the connection pad 6, and the insulating film 7, and further includes the protective film 9, the interconnect 11, the columnar electrode 12, and the sealing film 13.

A first insulating material (insulating sheet member) 14 having a rectangular frame shape is provided on the upper surface of the metal layer 1 around the semiconductor member 3. The upper surface of the first insulating material 14 is almost flush with the upper surface of the semiconductor member 3. A second insulating material 15 having a flat upper surface is provided on the upper surfaces of the semiconductor member 3 and the first insulating material 14.

The first insulating material 14, commonly referred to as prepreg, is prepared by, for example, impregnating a thermosetting resin such as epoxy resin into the glass fibers. The second insulating material 15 is generally referred to as aggregate material for the aggregate substrate. The second insulating material 15 is composed of a thermosetting resin such as an epoxy resin or a BT (bismaleimide triazine) resin containing a reinforcing material such as a fiber or a filler. In this case, the fibers are preferably made of glass fibers or aramid fibers. The filler is preferably a silica filler or a ceramic filler.

An opening portion 16 is formed in the second insulating material 15 at a position corresponding to a central portion of the upper surface of the columnar electrode 12. The upper interconnections 17 made of copper are arranged in a matrix. Each of the upper interconnections 17 extends from the upper surface of a corresponding one of the columnar electrodes 12 to a predetermined portion of the upper surface of the second insulating material 15, wherein the corresponding one of the columnar electrodes 12 is exposed from the upper surface of the insulating material 15 through the opening portion 16.

An upper insulating film 18 made of a solder resist is formed on the upper surface of the upper interconnect 17 and the second insulating material 15. An opening portion 19 is formed in the upper insulating film 18 at a position corresponding to the connection pad of the upper interconnect 17. The protruding electrodes 20 formed of solder balls are formed in and on the opening portions 19 and electrically (and mechanically) connected to the connection pad portions of the upper interconnections 17. The protruding electrodes 20 are disposed in a matrix on the upper insulating film 18.

The size of the metal layer 1 is slightly larger than the size of the semiconductor component 3. The reason is as follows. As the number of connection pads on the silicon substrate 5 increases, the arrangement area of the protruding electrode 20 is slightly larger than the size of the semiconductor member 3. Thus, the size and pitch of the connection pad portion of the upper interconnect 17 (the portion in the opening portion 19 of the upper insulating film 8) are formed larger than those of the columnar electrodes 12.

Therefore, the connection pad portions of the upper interconnections 17 arranged in a matrix are mounted not only on the regions corresponding to the semiconductor member 3 but also on the regions corresponding to the first insulating material 14 arranged outside the outer side surfaces of the semiconductor member 3. That is, among the protruding electrodes 20 arranged in a matrix, at least the protruding electrode 20 at the outermost position is arranged around the semiconductor member 3.

As described above, as a feature of such a semiconductor device, the first and second insulating members 14 and 15 are provided around and on the semiconductor member 3, wherein not only the connection pad 6 and the insulating film 7 but also the protective film 9, the interconnect 11, the columnar electrode 12, and the sealing film 13 are formed on the silicon substrate 5. An upper interconnection 17 connected to the columnar electrode 12 through an opening portion 16 formed in the second insulating material 15 is formed on an upper surface of the second insulating material 15.

In the above structure, the upper surface of the second insulating material 15 is flat. For this reason, the height positions of the upper interconnect 17 and the upper surface of the protruding electrode 20 formed in a later step may be uniform, and the reliability of connection may be improved.

An example of a method of manufacturing a semiconductor device will be described below. First, an example of a method of manufacturing the semiconductor member 3 will be described. In this case, as shown in fig. 2, an assembly member is prepared in which connection pads 6 made of an aluminum-based metal, an insulating film 7 made of silicon oxide, and a protective film 9 made of an epoxy resin or a polyimide resin are formed on a silicon substrate (semiconductor substrate) 5 in a wafer state, and the center portions of the connection pads 6 are exposed through opening portions 8 and 10 formed in the insulating film 7 and the protective film 9. In the above structure, an integrated circuit having a predetermined function is formed in a region of the silicon substrate 5 in a wafer state where each semiconductor member is to be formed. Each of the connection pads 6 is electrically connected to an integrated circuit formed in a corresponding region.

Next, as shown in fig. 3, a lower metal layer 11a is formed on the entire upper surface of the protective film 9, including the upper surface of the connection pad 6 exposed through the opening portions 8 and 10. In this case, the lower metal layer 11a may have only a copper layer formed by electroless plating or only a copper layer formed by sputtering. Alternatively, a copper layer may be formed by a sputtering method on a thin titanium layer formed by sputtering. This also applies to the lower metal layer of the upper interconnect 17 (to be described later).

Next, a plating resist film 21 is formed and patterned on the upper surface of the lower metal layer 11 a. In this case, the patterned resist film 21 has an opening portion 22 at a position corresponding to the formation region of each interconnect 11. Copper plating is performed using the lower metal layer 11a as a plating current path, thereby forming an upper metal layer 11b on the upper surface of the lower metal layer 11a in each opening portion 22 of the plating resist film 21. Then, the plating resist film 21 is removed.

As shown in fig. 4, a plating resist film 23 is formed and patterned on the upper surface of the lower metal layer 11a including the upper metal layer 11 b. In this case, the patterned resist film 23 has an opening portion 24 at a position corresponding to the formation region of each columnar electrode 12. Copper plating is performed using the lower metal layer 11a as a plating current path, so that columnar electrodes 12 are formed on the upper surfaces of the connection pads of the upper metal layer 11b in each opening portion 24 of the plating resist film 23.

Then, the plating resist film 23 is removed. Then, unnecessary portions of the lower metal layer 11a are removed by etching using the columnar electrodes 12 and the upper metal layer 11b as a mask, so that the lower metal layer 11a remains only under the upper metal layer 11b, as shown in fig. 5. Each of the remaining lower metal layers l1a and upper metal layer 11b formed on the entire upper surface of lower metal layer 11a constitute interconnect 11.

As shown in fig. 6, a sealing film 13 composed of an epoxy resin or a polyimide resin is formed on the entire upper surfaces of the protective film 9, the columnar electrodes 12, and the interconnects 11 by screen printing, spin coating, or die coating. The thickness of the sealing film 13 is larger than the height of the columnar electrodes 12. Therefore, in this state, the upper surfaces of the columnar electrodes 12 are covered with the sealing film 13. The upper surface sides of the sealing film 13 and the columnar electrodes 12 are appropriately polished, thereby exposing the upper surfaces of the columnar electrodes 12, as shown in fig. 7. The upper surface of the sealing film 13 including the exposed upper surfaces of the columnar electrodes 12 is also planarized.

The reason why the upper surface side of the columnar electrode 12 is appropriately polished is: the height of the columnar electrode l2 formed by electroplating varies and must be made uniform by removing the variation. In order to simultaneously polish the columnar electrode 12 made of soft copper and the sealing film 13 made of epoxy resin or the like, a grinder of a grindstone having an appropriate roughness is used.

As shown in fig. 8, the adhesive layer 4 is attached to the entire lower surface of the silicon substrate 5. The adhesive layer 4 is made of a die bonding material such as epoxy or polyimide and is bonded to the silicon substrate 5 in a temporarily set state by heating and pressing. Next, the adhesive layer 4 bonded to the silicon substrate 5 is attached to a dicing tape (not shown). After the cutting step shown in fig. 9, each member is peeled off from the dicing tape. Thus, a plurality of semiconductor members 3 each having the adhesive layer 4 on the lower surface of the silicon substrate 5 are obtained, as shown in fig. 1.

In the semiconductor member 3 thus obtained, the adhesive layer 4 is present on the lower surface of the silicon substrate 5. Therefore, after the dicing step, a very troublesome operation for forming an adhesive layer on the lower surface of the silicon substrate 5 of each semiconductor member 3 is not required. The operation for peeling each semiconductor member from the dicing tape after the dicing step is much simplified than the operation for forming the adhesive layer on the lower surface of the silicon substrate 5 of each semiconductor member 3 after the dicing step.

An example will be given below in which the semiconductor device shown in fig. 1 is manufactured using the semiconductor member 3 obtained by the above-described method. First, as shown in fig. 10, a substrate 31 is prepared. The substrate 31 is so large that a plurality of copper foils constituting the upper surface side of the metal layer 1 as shown in fig. 1 are sampled, which will be described later. The substrate 31 has a rectangular planar shape, particularly an approximately square planar shape, but its shape is not limited thereto. The copper foil is attached to the upper surface of the substrate 31 via an adhesive layer 32.

The substrate 31 may be made of an insulating material such as glass, ceramic, or resin. In this case, a substrate made of aluminum is used as an example. Regarding the dimensions, the thickness of the substrate 31 made of aluminum is about 0.4mm, and the thickness of the copper foil 1a is about 0.012 mm. The substrate 31 is used because the copper foil 1a is too thin and cannot be used as a substrate. The device copper foil 1a serves as an antistatic member at the manufacturing step.

Next, the adhesive layer 4 bonded to the lower surface of the silicon substrate 5 of the semiconductor member 3 is bonded to a plurality of predetermined portions of the upper surface of the copper foil 1 a. During this bonding process, the adhesive layer 4 is finally provided by heating and pressing. Two first insulating plates 14a and 14b each having opening portions arranged in a matrix are aligned and stacked on the upper surface of the copper foil 1a between the semiconductor member 3 and the outside of the semiconductor member 3 located at the outermost position. The second insulating sheet member 15a is placed on the upper surface of the first insulating sheet member 14 b. The semiconductor member 3 may be provided after stacking and providing the two first insulating sheet members 14a and 14 b.

The first insulating sheet members 14a and 14b each having a matrix shape can be obtained in the following manner. A thermosetting resin such as an epoxy resin is injected into the glass fibers. The thermosetting resin is semi-cured to prepare a plate-shaped prepreg. A plurality of rectangular opening portions 33 are formed in the prepreg material by punching or etching. In this case, in order to obtain flatness, each of the first insulating sheet members 14a and 14b must be a plate-shaped member. However, the material need not always be a prepreg material. A thermosetting resin or a thermosetting resin in which a reinforcing material such as glass fiber or silica filler is dispersed may also be used.

The second insulating sheet member 15a is preferably made of aggregate material, but is not limited thereto. As the aggregate material, a thermosetting resin in which a silica filler and a semi-cured resin are mixed, such as an epoxy resin or a BT resin, may be used. However, as the second insulating sheet member 15a, the above prepreg or a material containing no filler or containing only a thermosetting resin may be used.

The size of the opening portion 33 of the first insulating sheet members 14a and 14b is slightly larger than that of the semiconductor member 3. For this reason, a gap 34 is formed between the first insulating plate members 14a, 14b and the semiconductor member 3. The length of the gap 34 is, for example, approximately 0.1-0.5 mm. The total thickness of the first insulating sheet members 14a and 14b is larger than the thickness of the semiconductor member 3. The first insulating sheet members 14a and 14b are sufficiently thick to fill the gap 34 when the first insulating sheet members are heated and pressed, as described later.

In this case, the first insulating plate members 14a and 14b having the same thickness are used. However, the first insulating plate substrates 14a and 14b may have different thicknesses. The first insulating sheet member may comprise two layers, as described above. However, one layer or three or more layers may be included. The thickness of the second insulating sheet member 15a corresponds to or is slightly larger than the thickness of the second insulating material 15 to be formed on the semiconductor member 3 in fig. 1.

Next, the first insulating sheet members 14a and 14b and the second insulating sheet member 15a are heated and pressed using a pair of heating/pressing plates 35 and 36 shown in fig. 11. Thus, the molten thermosetting resin in the first insulating sheet members 14a and 14b is pressed so as to fill the gap 34 between the first insulating sheet members 14a, 14b and the semiconductor member 3, as shown in fig. 10. By the subsequent cooling treatment, the thermosetting resin is semi-cured while being bonded to the semiconductor member 3 and the copper foil 1a therebetween. In this way, as shown in fig. 11, the first insulating material 14 made of a thermosetting resin containing a reinforcing material and bonded to the substrate 31 is formed on the upper surface of the copper foil 1a between the semiconductor member 3 and the outside of the semiconductor member 3 located on the outermost position. Further, a second insulating material 15 made of a thermosetting resin containing a reinforcing material is formed on the upper surfaces of the semiconductor member 3 and the first insulating material 14.

In this case, as shown in fig. 7, the columnar electrodes 12 in each semiconductor member 3 have a uniform height in the wafer state. Further, the upper surface of the sealing film 13 including the upper surfaces of the columnar electrodes 12 is planarized. For this reason, in the state shown in fig. 11, the plurality of semiconductor members 3 have the same thickness.

In the state shown in fig. 11, heating and pressing are performed while a virtual plane higher than the upper surface of the semiconductor member 3 is defined by the diameter of a layer of reinforcing material (e.g., silica filler) as a pressure limiting surface. The second insulating material 15 on the semiconductor member 3 obtains a thickness equal to the diameter of the reinforcing material (for example, silica filler). When an open-ended (open) flat press is used as the press having a pair of heating/pressing plates 35 and 36, the excess thermosetting resin in the insulating sheet members 14a, 14b, 15a is extruded out of the pair of heating/pressing plates 35 and 36.

The upper surface of the second insulating material 15 is a flat surface because it is pressed on the upper side by the lower surface of the heating/pressing plate 36. Therefore, a polishing step of planarizing the upper surface of the second insulating material 15 is not required. Even if the copper foil 1a has a relatively large size, for example, about 500 × 500mm, the second insulating material 15 can be easily planarized at a time with respect to the plurality of semiconductor members 3 provided on the copper foil 1 a.

The first and second insulating materials 14 and 15 are composed of a thermosetting resin containing a reinforcing material such as a fiber or a filler. For this reason, stress due to shrinkage in curing of the thermosetting resin can be reduced as compared with a structure composed of only the thermosetting resin. This also prevents the copper foil 1a from bending.

In the manufacturing step shown in fig. 11, the heating and pressing may be performed by separate devices. That is, for example, the lower surface of the semiconductor member 3 may be heated by the heater while the pressing is performed only from the upper surface side. Alternatively, the heating and pressurizing may be performed in separate steps.

When the manufacturing step shown in fig. 11 is finished, the first and second insulating materials 14 and 15, the semiconductor member 3, and the copper foil 1a are integrated together. They retain only the required strength. Next, the substrate 31 and the adhesive layer 32 are peeled or removed by polishing or etching. Such a process is performed in order to reduce a load in dicing (which will be described later) and to reduce the thickness of a semiconductor device as a product. In the manufacturing step shown in fig. 10, when the insulating sheet members 14a, 14b, and 15a are temporarily cured and temporarily adhered to the upper surface of the copper foil 1a by temporary contact bonding, the substrate 31 and the adhesive layer 32 may be peeled or removed by polishing or etching after this step.

Then, as shown in fig. 12, an opening portion 16 is formed in the second insulating material 15 at a position corresponding to the central portion of the upper surface of the columnar electrode 12 by laser machining in which the second insulating material 15 is irradiated with a laser beam. Then, the epoxy oil stain generated in the opening portion 16 is removed by degreasing treatment as needed.

As shown in fig. 13, an upper interconnect forming layer 17a is formed on the entire upper surface of the second insulating material 15, including the upper surfaces of the columnar electrodes 12 exposed through the opening portions 16. Meanwhile, a metal film 1b is formed on the lower surface of the copper foil 1 a. In this case, the upper interconnect formation layer 17a and the metal film 1b each include, for example, a lower metal layer formed of a copper layer formed by electroless plating and an upper metal layer formed on a surface of the lower metal layer by performing copper electroplating using the lower metal layer as an electroplating current path.

When the upper interconnect forming layer 17a is patterned by photolithography, the upper interconnect 17 is formed on a predetermined position of the upper surface of the second insulating material 15, as shown in fig. 14. In this state, the upper interconnect 17 is connected to the upper surface of the columnar electrode 12 through the opening portion 16 in the second insulating material 15. The copper foil 1a and the metal film 1b formed on the lower surface thereof form a metal layer 1.

As shown in fig. 15, an upper insulating film 18 composed of a solder resist is formed on the entire upper surface of the second insulating material 15 including the upper interconnections 17 by screen printing or spin coating. In this case, the upper insulating film 18 has opening portions 19 at positions corresponding to the connection pad portions of the upper interconnections 17. Further, an insulating layer 2 composed of a solder resist is formed on the lower surface of the metal layer 1 by spin coating. Subsequently, the protruding electrode 20 is formed in and on the opening portion 19 and connected to the connection pad portion of the upper interconnect 17.

As shown in fig. 16, when the upper insulating film 18, the first and second insulating materials 14 and 15, the metal layer 1, and the insulating layer 2 are cut between the adjacent semiconductor members 3, the semiconductor device shown in fig. 1 is obtained.

In the semiconductor device thus obtained, the upper interconnection 17 on the electrode 12 of the pillar to be connected to the semiconductor member 3 is formed by electroless plating (or sputtering) and electroplating. For this reason, the electrical connection between each upper interconnect 17 and the corresponding columnar electrode 12 of the semiconductor member 3 can be reliably ensured.

In the above-described manufacturing method, the plurality of semiconductor members 3 are provided on the copper foil 1a via the adhesive layer 4. For the plurality of semiconductor members 3, the first and second insulating materials 14 and 15, the upper interconnect 17, the upper insulating film 18, and the protruding electrode 20 may be formed at a time. Thereafter, the semiconductor structures are separated, thereby obtaining a plurality of semiconductor devices. Therefore, the manufacturing steps can be simplified. Further, as seen from the manufacturing step shown in fig. 12, a plurality of semiconductor members 3 can be conveyed together with the copper foil 1 a. This also simplifies the manufacturing steps.

In the above-described manufacturing method, as shown in fig. 10, the CSP type semiconductor member 3 having the interconnections 11 and the columnar electrodes 12 is bonded to the copper foil 1a via the adhesive layer 4. The cost is reduced as compared with the case where, for example, a standard semiconductor chip having the connection pads 6 and the insulating film 7 on the silicon substrate 5 is bonded to the copper foil 1a, and the interconnects and the columnar electrodes are formed on a sealing film formed around the semiconductor chip.

For example, it is assumed that the copper foil 1a before cutting has an almost circular shape of a predetermined size, such as a silicon wafer. In this case, if the interconnects and the columnar electrodes are formed on the sealing film formed around the semiconductor chip bonded to the copper foil 1a, the processing area increases. In other words, since the low density process is performed, the number of wafers processed per cycle is reduced. This reduces yield and increases cost.

In contrast, in the above-described manufacturing method, the CSP type semiconductor member 3 having the interconnect 11 and the columnar electrode 12 is bonded to the copper foil 1a via the adhesive layer 4, and then build-up (build-up) is performed. Although the number of processes increases, the efficiency improves because high-density processing is performed until the columnar electrodes 12 are formed. For this reason, even if the increase in the number of processes is considered, the total cost can be reduced.

In the above-described embodiment, the protruding electrodes 20 are arranged in a matrix and correspond to the entire surface of the semiconductor member 3 and the first insulating material 14 therearound. However, the protruding electrodes 20 may be arranged only on the regions corresponding to the first insulating material 14 around the semiconductor member 3. The protruding electrodes 20 may be formed not to always surround the semiconductor member 3 but on one to three sides of the four sides of the semiconductor member 3. In this case, the first insulating material 14 does not have to have a rectangular frame shape, and may be provided only on the side where the protruding electrode 20 is to be formed.

(second embodiment)

Fig. 17 is a sectional view of a semiconductor device according to a second embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 1 in that it does not have an insulating layer 2.

In manufacturing the semiconductor device according to the second embodiment, in the manufacturing step shown in fig. 15, the insulating layer 2 is not formed on the lower surface of the metal layer 1. After the formation of the protruding electrodes 20, the upper insulating film 18, the first and second insulating materials 14 and 15, and the metal layer 1 are cut between the adjacent semiconductor members 3. Thus, a plurality of semiconductor devices shown in fig. 17 were obtained. The plurality of semiconductor devices thus obtained can be very thin because of the absence of the insulating layer 2.

(third embodiment)

Fig. 18 is a sectional view of a semiconductor device according to a third embodiment of the present invention. Such a semiconductor device can be obtained by omitting the formation of the metal layer 1b on the upper surface of the copper foil 1a in the manufacturing step shown in fig. 13 and the formation of the insulating layer 2 in the manufacturing step shown in fig. 15.

(fourth embodiment)

Fig. 19 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. Such a semiconductor device can be obtained by omitting the formation of the metal layer 1b on the lower surface of the copper foil 1a in the manufacturing step shown in fig. 13 and the formation of the insulating layer 2 in the manufacturing step shown in fig. 15.

(fifth embodiment)

Fig. 20 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 1 in that it has neither a metal layer 1 nor an insulating layer 2.

In manufacturing the semiconductor device according to the fifth embodiment, for example, in the manufacturing step shown in fig. 15, the formation of the insulating layer 2 on the lower surface of the metal layer 1 is omitted. After the formation of the protruding electrode 20, the metal layer 1 is removed by polishing or etching. Subsequently, the upper insulating film 18 and the first and second insulating materials 14 and 15 are cut between the adjacent semiconductor members 3. Thus, a plurality of semiconductor devices shown in fig. 20 are obtained. The semiconductor device thus obtained can be very thin since it has neither a metal layer 1 nor an insulating layer 2.

(sixth embodiment)

Fig. 21 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention. Such a semiconductor device can be obtained in the following manner. For example, in the state shown in fig. 19, the metal layer 1 is removed by polishing or etching. Then, the lower surface side of the silicon substrate 5 including the adhesive layer 4 and the lower surface side of the first insulating material 14 are appropriately polished. Next, the upper insulating film 18 and the first and second insulating materials 14 and 15 are cut between the adjacent semiconductor members 3, thereby obtaining a semiconductor device. The semiconductor device thus obtained can be made thinner.

Alternatively, the metal layer 1 is removed by polishing or etching before the formation of the protruding electrodes 20 (if necessary, the lower surface side of the silicon substrate 5 including the adhesive layer 4 and the lower surface side of the first insulating material 14 are also appropriately polished). Then, the protruding electrodes 20 are formed, and the upper insulating film 18 and the first and second insulating materials 14 and 15 are cut between the adjacent semiconductor members 3.

(seventh embodiment)

Fig. 22 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 1 in that it has neither a metal layer 1 nor an insulating layer 2, but has a substrate 31 in place of them.

In manufacturing the semiconductor device according to the seventh embodiment, in the manufacturing step shown in fig. 10, the formation of the adhesive layer 32 and the copper foil 1a on the upper surface of the substrate 31 is omitted. The semiconductor member 3 is bonded to the upper surface of the substrate 31 via an adhesive layer 4 formed on the lower surface thereof. Nothing is formed on the lower surface of the substrate 31. After the formation of the protruding electrodes 20, the upper insulating film 18, the first and second insulating materials 14, 15, and the substrate 31 are cut between the adjacent semiconductor members 3. Thus, a plurality of semiconductor devices shown in fig. 22 were obtained.

(eighth embodiment)

Fig. 23 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 1 in that a lower interconnection 41 is formed on the lower surfaces of the adhesive layer 4 and the first insulating material 14 and is connected to an upper interconnection l7 through a vertical electrical connection portion 43, wherein the vertical electrical connection portion 43 is formed on the inner surface of a through-hole 42, and the through-hole 42 is formed at a predetermined position of the first and second insulating materials 14 and 15 formed around the semiconductor member 3.

In manufacturing the semiconductor device according to the eighth embodiment, for example, after the manufacturing step shown in fig. 11, the substrate 31, the adhesive layer 32, and the copper foil 1a are removed by polishing or etching. Next, as shown in fig. 24, an opening portion 16 is formed in the second insulating material 15 at a position corresponding to a central portion of the upper surface of the columnar electrode 12 by laser processing. Further, the through-hole 42 is formed at a predetermined position of the first and second insulating materials 14 and 15 provided around the semiconductor member 3.

As shown in fig. 25, the copper electroless plating and the copper plating are continuously performed to form the upper interconnect forming layer 17a on the entire upper surface of the second insulating material 15 including the upper surfaces of the columnar electrodes 12 exposed through the opening portions l 6. Further, the lower interconnect forming layer 41a is formed on the entire lower surface of the adhesive layer and the first insulating material 14. Then, the vertical electrical connection portion 43 is formed on the inner surface of the through-hole 42.

Next, the upper interconnect-forming layer 17a and the lower interconnect-forming layer 41a are patterned by photolithography. For example, as shown in fig. 23, the upper interconnect 17 is formed on the upper surface of the second insulating material 15, the lower interconnect 41 is formed on the lower surfaces of the adhesive layer 4 and the first insulating material 14, and the vertical electrical connection portion 43 is left on the inner surface of the through-hole 42.

This will be explained with reference to fig. 23. An upper insulating film 18 made of a solder resist and having an opening portion 19 is formed on the upper surface of the second insulating material 15 including the upper interconnection 17. Further, a lower insulating film 44 made of a solder resist is formed on the entire lower surface of the first insulating material 14 including the lower interconnection 41. In this case, the vertical electrical connection portions 43 are filled with a solder resist. Next, the bump electrodes 20 are formed, and the upper insulating film 18, the first and second insulating materials 14, 15, and the lower insulating film 44 are cut between the adjacent semiconductor members 3. Thus, a plurality of semiconductor devices shown in fig. 23 are obtained.

(ninth embodiment)

Fig. 26 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 23 in that a lower interconnection 41 is formed of a copper foil 1a and a copper layer 41a formed on the lower surface of the copper foil 1a, and vertical electrical connection portions 43 are formed in a through-hole 42 without forming any gap.

In manufacturing the semiconductor device according to the ninth embodiment, for example, in the manufacturing step shown in fig. 12, the opening portion 16 is formed in the second insulating material 15 at a position corresponding to the central portion of the upper surface of the columnar electrode 12 by laser processing, as shown in fig. 27. Further, a through hole 42 is formed at a predetermined position of the first and second insulating materials 14, 15 provided around the semiconductor member 3. In this case, the copper foil 1a is formed on the entire lower surface of the adhesive layer 4 and the first insulating material 14. Therefore, the lower surface side of the through hole 42 is covered with the copper foil 1 a.

As shown in fig. 28, copper plating is performed using the copper foil 1a as a plating current path, thereby forming vertical electrical connection portions 43 on the upper surface of the copper foil 1a in the through-hole 42. In this case, the upper surface of the vertical electrical connection portion 43 is preferably almost flush with the upper plane of the through-hole 42 or located slightly below.

Next, as shown in fig. 29, the copper electroless plating and the copper electroplating are successively performed to form an upper interconnect forming layer 17a on the entire upper surface of the second insulating material 15 including the upper surfaces of the columnar electrodes 12 exposed through the opening portions 16 and the upper surfaces of the vertical electrical connection portions 43 in the through holes 42. Further, a lower interconnection forming layer 41a is formed on the entire lower surface of the copper foil 1 a. Then, with the same manufacturing steps as those of the eighth embodiment, a plurality of semiconductor devices shown in fig. 26 are obtained.

(tenth embodiment)

Fig. 30 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 1 in that it is free of the second insulating material 15.

In manufacturing the semiconductor device of the tenth embodiment, the substrate 31 and the adhesive layer 32 are removed after the manufacturing step shown in fig. 11. Further, the second insulating material 15 is removed by polishing. In this case, when the second insulating material 15 is removed by polishing, if the upper surface side of the sealing film 13 including the columnar electrode 12 and the semiconductor member 3 and the upper surface side of the first insulating material 14 are slightly polished, no problem occurs.

The subsequent manufacturing steps are the same as those of the first embodiment. However, in the tenth embodiment, as shown in fig. 30, the upper interconnect 17 is formed on the upper surfaces of the semiconductor member 3 and the first insulating material 14 and connected to the upper surface of the columnar electrode 12. An upper insulating film 18 having an opening portion 19 is formed on the upper interconnect 17. A protruding electrode 20 is formed in and on the opening portion 19 and connected to the connection pad portion of the upper interconnect 17. Although not shown, if the columnar electrodes 12 are arranged in a matrix, it is of course possible to introduce the upper interconnections 17 between the columnar electrodes 12.

(eleventh embodiment)

Fig. 31 is a sectional view of a semiconductor device according to an eleventh embodiment of the present invention. Such a semiconductor device is obtained by removing the second insulating material 15 by polishing in fig. 23, as in the tenth embodiment.

(twelfth embodiment)

Fig. 32 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention. Such a semiconductor device is obtained by removing the second insulating material 15 by polishing in fig. 26, as in the tenth embodiment.

(thirteenth embodiment)

In the above-described embodiment, for example, as shown in fig. 1, the upper interconnect 17 and the upper insulating film 18 each including one layer are formed on the second insulating material 15. However, the present invention is not limited thereto. Upper interconnections 17 and upper insulating films 18 each including two or more layers may also be formed. For example, as in the thirteenth embodiment of the present invention shown in fig. 33, each of the upper interconnect 17 and the upper insulating film 18 may have two layers.

More specifically, in this semiconductor device, the first upper interconnect 51 is formed on the upper surface of the second insulating material 15 and connected to the upper surface of the columnar electrode 12 through the opening portion 16 formed in the second insulating material 15. A first upper insulating film 52 composed of an epoxy resin or a polyimide resin is formed on the upper surface of the second insulating material 15 including the first upper interconnection 51. The second upper interconnection 54 is formed on the upper surface of the first upper insulating film 52 and connected to the upper surface of the connection pad portion of the first upper interconnection 51 through the opening portion 53 formed in the first upper insulating film 52.

A second upper insulating film 55 composed of a solder resist is formed on the upper surface of the first upper insulating film 52 including the second upper interconnection 54. The second upper insulating film 55 has opening portions 56 at positions corresponding to the connection pad portions of the second upper interconnections 54. The protruding electrodes 20 are formed in and on the opening portions 56 and connected to the connection pad portions of the second upper interconnections 54. In this case, only the copper foil 1a is formed on the lower surfaces of the adhesive layer 4 and the first insulating material 14.

(fourteenth embodiment)

For example, in fig. 16, the resulting member is cut between the semiconductor members 3 adjacent to each other. However, the present invention is not limited thereto. The resulting member may be cut for every two or more semiconductor members. For example, as in the fourteenth embodiment of the present invention, as shown in fig. 34, the resulting members are cut for every three semiconductor members 3, thereby obtaining a multi-chip module type semiconductor device. In this case, the three semiconductor members 3 may be of the same type or different types.

In the above-described embodiment, the semiconductor member 3 and the first insulating material 14 are formed in the following state: wherein the lower surface of the semiconductor member 3 is supported by the substrate 31. After forming the second insulating material 15 on the semiconductor member 3 and the first insulating material 14, the substrate 31 is removed. The substrate 31 is not left in the completed semiconductor device. However, an organic material such as an epoxy-based material or a polyimide-based material or a thin plate formed of a thin metal film may also be used as the material of the substrate 31. After the upper interconnection 17 and the upper insulating film 18 are formed, as necessary, after the protrusion electrode 20 is formed, the substrate 31 is cut together with the upper insulating film 18, the second insulating material 15, and the first insulating material 14, thereby leaving the substrate 31 as a base member of the semiconductor device. In this case, the base may be cut after forming interconnections or the like on the surface of the substrate 31 on the opposite side of the mounting surface of the semiconductor member 3.

In the first to fourteenth embodiments described above, the semiconductor device is basically manufactured by forming the insulating film while supporting the lower surface of each semiconductor member 3 by the substrate 31.

However, the semiconductor device can be manufactured by forming the insulating film and the interconnection while supporting the upper surface of each semiconductor member 3 by the substrate 31. This method will be described in detail below.

(fifteenth embodiment)

A semiconductor device according to a fifteenth embodiment shown in fig. 35 represents an embodiment manufactured by the latter method. Note that the purpose of this embodiment is to indicate that not only the structure shown in fig. 35 can be obtained by the latter method but also a semiconductor device having one of the structures according to the above-described first to fourteenth embodiments can be manufactured by the latter method. This will be explained below in a suitable step.

The semiconductor device shown in fig. 35 is different from the semiconductor devices of the first to fourteenth embodiments in that: the lower surface of the semiconductor member 3 is directly bonded to the insulating layer 2 without interposing any adhesive layer. The insulating layer 2 is formed on the lower surface of the semiconductor member 3 by printing or spin coating, which will be described later.

A method of manufacturing a semiconductor device according to a fifteenth embodiment is described below.

With the steps shown in fig. 2 to 7, the interconnect 11 and the sealing film 13 are formed on the silicon substrate 5 in a wafer state so that the interconnect 11 and the sealing film 13 are flush with each other.

In this state, dicing is performed without forming any adhesive layer on the lower surface of the silicon substrate 5, thereby obtaining a plurality of semiconductor members 3 shown in fig. 35, as shown in fig. 36.

As shown in fig. 37, a substrate 31 is prepared. The substrate 31 has a plurality of semiconductor devices corresponding to those shown in fig. 35. The substrate 31 is made of metal such as aluminum and has a rectangular planar shape, more preferably, an almost square planar shape, but the shape is not limited thereto. The substrate 31 may be made of an insulating material such as glass, ceramic, or resin.

The second insulating sheet member 15a is bonded to the entire upper surface of the base plate 31. The second insulating sheet member 15a is preferably made of aggregate material, but the present invention is not limited thereto. As the aggregate material, a thermosetting resin such as an epoxy resin or a BT resin, which is mixed with a silica filler and semi-cured, may be used. However, as the second insulating sheet member 15a, the above prepreg or a material containing no filler or containing only a thermosetting resin may be used. The thermosetting resin is semi-cured (semi-set) by heating and pressing, and the second insulating sheet member 15a is bonded to the entire upper surface of the substrate 31.

The semiconductor construct 3 shown in fig. 36 is turned upside down and disposed on a plurality of predetermined positions on the upper surface of the second insulating sheet member 15a in a face-down state. The semiconductor member 3 is heated and pressed to temporarily cure the thermosetting resin in the second insulating sheet member 15a, so that the lower surface of the second insulating sheet member 15a is temporarily adhered to the upper surface of the base plate 31.

Two first insulating plate members 14a and 14b each having opening portions arranged in a matrix are aligned and stacked on the upper surface of the second insulating plate member 15a between the semiconductor members 3 and between the outsides of the semiconductor members disposed at the outermost positions. The first insulating sheet members 14a and 14b are obtained as follows. The glass fibers are impregnated with a thermosetting resin such as an epoxy resin. The thermosetting resin is semi-cured to prepare a sheet-like prepreg. A plurality of rectangular opening portions 33 are formed in the prepreg material by punching or etching.

In this case, in order to obtain flatness, each of the first insulating sheet members 14a and 14b must be a plate-like member. However, the material need not always be a prepreg material. A thermosetting resin or a thermosetting resin in which a reinforcing material such as glass fiber or silica filler is dispersed may also be used.

The size of the opening portion 33 of the first insulating sheet members 14a and 14b is slightly larger than that of the semiconductor member 3. For this reason, a gap 34 is formed between the first insulating plate members 14a and 14b and the semiconductor member 3. The length of the gap 34 is, for example, approximately 0.1-0.5 mm. The total thickness of the first insulating sheet members 14a and 14b is larger than the thickness of the semiconductor member 3. The first insulating sheet members 14a and 14b are thick enough to sufficiently fill the gap 34 when the first insulating sheet members are heated and pressurized, which will be described later.

In this case, the first insulating sheet members 14a and 14b having the same thickness are used. However, the first insulating sheet members 14a and 14b may have different thicknesses. The second insulating sheet member may comprise two layers, as described above. However, one or three or more layers may be included. The thickness of the second insulating sheet member 15a corresponds to or is slightly larger than the thickness of the second insulating material 15 to be formed on the semiconductor member 3 in fig. 35.

Next, the second insulating sheet member 15a and the first insulating sheet members 14a and 14b are heated and pressed by using a pair of heating/pressing plates 35 and 36, as shown in fig. 38. Thus, the molten thermosetting resin in the first insulating sheet members 14a and 14b is pressed so as to fill the gap 34 between the first insulating sheet members 14a, 14b and the semiconductor member 3, as shown in fig. 37. By the subsequent cooling process, the thermosetting resin is cured while adhering to the semiconductor member 3. In this way, as shown in fig. 38, the second insulating material 15 made of a thermosetting resin containing a reinforcing material is formed and adhered onto the upper surface of the substrate 31. Further, the semiconductor member 3 is bonded to the upper surface of the second insulating material 15. Further, a first insulating material 14 made of a thermosetting resin containing a reinforcing material is formed and adhered on the upper surface of the second insulating material 15.

In this case, as shown in fig. 36, the columnar electrodes 12 in each semiconductor member 3 have a uniform height in the wafer state. Further, the upper surface of the sealing film 13 including the upper surfaces of the columnar electrodes 12 is planarized. For this reason, in the state shown in fig. 38, the plurality of semiconductor members 3 have the same thickness.

In the state shown in fig. 38, heating and pressing are performed while a virtual plane higher than the upper surface of the semiconductor member 3 is defined by the diameter of the reinforcing material (e.g., silica filler) as a pressure limiting surface. The second insulating material 15 underneath the semiconductor member 3 obtains a thickness equal to the diameter of the reinforcing material (for example silica filler). When an open-ended (open) flat press is used as the press having a pair of heating/pressing plates 35 and 36, the excess thermosetting resin in the insulating plate members 14a, 14b, and 15a is extruded out of the pair of heating/pressing plates 35 and 36.

As a result, the upper surface of the first insulating material 14 becomes flush with the upper surface of the semiconductor member 3. The lower surface of the second insulating material 15 is flat because the surface is regulated by the upper surface of the lower heating/pressing plate 35. Therefore, it is not necessary to perform a polishing step of planarizing the upper surface of the first insulating material 14 and the lower surface of the second insulating material 15. Even if the substrate 31 has a relatively large size, for example, about 500 × 500mm, the first and second insulating materials 14, 15 can be easily planarized at a time with respect to the plurality of semiconductor members 3 provided on the substrate 31.

The first and second insulating materials 14 and 15 are composed of a thermosetting resin containing a reinforcing material such as a fiber or a filler. For this reason, stress due to shrinkage in curing of the thermosetting resin can be reduced as compared with a structure composed of only the thermosetting resin. This also prevents the substrate 31 from bending.

In the manufacturing step shown in fig. 38, heating and pressing may be performed by separate devices. That is, for example, the lower surface of the semiconductor member 3 may be heated by the heater while the pressing is performed only from the upper surface side. Alternatively, the heating and pressurizing may be performed in separate steps.

When the manufacturing step shown in fig. 38 is finished, the semiconductor member 3 and the first and second insulating materials 14 and 15 are integrated together. They retain only the required strength. Next, the substrate 31 is peeled or removed by polishing or etching. Such a process is performed in order to reduce a load in dicing (which will be described later) and to reduce the thickness of a semiconductor device as a product.

Next, the resultant member shown in fig. 38 in which the semiconductor member 3 and the first and second insulating materials 14, 15 are integrated is inverted and set in a face-up state. As shown in fig. 39, an opening portion 16 is formed in the second insulating material 15 at a position corresponding to the central portion of the upper surface of the columnar electrode 12 by a laser machining method of irradiating the second insulating material 15 with a laser beam. Then, the epoxy oil stain generated in the opening portion 16 is removed by degreasing treatment as needed.

As shown in fig. 40, the upper interconnect forming layer 17a is formed on the entire upper surface of the second insulating material 15 including the upper surfaces of the columnar electrodes 12 exposed through the opening portions 16. In this case, the upper interconnect formation layer 17a includes a lower metal layer formed of, for example, a copper layer formed by electroless plating and an upper metal layer formed on a surface of the lower metal layer by performing copper electroplating by using the lower metal layer as an electroplating current path.

When the upper interconnect forming layer 17a is patterned by photolithography, the upper interconnect 17 is formed on a predetermined position of the upper surface of the second insulating material 15, as shown in fig. 41. In this state, the upper interconnect 17 is connected to the upper surface of the columnar electrode 12 through the opening portion 16 in the second insulating material 15.

As shown in fig. 42, the upper insulating film 18 composed of a solder resist is formed on the entire upper surface of the second insulating material 15 including the upper interconnect 17 by screen printing or spin coating. In this case, the upper insulating film 18 has opening portions 19 at positions corresponding to the connection pad portions of the upper interconnections 17. Further, the insulating layer 2 composed of a solder resist is formed on the lower surfaces of the silicon substrate 5 and the first insulating material 14 by printing or spin coating. Subsequently, the protruding electrode 20 is formed in and on the opening portion 19 and connected to the connection pad portion of the upper interconnect 17.

As shown in fig. 43, when the upper insulating film 18, the first and second insulating materials 14 and 15, and the insulating layer 2 are cut between the adjacent semiconductor members 3, the semiconductor device shown in fig. 35 is obtained.

In the semiconductor device thus obtained, the upper interconnection 17 on the electrode 12 of the pillar to be connected to the semiconductor member 3 is formed by electroless plating (or sputtering) and electroplating. For this reason, the electrical connection between each upper interconnect 17 and the corresponding columnar electrode 12 of the semiconductor member 3 can be reliably ensured. In the state shown in fig. 41, when the insulating layer 2 having the metal layer 1 is adhered with an adhesive layer, instead of forming the insulating layer 2 on the lower surfaces of the silicon substrate 5 and the first insulating material 14, the semiconductor device according to the first embodiment shown in fig. 1 can be obtained. It should be fully understood that the semiconductor device according to any one of the second to fourteenth embodiments other than the first embodiment can also be obtained, although the detailed description is omitted.

In the above-described manufacturing method, the plurality of semiconductor members 3 are provided on the second insulating sheet member 15a located on the substrate 31. The first and second insulating materials 14 and 15 may be formed at a time for a plurality of semiconductor members 3. After that, the substrate 31 is removed. Then, for the plurality of semiconductor members 3, the upper interconnections 17, the upper insulating film 18, and the protruding electrodes 20 are formed at once. After that, the semiconductor members are separated, thereby obtaining a plurality of semiconductor devices. Therefore, the manufacturing steps can be simplified.

Further, as seen from the manufacturing step shown in fig. 38, even if the substrate 31 is removed, the plurality of semiconductor members 3 can be conveyed together with the first and second insulating materials 14 and 15. This also simplifies the manufacturing steps. Further, in the above-described manufacturing method, as shown in fig. 37, the semiconductor member 3 is bonded to the substrate 31 via the second insulating sheet member 15 a. Therefore, a process for forming the adhesion difference is not required. When removing the substrate 31, only the substrate 31 has to be removed. This also simplifies the manufacturing steps.

In the above-described manufacturing method, the protruding electrodes 20 are arranged in a matrix and correspond to the entire surface of the semiconductor member 3 and the first insulating material 14 therearound. However, the protruding electrode 20 may be provided only on a region corresponding to the first insulating material 14 around the semiconductor member 3. The protruding electrodes 20 may not entirely surround the semiconductor member 3, but surround only one to three sides among four sides of the semiconductor member 3. In this case, the first insulating material 14 does not have to have a rectangular frame shape and may be provided only on the side where the protruding electrode 20 is to be formed.

(sixteenth embodiment)

Fig. 44 is a sectional view of a semiconductor device according to a sixteenth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 35 in that it does not have the insulating layer 2.

In the manufacture of the semiconductor device according to the sixteenth embodiment, in the manufacturing step shown in fig. 42, the insulating layer 2 is not formed on the lower surfaces of the silicon substrate 5 and the first insulating material 14. After the formation of the protruding electrodes 20, the upper insulating film 18, and the first and second insulating materials 14 and 15 are cut between the adjacent semiconductor members 3. Thus, a plurality of semiconductor devices shown in fig. 44 are obtained. The semiconductor device thus obtained can be very thin because it has no insulating layer 2.

(seventeenth embodiment)

Fig. 45 is a cross-sectional view of a semiconductor device according to a seventeenth embodiment of the present invention. Such a semiconductor device can be obtained by: for example, in the state shown in fig. 44, the lower surface side of the silicon substrate 5 and the first insulating material 14 is appropriately polished and the upper insulating film 18 and the first and second insulating materials 14 and 15 are cut between the adjacent semiconductor members 3. The semiconductor device thus obtained can be thinner.

Before the formation of the protruding electrode 20, the insulating layer 2 may be removed by polishing or etching (if necessary, the lower surface side of the silicon substrate 5 and the first insulating material 14 may be appropriately polished). Then, the protruding electrode 20 may be formed, and the upper insulating film 18 and the first insulating material 14 may be cut between the adjacent semiconductor members 3.

(eighteenth embodiment)

Fig. 46 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in fig. 35 in that a second insulating material 15A is provided on the upper surface of the semiconductor member 3, and a first insulating material 14A is provided on the upper surface of the insulating layer 2 surrounding the semiconductor member 3 and the second insulating material 15A.

In the manufacture of the semiconductor device according to the eighteenth embodiment, after the manufacturing step shown in fig. 7, the plate-like first insulating plate 15A is adhered to the entire upper surface of the sealing film 13 including the upper surfaces of the columnar electrodes 12, as shown in fig. 47.

Next, as shown in fig. 48, a dicing step is performed, thereby obtaining a plurality of semiconductor members 3. In this case, however, the first insulating sheet member 15A is adhered to the upper surface of the sealing film 13 including the upper surface of the semiconductor member 3. The semiconductor member 3 thus obtained has a plate-like first insulating plate 15A on the upper surface thereof. Therefore, a very troublesome operation for adhering the first insulating sheet member 15A to the upper surface of each semiconductor member 3 after the dicing step is not required.

As shown in fig. 49, the semiconductor member 3 shown in fig. 48 is inverted and set in a face-down state, so that the first insulating sheet member 15A bonded to the lower surface of the semiconductor member 3 is bonded to a plurality of predetermined positions on the upper surface of the substrate 31 by using the first insulating sheet member 15A of appropriate viscosity. Heat and pressure are applied to temporarily cure the thermosetting resin in the first insulating sheet member 15A, so that the lower surface of the first insulating sheet member 15A is temporarily adhered to the upper surface of the substrate 31. Further, the lower surface of the semiconductor member 3 is temporarily bonded to the upper surface of the first insulating plate member 15A. Two first insulating sheet members 14a and 14b each having an opening portion 33 are aligned and stacked on the upper surface of the substrate 31 between the semiconductor constructions 3 and between the outsides of the semiconductor constructions 3 disposed at the outermost positions.

Also in this case, the size of the opening portion 33 of the first insulating plate members 14a and 14b is slightly larger than that of the semiconductor member 3. For this reason, a gap 34 is formed between the first insulating sheet members 14a and 14b and the semiconductor member 3 including the first insulating sheet member 15A. The length of the gap 34 is, for example, approximately 0.1-0.5 mm. The total thickness of the first insulating sheet members 14a and 14b is larger than the thickness of the semiconductor member 3 including the first insulating sheet member 15A. The first insulating sheet members 14a and 14b are sufficiently thick to substantially fill the gap 34 when the first insulating sheet members are heated and pressed, as described later.

Next, the first insulating plate member 15A and the first insulating plate members 14a and 14b are heated and pressed using a pair of heating/pressing plates 35 and 36, as shown in fig. 50. Thus, the molten thermosetting resin in the first insulating sheet members 14a and 14b is pressed so as to fill the gap 34 between the first insulating sheet members 14a, 14b and the semiconductor construct 3 including the first insulating sheet member l5A, as shown in fig. 49. By the subsequent cooling process, the thermosetting resin is cured while adhering to the semiconductor construct 3 and the substrate 31 therebetween.

In this way, as shown in fig. 50, the second insulating material 15A made of a thermosetting resin containing a reinforcing material is formed and adhered to a plurality of predetermined positions on the upper surface of the substrate 31. Further, the semiconductor member 3 is bonded to the upper surface of the second insulating material 15A. Further, the first insulating material 14 composed of a thermosetting resin containing a reinforcing material is formed and adhered onto the upper surface of the substrate 31 between the semiconductor member 3 and the outside of the semiconductor member located at the outermost position. The semiconductor device shown in fig. 46 is obtained by the same manufacturing steps as those of the fifteenth embodiment.

In the above-described embodiment, the semiconductor member 3 has the interconnect 11 and the columnar electrode 12 as the external connection electrodes, in addition to the connection pad 6. The present invention can also be applied to the following semiconductor member 3: it has only the connection pad 6 as an external connection electrode or the connection pad 6 and the interconnect 11 having a connection pad portion.

As has been described previously, according to the present invention, at least some of the connection pad portions of the uppermost upper interconnections are provided on the first insulating material formed on the semiconductor member side. For this reason, even if the number of connection pad portions of the uppermost upper interconnection is increased, a desired size and pitch can be secured.

Claims (42)

1. A semiconductor device characterized by comprising:

at least one semiconductor component (3) having: a semiconductor substrate (5) provided with a plurality of connection pads (6), an insulating film (9) formed on the semiconductor substrate (5) and having opening portions (10) that expose the connection pads (6), interconnects (11) connected to the connection pads (6) via the opening portions (10) and extending onto the insulating film (9), and a plurality of external connection electrodes (12) provided on the interconnects (11);

a first insulating material (14, 14A) disposed around the semiconductor member (3); and

a plurality of upper interconnections (17, 54) having connection pad portions, wherein the connection pad portions are disposed on the first insulating material (14, 14A) and correspond to the upper interconnections, and are electrically connected to external connection electrodes (12) of the semiconductor member (3).

2. A semiconductor device according to claim 1, characterized by comprising a plurality of semiconductor members (3).

3. A semiconductor device according to claim 1, characterized in that the first insulating material (14, 14A) is mainly made of a material prepared by impregnating fibers with a thermosetting resin.

4. A semiconductor device according to claim 1, characterized in that the second insulating material (15) is formed between the first insulating material (14) and the upper interconnect (17) and between the above-mentioned upper interconnect (17) and the semiconductor member (3).

5. A semiconductor device according to claim 4, characterized in that the second insulating material (15, 15A) is a plate.

6. A semiconductor device according to claim 4, characterized in that the upper surface of the second insulating material (15, 15A) is flat.

7. The semiconductor device according to claim 1, further comprising an upper insulating film (18, 52) covering a portion other than the connection pad portion of the upper interconnect (17, 54).

8. A semiconductor device according to claim 7, characterized in that the solder balls (20) are formed on the connection pad portions of the upper interconnections (17, 54).

9. A semiconductor device according to claim 1, characterized in that the metal layer (1, 1a) is formed on the lower surface of the semiconductor member (3) and the first insulating material (14, 14A).

10. A semiconductor device according to claim 9, characterized in that the insulating layer (2) is formed on the lower surface of the metal layer (1).

11. A semiconductor device as claimed in claim 9, characterized in that the metal layer (1, 1a) has at least a metal foil.

12. The semiconductor device according to claim 11, wherein the metal foil is a copper foil.

13. A semiconductor device according to claim 1, characterized in that the lower interconnection (41) is formed on at least the lower surface of the first insulating material (14, 14A), and the upper interconnection (17) and the lower interconnection (41) are connected by a vertical electrical connection portion (43) formed in the first insulating material (14).

14. A semiconductor device according to claim 1, characterized in that the first insulating material (14) has a multilayer structure of a plurality of insulating sheet members (14a, 14 b).

15. The semiconductor device according to claim 1, wherein the first insulating material (14A) has a thickness larger than that of the semiconductor member (3) and is formed in a frame shape covering the periphery of the semiconductor member (3), a second insulating material (15A) is formed in a central portion of the first insulating material (14A) corresponding to the semiconductor member (3), and an upper surface of the first insulating material (14A) is flush with an upper surface of the second insulating material (15A).

16. A semiconductor device manufacturing method, comprising:

providing a plurality of semiconductor members (3) on a substrate (31), each of which has a semiconductor substrate (5) provided with a plurality of connection pads (6), an insulating film (9) formed on the semiconductor substrate (5) and having an opening portion (10) exposing each of the connection pads (6), interconnects (11) connected to the connection pads (6) via the opening portions (10) respectively and extending onto the insulating film (9), a plurality of columnar electrodes (12) for external connection provided on the interconnects (11), and a sealing film (13) provided between the columnar electrodes (12) on the semiconductor substrate (5), simultaneously separating the semiconductor members from each other, and providing at least one first insulating material (14) having an opening portion (33) at a position corresponding to each of the semiconductor members (3);

heating and pressurizing the first insulating material (14) from an upper side of the first insulating material (14), thereby melting and solidifying the first insulating material (14) between the semiconductor members;

forming at least one layer of upper interconnections (17, 54) having connection pad portions and connected to respective ones of a plurality of connection pads (6) of one of the plurality of semiconductor members (3) so as to place the connection pad portions on the first insulating material (14) corresponding to the upper interconnections; and

the first insulating material (14) is cut between the semiconductor members (3), thereby obtaining a plurality of semiconductor devices in which the connection pad portions of the upper interconnections (17, 54) are disposed on the first insulating material (14).

17. A semiconductor device manufacturing method according to claim 16, characterized in that in cutting the first insulating material (14), the first insulating material (14) is cut so that each semiconductor device includes a plurality of semiconductor members (3).

18. A semiconductor device manufacturing method according to claim 16, characterized in that the substrate (31) is removed before the first insulating material (14) is cut.

19. A semiconductor device manufacturing method according to claim 16, characterized in that after the first insulating material (14) is cut, the substrate (31) is removed.

20. A semiconductor device manufacturing method according to claim 16, wherein the heating and pressing treatment is performed while providing the pressure limiting surface.

21. A semiconductor device manufacturing method according to claim 16, characterized in that the size of the opening portion (33) of the first insulating material (14) is slightly larger than the size of the semiconductor member (3).

22. A semiconductor device manufacturing method according to claim 21, characterized in that the thickness of the first insulating material (14) provided on the substrate (31) is larger than the thickness of the semiconductor member (3).

23. A semiconductor device manufacturing method according to claim 16, characterized in that the first insulating material (14) is mainly composed of a material prepared by impregnating fibers with a thermosetting resin.

24. A semiconductor device manufacturing method according to claim 16, characterized by further comprising the step of forming a second insulating material (15) between the first insulating material (14) and the upper interconnect (17).

25. A semiconductor device manufacturing method according to claim 24, characterized in that the second insulating material (15) is a plate.

26. A semiconductor device manufacturing method according to claim 16, characterized by further comprising forming a thin film (1a) to be removed from the substrate (31) on the substrate (31) before providing the semiconductor member (3) and the first insulating material (14) on the substrate (31).

27. A semiconductor device manufacturing method according to claim 26, characterized in that the thin film (1a) is mainly made of metal.

28. A semiconductor device manufacturing method according to claim 26, characterized in that the thin film (1a) is cut together with the first insulating material (14) at the time of cutting the first insulating material (14).

29. A semiconductor device manufacturing method according to claim 26, characterized in that after the semiconductor member (3) and the first insulating material (14) are provided on the film (1a), the first insulating material (14) is temporarily cured.

30. A semiconductor device manufacturing method according to claim 29, characterized in that after the temporary curing, the substrate (31) is removed.

31. A semiconductor device manufacturing method according to claim 30, characterized in that after the substrate (31) is removed, another thin film (1b, 2) is formed on the thin film (1 a).

32. A semiconductor device manufacturing method according to claim 31, characterized in that the thin film (1a) is a metal foil and the other thin film (1b) is a metal foil.

33. A semiconductor device manufacturing method according to claim 31, characterized in that the other film (2) is mainly made of an insulating material.

34. A semiconductor device manufacturing method according to claim 31, characterized in that the other film (1b, 2) is formed by stacking a plurality of layers made of different materials.

35. A semiconductor device manufacturing method according to claim 31, characterized in that the first insulating material (14), the thin film (1a), and the other thin films (1b, 2) are cut when the first insulating material (14) is cut.

36. A semiconductor device manufacturing method according to claim 16, characterized in that in cutting the first insulating material, the first insulating material (14) is cut while the substrate (31) is cut, so that the semiconductor device has the substrate (31).

37. A semiconductor device manufacturing method according to claim 16, further comprising a step of forming an upper insulating film (18, 55), the upper insulating film (18, 55) covering a portion other than the connection pad portion of the upper interconnect (17, 54).

38. A semiconductor device manufacturing method according to claim 37, characterized by further comprising the step of forming solder balls (20) on the connection pad portions of the upper interconnections (17, 54).

39. A semiconductor device manufacturing method according to claim 16, further comprising forming a via hole (42) in the first insulating material (14), forming a lower interconnect (41) on a lower surface of the first insulating material (14), and forming a vertical electrical connection portion (43) in the via hole (42), wherein the vertical electrical connection portion (43) connects the upper interconnect (17) and the lower interconnect (41).

40. A semiconductor device manufacturing method according to claim 39, wherein the substrate is removed before the via hole (42), the lower interconnection (41), and the vertical electrical connection portion (43) are formed.

41. A semiconductor device manufacturing method according to claim 16, characterized in that the method further comprises forming an upper insulating film (15a) on the substrate (31), and disposing the semiconductor member (3) on the upper insulating film (15a) such that the surface on which the connection pad (6) is formed is opposed to the upper insulating film (15 a).

42. A semiconductor device manufacturing method according to claim 41, wherein the first insulating material (14) is provided on the upper insulating film (15 a).