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HK1042380A1 - Method of protecting an underlying wiring layer during dual damascene processing - Google Patents

Method of protecting an underlying wiring layer during dual damascene processing Download PDF

Info

Publication number
HK1042380A1
HK1042380A1 HK02104146.3A HK02104146A HK1042380A1 HK 1042380 A1 HK1042380 A1 HK 1042380A1 HK 02104146 A HK02104146 A HK 02104146A HK 1042380 A1 HK1042380 A1 HK 1042380A1
Authority
HK
Hong Kong
Prior art keywords
protecting
wiring layer
layer during
dual damascene
damascene processing
Prior art date
Application number
HK02104146.3A
Other languages
Chinese (zh)
Inventor
A. Hussein Makarem
M. Myers Alan
H. Recchia Charles
Sivakumar Sam
W. Kandas Angelo
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/345,586 external-priority patent/US6406995B1/en
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of HK1042380A1 publication Critical patent/HK1042380A1/en

Links

Classifications

    • H10W20/085—
    • H10W20/01—
    • H10W20/077—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming an interconnection including the steps of forming a sacrificial material (160) that comprises a physical property that is generally insensitive to a photoreaction in a via (150) through a dielectric material (130) to a masking material (120) over a conductive material (110). The method also includes forming a trench (180) over in the dielectric material over the via (150) and removing the sacrificial material (160) from the via.
HK02104146.3A 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing HK1042380A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US345586 1999-06-30
US09/345,586 US6406995B1 (en) 1998-09-30 1999-06-30 Pattern-sensitive deposition for damascene processing
PCT/US2000/040108 WO2001001480A1 (en) 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing

Publications (1)

Publication Number Publication Date
HK1042380A1 true HK1042380A1 (en) 2002-08-09

Family

ID=23355627

Family Applications (1)

Application Number Title Priority Date Filing Date
HK02104146.3A HK1042380A1 (en) 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing

Country Status (8)

Country Link
EP (1) EP1192656A1 (en)
JP (1) JP4675534B2 (en)
KR (1) KR100452418B1 (en)
AU (1) AU5790800A (en)
HK (1) HK1042380A1 (en)
IL (2) IL147301A0 (en)
TW (1) TW531789B (en)
WO (1) WO2001001480A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6576550B1 (en) 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
JP2004503089A (en) * 2000-06-30 2004-01-29 インフィネオン　テクノロジーズ　アクチエンゲゼルシャフト Via-first dual damascene method for copper metallization
KR100393974B1 (en) * 2001-01-12 2003-08-06 주식회사 하이닉스반도체 Forming Method for Dual Damascene
KR100419901B1 (en) * 2001-06-05 2004-03-04 삼성전자주식회사 Method of fabricating semiconductor device having dual damascene interconnection
JP2002373936A (en) * 2001-06-14 2002-12-26 Nec Corp Wiring formation method by dual damascene method
KR100545220B1 (en) 2003-12-31 2006-01-24 동부아남반도체 주식회사 Dual damascene wiring formation method of semiconductor device
JP5096669B2 (en) 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
KR100691105B1 (en) * 2005-09-28 2007-03-09 동부일렉트로닉스 주식회사 Copper wiring formation method using dual damascene process
JP2009016596A (en) * 2007-07-05 2009-01-22 Elpida Memory Inc Semiconductor device and manufacturing method of semiconductor device
JP4891296B2 (en) * 2008-07-03 2012-03-07 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
JP5641681B2 (en) * 2008-08-08 2014-12-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Manufacturing method of semiconductor device
US10170354B2 (en) * 2015-04-12 2019-01-01 Tokyo Electron Limited Subtractive methods for creating dielectric isolation structures within open features

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0609496B1 (en) * 1993-01-19 1998-04-15 Siemens Aktiengesellschaft Process of making a metallization stage comprising contacts and runners which canneet these contacts
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
JPH08335634A (en) * 1995-06-08 1996-12-17 Toshiba Corp Method for manufacturing semiconductor device
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
JPH10223755A (en) * 1997-02-03 1998-08-21 Hitachi Ltd Method for manufacturing semiconductor integrated circuit device
JP3183238B2 (en) * 1997-11-27 2001-07-09 日本電気株式会社 Method for manufacturing semiconductor device
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6387819B1 (en) * 1998-04-29 2002-05-14 Applied Materials, Inc. Method for etching low K dielectric layers
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP3734390B2 (en) * 1998-10-21 2006-01-11 東京応化工業株式会社 Embedding material and wiring forming method using the embedding material
JP2000150644A (en) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp Method for manufacturing semiconductor device
JP4082812B2 (en) * 1998-12-21 2008-04-30 富士通株式会社 Semiconductor device manufacturing method and multilayer wiring structure forming method

Also Published As

Publication number Publication date
JP2003528442A (en) 2003-09-24
AU5790800A (en) 2001-01-31
TW531789B (en) 2003-05-11
IL147301A0 (en) 2002-08-14
JP4675534B2 (en) 2011-04-27
IL147301A (en) 2006-07-05
WO2001001480A1 (en) 2001-01-04
EP1192656A1 (en) 2002-04-03
KR20020020921A (en) 2002-03-16
KR100452418B1 (en) 2004-10-12

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