AU5790800A - Method of protecting an underlying wiring layer during dual damascene processing - Google Patents

Method of protecting an underlying wiring layer during dual damascene processing

Info

Publication number: AU5790800A
Authority: AU; Australia
Prior art keywords: protecting; wiring layer; layer during; dual damascene; damascene processing
Prior art date: 1999-06-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU57908/00A

Inventor

Makarem A. Hussein

Angelo W. Kandas

Alan M Myers

Charles H. Recchia

Sam Sivakumar

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Intel Corp

Original Assignee

Intel Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1999-06-30

Filing date

2000-06-05

Publication date

2001-01-31

1999-06-30 Priority claimed from US09/345,586 external-priority patent/US6406995B1/en

2000-06-05 Application filed by Intel Corp filed Critical Intel Corp

2001-01-31 Publication of AU5790800A publication Critical patent/AU5790800A/en

Status Abandoned legal-status Critical Current

Classifications

- H10W20/085—
- H10W20/01—
- H10W20/077—

AU57908/00A 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing Abandoned AU5790800A (en)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
US09/345,586 US6406995B1 (en)	1998-09-30	1999-06-30	Pattern-sensitive deposition for damascene processing
US09345586		1999-06-30
PCT/US2000/040108 WO2001001480A1 (en)	1999-06-30	2000-06-05	Method of protecting an underlying wiring layer during dual damascene processing

Publications (1)

Publication Number	Publication Date
AU5790800A true AU5790800A (en)	2001-01-31

Family

ID=23355627

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU57908/00A Abandoned AU5790800A (en)	1999-06-30	2000-06-05	Method of protecting an underlying wiring layer during dual damascene processing

Country Status (8)

Country	Link
EP (1)	EP1192656A1 (en)
JP (1)	JP4675534B2 (en)
KR (1)	KR100452418B1 (en)
AU (1)	AU5790800A (en)
HK (1)	HK1042380A1 (en)
IL (2)	IL147301A0 (en)
TW (1)	TW531789B (en)
WO (1)	WO2001001480A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6576550B1 (en)	2000-06-30	2003-06-10	Infineon, Ag	‘Via first’ dual damascene process for copper metallization
WO2002003457A2 (en) *	2000-06-30	2002-01-10	Infineon Technologies Ag	Via first dual damascene process for copper metallization
KR100393974B1 (en) *	2001-01-12	2003-08-06	주식회사 하이닉스반도체	Forming Method for Dual Damascene
KR100419901B1 (en) *	2001-06-05	2004-03-04	삼성전자주식회사	Method of fabricating semiconductor device having dual damascene interconnection
JP2002373936A (en) *	2001-06-14	2002-12-26	Nec Corp	Wiring formation method by dual damascene method
KR100545220B1 (en)	2003-12-31	2006-01-24	동부아남반도체 주식회사	Dual damascene wiring formation method of semiconductor device
JP5096669B2 (en)	2005-07-06	2012-12-12	ルネサスエレクトロニクス株式会社	Manufacturing method of semiconductor integrated circuit device
KR100691105B1 (en) *	2005-09-28	2007-03-09	동부일렉트로닉스 주식회사	Copper wiring formation method using dual damascene process
JP2009016596A (en) *	2007-07-05	2009-01-22	Elpida Memory Inc	Semiconductor device and manufacturing method of semiconductor device
JP4891296B2 (en) *	2008-07-03	2012-03-07	ルネサスエレクトロニクス株式会社	Manufacturing method of semiconductor integrated circuit device
JP5641681B2 (en) *	2008-08-08	2014-12-17	ピーエスフォールクスコエスエイアールエルＰＳ４ＬｕｘｃｏＳ．ａ．ｒ．ｌ．	Manufacturing method of semiconductor device
KR102344900B1 (en) *	2015-04-12	2021-12-28	도쿄엘렉트론가부시키가이샤	Subtractive methods for creating dielectric isolation structures within open features

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0609496B1 (en) *	1993-01-19	1998-04-15	Siemens Aktiengesellschaft	Process of making a metallization stage comprising contacts and runners which canneet these contacts
US5705430A (en) *	1995-06-07	1998-01-06	Advanced Micro Devices, Inc.	Dual damascene with a sacrificial via fill
JPH08335634A (en) *	1995-06-08	1996-12-17	Toshiba Corp	Method for manufacturing semiconductor device
US5702982A (en) *	1996-03-28	1997-12-30	Taiwan Semiconductor Manufacturing Company, Ltd.	Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
JPH10223755A (en) *	1997-02-03	1998-08-21	Hitachi Ltd	Method for manufacturing semiconductor integrated circuit device
JP3183238B2 (en) *	1997-11-27	2001-07-09	日本電気株式会社	Method for manufacturing semiconductor device
US6057239A (en) *	1997-12-17	2000-05-02	Advanced Micro Devices, Inc.	Dual damascene process using sacrificial spin-on materials
US6387819B1 (en) *	1998-04-29	2002-05-14	Applied Materials, Inc.	Method for etching low K dielectric layers
US6245662B1 (en) *	1998-07-23	2001-06-12	Applied Materials, Inc.	Method of producing an interconnect structure for an integrated circuit
JP3734390B2 (en) *	1998-10-21	2006-01-11	東京応化工業株式会社	Embedding material and wiring forming method using the embedding material
JP2000150644A (en) *	1998-11-10	2000-05-30	Mitsubishi Electric Corp	Method for manufacturing semiconductor device
JP4082812B2 (en) *	1998-12-21	2008-04-30	富士通株式会社	Semiconductor device manufacturing method and multilayer wiring structure forming method

2000
- 2000-06-05 IL IL14730100A patent/IL147301A0/en active IP Right Grant
- 2000-06-05 KR KR10-2001-7016608A patent/KR100452418B1/en not_active Expired - Fee Related
- 2000-06-05 WO PCT/US2000/040108 patent/WO2001001480A1/en not_active Ceased
- 2000-06-05 HK HK02104146.3A patent/HK1042380A1/en unknown
- 2000-06-05 AU AU57908/00A patent/AU5790800A/en not_active Abandoned
- 2000-06-05 JP JP2001506606A patent/JP4675534B2/en not_active Expired - Fee Related
- 2000-06-05 EP EP00943434A patent/EP1192656A1/en not_active Ceased
- 2000-08-19 TW TW089112999A patent/TW531789B/en not_active IP Right Cessation
2001
- 2001-12-25 IL IL147301A patent/IL147301A/en not_active IP Right Cessation

Also Published As

Publication number	Publication date
JP4675534B2 (en)	2011-04-27
IL147301A (en)	2006-07-05
JP2003528442A (en)	2003-09-24
HK1042380A1 (en)	2002-08-09
IL147301A0 (en)	2002-08-14
KR20020020921A (en)	2002-03-16
WO2001001480A1 (en)	2001-01-04
EP1192656A1 (en)	2002-04-03
TW531789B (en)	2003-05-11
KR100452418B1 (en)	2004-10-12

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Legal Events

Date	Code	Title	Description
2002-04-18	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase