HK1041975B

HK1041975B - Method and apparatus to control the temperature of a component

Info

Publication number: HK1041975B
Application number: HK02103763.7A
Authority: HK
Inventors: Jain Satchitanand; Reinhardt Dennis; Cho Sung-Soo
Original assignee: 英特尔公司
Priority date: 1998-08-18
Filing date: 1999-08-13
Publication date: 2007-02-23
Also published as: GB0103092D0; CN1263037C; HK1041975A1; GB2358944A; DE19983470T1; GB2358944B; CN1328687A; AU5398199A; DE19983470B4; WO2000011675A1

Abstract

When a component, such as a memory device, exhibits an overtemperature condition (e.g., exceeds a first threshold value), the data transmission rate with respect to the component is reduced so as to lower its operating temperature. In one embodiment, this is achieved by changing the latency at which data packets are transmitted to and from the memory device in dependance on the temperature of the device. Controlling temperature in such a fashion allows for efficient use of the component over a large range of temperatures.

Description

Method and apparatus for controlling temperature of a component

Background

The present invention relates to a method and apparatus for controlling the temperature of a component. More particularly, the present invention relates to a method and apparatus for controlling the temperature of a component by reducing the rate of data transfer to and/or from the component.

Electronic components, such as memory (e.g., Static Random Access Memory (SRAM)), chipsets (e.g., the 82430FX PCI group manufactured by Intel corporation, Santa Clara, california), graphics controllers, and processor processors (e.g., the Pentium II processor manufactured by Intel corporation), are electronic circuits that generate heat during operation. In many cases, the specifications of these components indicate the highest temperature at which the component is operating correctly. If the components exceed this temperature, several problematic conditions may occur. First, the component can compromise the transmitted data signals and or the data signals stored within the component. This leads to errors in other components that rely on such data signals. In addition, excessive heat can cause irreversible damage to individual circuits in the component.

Several program steps have been proposed to control excessive temperature problems in components such as the electronic components described above. In one system, when a component becomes too hot, it is turned off (i.e., powered off) and the user is asked to turn the computer system off and on again (preferably after the computer cools down).

The problems that arise with such systems are: the use of the computer is completely interrupted due to the power-off and power-on of the computer system. There is therefore a need for a method and apparatus that allows control of the thermal temperature in a component without the need for such an in-service interruption.

Summary of The Invention

According to an embodiment of the present invention, an apparatus for controlling the temperature of a component is provided. The apparatus comprises control means adapted to be connected to the component and adapted to control the rate of data transfer between the control means and the component in dependence on the temperature of the component.

Brief Description of Drawings

FIG. 1 is a general block diagram of a system constructed in accordance with an embodiment of the invention.

Fig. 2 is a block diagram of an example of the system of fig. 1.

Figures 3a-b are block diagrams of DRAM memory modules constructed in accordance with embodiments of the present invention.

Fig. 4a-b are flow diagrams of methods according to embodiments of the invention.

Detailed Description

Referring to fig. 1, there is shown a general block diagram of an embodiment in accordance with the invention. A control device is provided which sends data to and/or receives data from the component 12. As used herein, the term "data" should be broadly interpreted to include data, commands, controls, addresses, and other such signals. The component 12 generates heat during its operation, at least partly due to the reception of data from the control device 11. The component 12 may generate a temperature signal and send the signal to a control device. This temperature signal may be, for example, the actual operating temperature, an excess of a predetermined threshold value, etc. In response to the temperature signal from the component 12, the control means 11 reduces the rate at which data is transmitted to the component 12 and/or the rate at which data is received from the component 12.

Referring to FIG. 2, the circuit of FIG. 1 is shown in a computer system environment. In the embodiment of FIG. 2, computer system 20 includes a processor 21 (e.g., a Pentium II processor manufactured by Intel corporation) coupled to a chipset 22 (e.g., 82430FX PCI group manufactured by Intel corporation). In this example, the chipset 22 includes a memory controller hub (hub)22a and an input/output (I/O) controller hub 22 b. These controllers are sometimes referred to in the art as a "north bridge" and a "south bridge," respectively. The memory controller hub 22a may be connected to the I/O controller hub 22b by a bus 23, such as a bus operating in accordance with the Peripheral Component Interconnect (PCI) specification (rev.2.1, PCI special interest group, Hillsboro, Oregon, 1995). If desired, graphics controller 24 may be connected to memory controller hub 22a (e.g., through an advanced graphics port (a.g.p.) interface (see a.g.p. interface specification, revision 1.0, 1996, Intel corporation)). The memory controller hub 22a includes a memory status register 31 which is connected to a memory controller 32. The memory controller is connected to one or more memory devices, such as Dynamic Random Access Memory (DRAM) devices 33a-c (e.g., Rambus' DRAM devices, Rambus corporation, Mountain View, Calif.).

Figures 3a-b show an example of a DRAM device. In fig. 3a, a memory device 33a includes a circuit board 41, such as a Printed Circuit Board (PCB), on which a plurality of memory modules 42a-d are mounted. In the present embodiment, the thermal sensor 43 is fixed on the circuit board 41 (e.g., by a bolt). The thermal sensor 43 includes an output signal line (described below). In fig. 3b, a side view of the memory device 33a of fig. 3a is shown. In this example, compressible, thermally conductive elastomer 45 is pressed against memory modules (e.g., memory modules 42c-d) and thermal sensors 43 with heat spreader plate 46 a. Heat dissipation plates 46a-b are made of a suitable thermally conductive material and are connected by pins (e.g., pins 42 c-d). In operation, thermal sensor 43 is capable of detecting heat generated by a memory module connected to circuit board 41 through elastomer 45 and heat spreader plates 46 a-b.

In this example, thermal sensor 43 senses the temperature of the memory module in memory module 33 a. For example, the thermal sensor 43 may include a well-known thermistor (i.e., an analog device having a resistance that changes in proportion to ambient temperature) and an analog-to-digital converter that converts an analog voltage value across the thermistor to a digital value (not specifically shown in FIG. 2). The digital value is then compared to a threshold value (i.e., a value representing the desired maximum operating temperature) and a pulse signal is generated on signal line 44 indicating that the threshold value has been exceeded. It may be desirable to set the threshold below the maximum operating temperature set forth in its specification.

In the embodiment of FIG. 2, signal line 44 from sensor 43 is connected to a general purpose I/O (GPIO) pin on IO controller hub 22 b. Alternatively, the thermal sensor on the additional memory module 33b-c may have a signal line (elements 50-51) connected to this GPIO pin. In this case, the signal lines 44, 50 and 51 are used as inputs to an or gate 55. Thus, when an over-temperature condition occurs on one or more of the memory modules 33a-c (e.g., the temperature exceeds a first threshold value), an appropriate signal is generated by its corresponding sensor (e.g., sensor 43) and transmitted through the OR gate to the GPIO pin of the I/O controller hub 22 b. In this example, the over-temperature signal at the I/O controller hub 22b causes an interrupt to be generated to the processor 21. Examples of suitable interrupts include System Management Interrupts (SMIs) present in all Intel Pentium and Pentium II processors, and System Control Interrupts (SCIs) (see Intel corporation et al, "advanced configuration and Power interface Specification," draft revision 1.0, Dec.22, 1996). In response, the processor 21 notifies the memory controller hub 22a of the over-temperature condition. In the example of fig. 2, this is done by writing (or logging) the appropriate value into the memory status register 31.

The memory controller 32 in the memory controller hub 22a controls the transfer (e.g., writing and reading) of data from and/or to the DRAM devices 33 a-c. In this embodiment, data is transmitted and received in accordance with a packet protocol. Each packet is transmitted according to a latency value (e.g., the amount of delay time for transmitting the packet to and/or from DRAM devices 33a-c after the packet is ready). For example, during normal operation, when DRAM devices 33a-c do not exhibit an over-temperature condition, the latency value should be low, preferably zero. The memory controller 32 periodically checks the contents of the memory status register 31. When the register 31 indicates an over-temperature condition in the DRAM devices 33a-c, the memory controller 32 increases the latency value in order to slow down the data transfer between the memory controller hub 22a and the DRAMs 33 a-c. The reduction in data traffic flow to/from the DRAMs 33a-c may result in a reduction in the operating temperature of these devices. Thus, the DRAMs 33a-c continue to operate (albeit at a slower data throughput) despite the over-temperature condition, rather than turning off completely. When the data transfer rate is reduced, the transfer of data to/from other devices (e.g., the graphics controller 24) to/from the DRAMs 33a-c may be slowed accordingly.

When the temperature on DRAMs 33a-c falls below a predetermined second threshold value, another signal (e.g., from sensor 43) is sent to the GPIO pin of I/O controller hub 22b (via OR gate 55) indicating that these devices are operating at a sufficiently low temperature to allow for an increase in the data transfer rate to memory controller hub 22 a. When the I/O controller hub 22a receives such a signal, it causes a second interrupt to be applied to the processor 21. In response, processor 21 places the appropriate value into memory status register 31 (e.g., resets the value stored therein). The new value in register 31 causes memory controller 32 to reduce the latency value (e.g., to zero) and increase the data transfer rate between memory controller hub 22a and DRAM 33 a.

In the embodiments of the present invention described above, DRAM devices 33a-c continue to operate at the appropriate rate. However, it is possible that interrupts between the I/O controller hub 22b and the processor 21 will be blocked. For example, a set of code (technically referred to as a virus) executed by the processor 21 may disable these interrupts. Other units may be added to prevent DRAM devices 33a-c from exceeding the maximum rated temperature, according to another embodiment of the present invention. The I/O controller hub may include a counter that starts counting when the GPIO pin receives a signal. When the counter 60 expires after a predetermined time interval, it is determined whether the IO controller center 22b generates an interrupt. If it is not generated, an appropriate message is sent from the I/O controller hub 22b to the memory controller hub 22a over the bus 23 or a dedicated bus 61 between these components. In response, the memory controller hub 22a sets the appropriate value in the memory status register 31, as indicated in the above-described embodiment. When the temperature falls below the second threshold, the resulting signal on the GPIO pin may be used to immediately generate an appropriate message to memory controller hub 22a, or a counter may be used to allow IO controller hub 22b the opportunity to generate an interrupt. For the above example, the message received by memory controller hub 22a causes the memory status register to be reset, thus increasing the data rate to/from DRAM devices 33 a-c.

A method according to an embodiment of the invention is shown in fig. 4a-4 b. At block 101, the system is initialized, assuming that all components are operating at an acceptable temperature. Thus, the data transfer rate to/from the component 12 (see fig. 1) is normal (e.g., at full rate). At decision block 103, a determination is made whether a component (e.g., component 12 of FIG. 1, or a memory of FIG. 2, such as DRAM memories 33a-c) exhibits an over-temperature condition. If no over-temperature has occurred, conditional control returns to decision block 103. Otherwise, control passes to block 105 (FIG. 4b), where a counter may optionally be started. At block 107 (FIG. 4a), an interrupt is generated (e.g., by the I/O controller hub 22b of FIG. 2). At block 109, an over-temperature condition is logged (e.g., the appropriate data is written to the memory status register 31 of FIG. 2). At decision block 110 (fig. 4b), it is checked whether the counter has expired. If so, control passes to decision block 111 to determine whether an interrupt was generated (e.g., at block 107). If not, the over-temperature condition is logged in a direct manner (e.g., via direct communication between the I/O controller hub 22b and the memory controller hub 22a of FIG. 2).

At block 113 (fig. 4a), the data transfer rate is decreased so as to reduce the operating temperature of the component 12 (fig. 1). At decision block 115, a determination is made whether the operating temperature has dropped below a second threshold. At decision block 117, a determination is made as to whether an interrupt was previously generated (e.g., in response to the over-temperature condition of block 107). If so, control passes to block 118 (FIG. 4 b). Where a new interrupt is generated and then an insufficient temperature condition is logged (e.g., the appropriate data is written to the memory status register 31 of fig. 2; see block 119). If no interrupt has been previously generated, control proceeds directly to block 119 to log in the insufficient temperature condition in a direct manner as described above. At block 121, the data rate is increased to improve performance.

In the examples of fig. 1-4, first and second temperature thresholds are used. When the component exceeds a first temperature threshold, the data rate is reduced to a predetermined rate. When the temperature drops below the second temperature threshold, the data rate is increased to its original value. Those skilled in the art will appreciate that the methods and apparatus shown in fig. 1-4 may be modified to handle additional intermediate threshold values. For example, when the temperature exceeds a first (and highest) threshold temperature value, the data transmission rate is reduced to a first (and lowest) value. If the temperature is below the first threshold but exceeds an intermediate threshold temperature (i.e., a temperature between the first and second threshold temperatures), the data rate may be set to a value that is intermediate between the original (full rate) value and the lowest value. Thus, by using this feature of the invention, the data transfer rate can be better optimized according to the operating temperature of the component.

While embodiments have been particularly shown and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. For example, although individual components are shown in FIGS. 1 and 2, many of the components may be separated into separate components or integrated into larger components. In addition, the present invention can be applied to components other than the memory device. However, when the memory device is used, the data transfer rate between the control device and the memory device can be reduced by reducing the number of write operations or read operations per unit time (instead of the number of both operations in the same time).

Claims

1. An apparatus for controlling a temperature of an electronic component selected from a memory, a chipset, a graphics controller, and a processor, the apparatus comprising:

a control device adapted to be connected to the electronic component, wherein the control device is adapted to control a data transfer rate between the control device and the electronic component depending on the temperature of the electronic component, wherein the data transfer rate comprises a transfer of data to be stored in the electronic component and/or a transfer of data stored in the electronic component to the control device.

2. The apparatus of claim 1 wherein said control means decreases said data transmission rate when a temperature of said electronic component exceeds a first threshold.

3. The apparatus of claim 2 wherein said electronic component is a memory device comprised of electronic circuitry.

4. The apparatus of claim 3, wherein said control means is a memory controller hub.

5. The apparatus of claim 4 wherein said memory controller hub includes a memory controller, said memory controller adapted to transmit data packets to said electronic circuit storage device at a latency value, said latency value being increased when a temperature of said electronic circuit storage device exceeds said first threshold value.

6. The apparatus of claim 5, wherein said latency value is decreased when the temperature of said memory device comprised of electronic circuitry decreases below a second threshold value.

7. An apparatus for controlling the temperature of a memory device comprised of electronic circuitry, comprising:

a memory device comprised of electronic circuitry, comprising:

at least one memory module;

a temperature sensor connected to the memory module;

a circuit board, wherein the memory module and the temperature sensor are connected to the circuit board; and

a thermally conductive elastomer connected to the memory module and the temperature sensor, an

A control device connected to said storage device comprised of electronic circuitry, said control device being adapted to control a data transfer rate between said control device and said storage device comprised of electronic circuitry in dependence on a temperature of said storage device comprised of electronic circuitry, wherein said data transfer rate comprises a transfer of data to be stored in said storage device comprised of electronic circuitry and/or a transfer of data stored in said storage device comprised of electronic circuitry to said control device.

8. The apparatus of claim 7, wherein said control means decreases said data transfer rate when a temperature of said storage means comprised of electronic circuitry exceeds a first threshold.

9. The apparatus of claim 8, wherein said control means is a memory controller hub.

10. The apparatus of claim 9 wherein said memory controller hub includes a memory controller, said memory controller adapted to transmit data packets to said electronic circuit comprising memory devices at a latency value, said latency value being increased when a temperature of said electronic circuit comprising memory devices exceeds a first threshold value.

11. The apparatus of claim 10, wherein said latency value is decreased when the temperature of said memory device comprised of electronic circuitry decreases below a second threshold value.

12. A method of controlling the temperature of an electronic component, the electronic component selected from a memory, a chipset, a graphics controller, and a processor, the method comprising:

controlling a data transfer rate between a control device and the electronic component as a function of the temperature of the electronic component, wherein the data transfer rate comprises a transfer of data to be stored in the electronic component and/or a transfer of data stored in the electronic component to the control device.