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GB914348A - Shift register - Google Patents

Shift register

Info

Publication number
GB914348A
GB914348A GB3642359A GB3642359A GB914348A GB 914348 A GB914348 A GB 914348A GB 3642359 A GB3642359 A GB 3642359A GB 3642359 A GB3642359 A GB 3642359A GB 914348 A GB914348 A GB 914348A
Authority
GB
United Kingdom
Prior art keywords
pulse
core
windings
capacitor
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3642359A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US528594A external-priority patent/US2907987A/en
Priority claimed from US548581A external-priority patent/US2919354A/en
Priority claimed from US625826A external-priority patent/US2904779A/en
Priority claimed from US757482A external-priority patent/US3163771A/en
Priority claimed from US769838A external-priority patent/US3077585A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB914348A publication Critical patent/GB914348A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/383Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/04Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using cores with one aperture or magnetic loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Electronic Switches (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Control Of Stepping Motors (AREA)
  • Discharge By Other Means (AREA)
  • Dc Digital Transmission (AREA)

Abstract

914,348. Stepping registers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 27, 1959 [Oct. 27, 1958], No. 36423/59. Class 40 (9). A stepping register has storage cores S1 S2, &c., and intermediate cores K1, K2, &c., each storage core being linked to the preceding and succeeding intermediate cores by a circuit including a series capacitor. As shown in Fig. 2, shift pulses from sources A and B in antiphase, as shown in Fig. 5, drive alternate pairs of cores K1, S1 ; K2, S2; &c., or K2, S1; K3, S2 ; &c., depending on switch 34 which determines whether the register steps left or right. A reset pulse source R drives the cores K1, K2, &c. Current entering a winding at the dot terminal tends to switch a core to " 0." For the switch position shown, and with all cores at " 0 " except S1 which is at " 1," an A drive pulse switches S1 to " 0 " producing a clockwise current in windings 10, 12, and 14, which cannot disturb core K1 as it is subject to the A pulse, but switches K2 to " 1." Shift of flux in K2 produces an anticlockwise current in windings 16, 18 and 20 while charging capacitor C2. As the current in this loop starts to decrease capacitor C2 discharges and this discharge is accelerated by an R pulse which restores core K2 to " 0," the consequent clockwise current in winding 20 switching core S2 to " 1." Clockwise current in the windings 10, 12, 14 as K2 is set to " 0 " is opposed by capacitor C1 which was charged when S1 was switched. When C1 discharges it provides an anti-clockwise current which does not affect cores S1 K1, or K2, as they already occupy " 0 " states. An A pulse, therefor, steps " 1 " from S1 to S2. A subsequent B pulse will similarly step the " 1 " in S2 to S3, and so forth. By throwing switch 34, reversely connected drive windings are used to step the register backwards in the same fashion, it being necessary for the windings 12 and 14, 16 and 18, &c., to have equal turns. The reset source R is dispensed with in the register shown in Fig. 6 where, for the step right connection of the sources A and B capacitor C1 is charged by clockwise current in windings 10, 12, 14, when S1 is switched to " 0 " by an A pulse and C2 is charged by anti-clockwise current in windings 16, 18, 20, as core K2 is switched to " 1." Due to loss over core K2 capacitor C2 is charged less than C1 so that when both capacitors discharge at the end of the A pulse current from C1 has a predominant effect on core K2 and switches it back to " 0." The discharge of capacitor C2 switches core S2 to " 1 " but does not switch core K3 as discharge takes place before the end of the A pulse which holds K3 at " 0." The " 1 " in core S1 is therefore stepped to S2 by an A pulse; a B pulse will similarly step the " 1 " in S2 to S3, and so forth. As shown in Fig. 7, a forward stepping register is constructed to avoid separate drive windings, drive being applied to the windings 12, 14, 22, 24, and 16, 18, 28, 60, &c., from drive sources A and B respectively. Supposing that core S1 occupies the only " 1 " state an A pulse switches S1 to " 0 " and charges capacitor C1 with a current which switches core K2 to " 1." When K2 switches, current flows in windings 16, 18, 20 to charge C2. When S1 is fully switched, winding 10 has low impedance and capacitor C1 discharges, switching K2 back to "0." Capacitor C2 also discharges to switch S2 to " 1 " and also tends to hold K2 in the " 1 " state, but as there is loss in charging C2 over K2, C1 predominates. Core K3 is unaffected by discharge of C2 as it is subject to the A pulse. A B pulse similarly shifts the " 1 " from S2 to S3. Specification 814,619 is referred to.
GB3642359A 1955-08-16 1959-10-27 Shift register Expired GB914348A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US528594A US2907987A (en) 1955-08-16 1955-08-16 Magnetic core transfer circuit
US548581A US2919354A (en) 1955-11-23 1955-11-23 Magnetic core logical circuit
US625826A US2904779A (en) 1956-12-03 1956-12-03 Magnetic core transfer circuit
US757482A US3163771A (en) 1958-08-27 1958-08-27 Logical transfer circuit
US769838A US3077585A (en) 1958-10-27 1958-10-27 Shift register

Publications (1)

Publication Number Publication Date
GB914348A true GB914348A (en) 1963-01-02

Family

ID=27541848

Family Applications (4)

Application Number Title Priority Date Filing Date
GB2466256A Expired GB841619A (en) 1955-08-16 1956-08-13 Improvements in magnetic core shift registers
GB3550156A Expired GB843496A (en) 1955-08-16 1956-11-20 Improvements in magnetic core switching networks
GB1791959A Expired GB881378A (en) 1955-08-16 1959-05-26 Improvements in logical switching devices
GB3642359A Expired GB914348A (en) 1955-08-16 1959-10-27 Shift register

Family Applications Before (3)

Application Number Title Priority Date Filing Date
GB2466256A Expired GB841619A (en) 1955-08-16 1956-08-13 Improvements in magnetic core shift registers
GB3550156A Expired GB843496A (en) 1955-08-16 1956-11-20 Improvements in magnetic core switching networks
GB1791959A Expired GB881378A (en) 1955-08-16 1959-05-26 Improvements in logical switching devices

Country Status (4)

Country Link
DE (5) DE1142452B (en)
FR (3) FR1172001A (en)
GB (4) GB841619A (en)
NL (2) NL109283C (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB706736A (en) * 1952-01-03 1954-04-07 British Tabulating Mach Co Ltd Improvements in or relating to electrical storage devices
US2781503A (en) * 1953-04-29 1957-02-12 American Mach & Foundry Magnetic memory circuits employing biased magnetic binary cores
US2784390A (en) * 1953-11-27 1957-03-05 Rca Corp Static magnetic memory
NL206689A (en) 1955-04-28
AT196644B (en) * 1955-08-16 1958-03-25 Ibm Circuit for forwarding information stored in a magnetic core

Also Published As

Publication number Publication date
DE1166256B (en) 1964-03-26
GB841619A (en) 1960-07-20
NL209697A (en)
GB843496A (en) 1960-08-04
FR1172057A (en) 1959-02-05
FR1194463A (en) 1959-11-10
DE1161311B (en) 1964-01-16
DE1160891B (en) 1964-01-09
FR1172001A (en) 1959-02-04
DE1155169B (en) 1963-10-03
DE1142452B (en) 1963-01-17
NL109283C (en)
GB881378A (en) 1961-11-01

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