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GB2530962A - Method and system for implementing a bit array in a cache line - Google Patents

Method and system for implementing a bit array in a cache line Download PDF

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Publication number
GB2530962A
GB2530962A GB1601479.7A GB201601479A GB2530962A GB 2530962 A GB2530962 A GB 2530962A GB 201601479 A GB201601479 A GB 201601479A GB 2530962 A GB2530962 A GB 2530962A
Authority
GB
United Kingdom
Prior art keywords
bit array
cache line
request
implementing
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB1601479.7A
Other versions
GB2530962B (en
GB201601479D0 (en
Inventor
Burkhard Steinmacher-Burow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB201601479D0 publication Critical patent/GB201601479D0/en
Publication of GB2530962A publication Critical patent/GB2530962A/en
Application granted granted Critical
Publication of GB2530962B publication Critical patent/GB2530962B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Stored Programmes (AREA)
  • Logic Circuits (AREA)

Abstract

The present invention relates to a method for implementing a bit array (318) in a cache line (211) of a memory system (128) that includes a memory storage (208) and a controller (206), the method comprising configuring in the cache line (211) the bit array (318), the bit array comprising array of bits, wherein the configuring further comprises defining a value of each bit in the bit array, receiving, by the controller (206), a request (210) for an operation on the bit array wherein the request is indicative of a location of the cache line (211) in the memory storage (208) and information specifying the request; identifying,by the controller (206),for the operation one or more actions on the bit array (318) using the information, wherein the one or more actions are encoded in the controller (206); and in response to receiving the request, performing the request by executing the one or more encoded actions.
GB1601479.7A 2013-07-11 2014-07-01 Method and system for implementing a bit array in a cache line Active GB2530962B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1312446.6A GB2516092A (en) 2013-07-11 2013-07-11 Method and system for implementing a bit array in a cache line
PCT/IB2014/062757 WO2015004571A1 (en) 2013-07-11 2014-07-01 Method and system for implementing a bit array in a cache line

Publications (3)

Publication Number Publication Date
GB201601479D0 GB201601479D0 (en) 2016-03-09
GB2530962A true GB2530962A (en) 2016-04-06
GB2530962B GB2530962B (en) 2020-04-22

Family

ID=49081142

Family Applications (2)

Application Number Title Priority Date Filing Date
GB1312446.6A Withdrawn GB2516092A (en) 2013-07-11 2013-07-11 Method and system for implementing a bit array in a cache line
GB1601479.7A Active GB2530962B (en) 2013-07-11 2014-07-01 Method and system for implementing a bit array in a cache line

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB1312446.6A Withdrawn GB2516092A (en) 2013-07-11 2013-07-11 Method and system for implementing a bit array in a cache line

Country Status (5)

Country Link
JP (1) JP6333371B2 (en)
CN (1) CN105378686B (en)
DE (1) DE112014003212T5 (en)
GB (2) GB2516092A (en)
WO (1) WO2015004571A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6458163B2 (en) 2015-03-26 2019-01-23 スパイレーション インコーポレイテッド ディー ビー エイ オリンパス レスピラトリー アメリカ Biopsy sample retention mechanism
EP3665580B1 (en) * 2017-08-08 2023-03-08 Continental Automotive Technologies GmbH Method of operating a cache

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003030051A (en) * 2001-07-19 2003-01-31 Sony Corp Data processing device and data access method
US20030088737A1 (en) * 2001-11-05 2003-05-08 Lee Burton Bandwidth enhancement for uncached devices
WO2011023679A1 (en) * 2009-08-31 2011-03-03 International Business Machines Corporation Transactional memory system with efficient cache support
US20110219215A1 (en) * 2010-01-15 2011-09-08 International Business Machines Corporation Atomicity: a multi-pronged approach
US20120185672A1 (en) * 2011-01-18 2012-07-19 International Business Machines Corporation Local-only synchronizing operations

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03172947A (en) * 1989-11-13 1991-07-26 Matra Design Semiconductor Inc Microcomputer system
WO2001063240A2 (en) * 2000-02-25 2001-08-30 Sun Microsystems, Inc. Maintaining high snoop traffic throughput and preventing cache data eviction during an atomic operation
US7127559B2 (en) * 2001-07-10 2006-10-24 Micron Technology, Inc. Caching of dynamic arrays
EP2159702B1 (en) * 2007-06-20 2013-04-17 Fujitsu Limited Cache control device and control method
CN100478918C (en) * 2007-10-31 2009-04-15 中国人民解放军国防科学技术大学 Segmental high speed cache design method in microprocessor and segmental high speed cache
US8296524B2 (en) * 2009-06-26 2012-10-23 Oracle America, Inc. Supporting efficient spin-locks and other types of synchronization in a cache-coherent multiprocessor system
US8543769B2 (en) * 2009-07-27 2013-09-24 International Business Machines Corporation Fine grained cache allocation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003030051A (en) * 2001-07-19 2003-01-31 Sony Corp Data processing device and data access method
US20030088737A1 (en) * 2001-11-05 2003-05-08 Lee Burton Bandwidth enhancement for uncached devices
WO2011023679A1 (en) * 2009-08-31 2011-03-03 International Business Machines Corporation Transactional memory system with efficient cache support
US20110219215A1 (en) * 2010-01-15 2011-09-08 International Business Machines Corporation Atomicity: a multi-pronged approach
US20120185672A1 (en) * 2011-01-18 2012-07-19 International Business Machines Corporation Local-only synchronizing operations

Also Published As

Publication number Publication date
GB2516092A (en) 2015-01-14
DE112014003212T5 (en) 2016-04-28
JP2016526739A (en) 2016-09-05
CN105378686A (en) 2016-03-02
JP6333371B2 (en) 2018-05-30
WO2015004571A1 (en) 2015-01-15
CN105378686B (en) 2018-05-29
GB2530962B (en) 2020-04-22
GB201601479D0 (en) 2016-03-09
GB201312446D0 (en) 2013-08-28

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Effective date: 20200608