GB2509545A - Photo detector comprising SPAD cell array - Google Patents

Abstract

A photo-detector comprising an array of SPAD (Single Photon Avalanche Diode) cells (50, 50'), wherein each SPAD cell includes a SPAD circuit (2, figure 1) and a readout circuit (4, figure 1) that has an output node (26, figure 1) and is configured to deliver an electrical current to the output node when the SPAD circuit is activated by a photon. The output nodes 26,26' of a plurality of the SPAD cells 50, 50' are connected to at least one common output line 56 whereby the currents delivered to the output nodes of the activated SPAD cells are added together (aggregated) to provide an output current Iout. The magnitude of the output current represents the activation rate of the SPAD cells. The SPAD circuit may be connected to the readout circuit through a buffer device (16 figure 1). The readout circuit may include a constant current device (20 figure 1) and a switch such as a MOS transistor (Ms figure 1) configured to control delivery of constant current to the output node 26. The switch may also be configured as a differential switch comprising for example source coupled MOS transistors (18, 18 figure 3) and a constant current source (20 figure 3). The photo detector may include a quench circuit (8 figure 1) to reset the SPAD or APD (avalanche photo diode) (6 figure 1). The readout circuit may also include sample and hold circuitry and a timing device (figure 9).

Description

Photo-detector The present invention relates to a photo-detector and in particular to a photo-detector that comprises an array of single photon avalanche diodes (SPADs).

There are various type of photo-detectors PDs) used in systems that need to detect light.

The simplest PDs are photo-diodes. These devices are easily fabricated and have the ability to be integrated with other peripheral electronics. For high speed applications such as optical communications one of the most common peripheral circuits used in conjunction with a photodiode is a transimpedance amplifier ITIA). The function of this circuit is to convert the output current from the photodiode into a voltage whilst also minimising the change in the voltage applied to the photodiode.

A problem with using a TIA is that when the photocurrent flowing in the photodetector is small the lowest detectable signal is determined by the noise within the TIA. The effect of this noise can be reduced by reducing the bandwidth of the TIA, however, this reduces the bandwidth of the photodetector. In applications for which sensitivity is critical it is important to use the largest possible detector to generate the largest possible photocurrent.

Although optical elements such as concentrators can be used to increase the collection area of the sensor, they limit the field of view of the photo-detector. This means that they give limited benefit in some applications and even when they are used the sensitivity of the overall system will be improved by using larger photodetectors. Unfortunately, larger photodiodes have a arger capacitance and so a lower RC bandwidth.

A popular approach to increasing the signal gain without increasing the area of the photodetector is to use a photodiode that is specifically designed so that it can be operated at a high reverse bias voltage. It is then possible to create a high electric field within the photodiode. if the field is high enough then each detected photon can create a large number of electrons and holes via a physical process known as avalanche multiplication. This process creates signal gain within the photodiode. These more sensitive detectors are known as Avalanche Photo-diodes (APDs). The internal gain within an APD increases when the reverse bias voltage of the APD increases and in particular it increases very rapidly as the applied voltage approaches the voltage at which the avalanche process becomes self-sustaining.

Unfortunately there are several disadvantages with using APDs: (i) There are statistical fluctuations in the amount of charge generated by each detected photon via the avalanche process. This means that the APD is nosier than a conventional photodiode.

(ii) Many APDs require bias voltages well in excess of normal operating voltages available within consumer equipment.

(iii) High gains are only achieved when the bias voltage is close to the breakdown voltage. In this bias range the gain of the APD is very sensitive to changes in the bias voltage and operating temperature. Ideally the bias voltage applied to the APD should therefore be well controlled at a value that depends upon the operating temperature of the APD.

(iv) Large area and ow capacitance APDs have to be manufactured on specific fabncation processes. Even then as the size of the APD increases, maintaining the uniformity of the electrical field is challenging, which leads to lower production yield and higher cost per device.

(v) The widely available CMOS process is not suitable for APDs as the reverse bias region in which avalanche gain occurs is too narrow, which makes these devices particularly sensitive to changes in the bias voltage and temperature. The resulting inability to integrate APDs with other components increases the power consumption, cost and size of systems.

Many of the problems associated with APDs can be avoided if the photodiode is biased so that the avalanche process becomes self-sustaining. These devices can then be converted to single photon detectors by placing the photodiode in series with another device so that the current which flows in response to an avalanche process automatically reduces the voltage across the photodiode to stop or quench the avalanche process. After a period the voltage across the photodetector is reset to its initial value ready for the detection of the next photon. When used in this mode the detector is known as a single photon avalanche diode (SPAD) and the penod when the voltage is too low to sustain avalanching is referred to as the deadtirne.

The output of the SPAD is a digital-like pulse which indicates an avalanche event. Hence, unlike photodiodes and APDs, the SPAD is a photon counting detector in which the intensity of the illumination is proportional to the event rate. Unfike APDs, SPADs are not sensitive to their bias voltage, excess noise, and temperature variation as the avalanche current is regarded as binary current. However the maximum size of a SPAD is limited by the fact that it can only detect single photons in a predetermined period and if a photon is absorbed within the device during its deadtime it will be missed. Increasing the size of the photodiode within the SPAD will also increase the background dark count rate.

In order to increase the collection area of the photodetector, an array on asynchronous SPADs can be used. Each SPAD operates independently and has its own quenching circuit.

The overall photon count from the array is an aggregation of the counts from the individual SPADs. One possible approach to detecting the events in the SPADs is to connect each SPAD separatdy to an external circuit. However, this can cause signal integrity problems and there is always a limit on the maximum number of connections that are available. This approach is therefore only practical for relatively small numbers of SPADs.

To overcome the signal integrity problem and the limited number of available connections, a single counter can be integrated onto the same substrate as the SPAD array. Events from each individual SPAD can trigger an asynchronous counter. The count within a known period can then be read from the counter. However, if two events are too close the second event may be missed, resulting in a miscount of the number of events. This leads to distorted event counting, especially in high event rates.

To avoid event clashing a cefl-levd counter can be used. The counter within each cell can then count and store the number of events in a particular SPAD. These counts can then be read later and added to an overall sum by a single accumulator. To operate quickly this type of system requires a high speed global clock and the cell level counter reduces the fraction of the available area that can be used to detect photons. Furthermore, like the other architectures the output of the system is a digital signal. which can create signal integrity problems at high speed.

US 2011/0235771 Al describes a CMOS readout architecture and method for photon-counting arrays. having a photon-counting detector, a digital counter and an overflow bit in each sensing element of the array.

It is also known to provide an analogue readout circuit for an SPAD array. "Compact readout circuits for SPAD arrays" (Danial Chitnis and Steve Collins: Proceedings of 2010 WEE International Symposium on Circuits and Systems (ISCAS), May 30 -June 2 2010; Page(s): 357 -360) describes a compact readout circuit that can be integrated between individual SPADs, which integrates charge onto a capacitor to represent the number of detected photons. One problem with this mechanism is that the capacitor must be reset periodically and so for some applications, including communications, it is then necessary to synchronise the SPAD array with another process.

It is an object of the invention to provide a photo-detector array that mitigates one or more of the aforesaid problems.

According to one aspect of the invention there is provided a photo-detector comprising an array of SPAD cells, wherein each SPAD cell includes a SPAD circuit and a readout circuit that has an output node and is configured to deliver an electrical current to the output node when the SPAD circuit is activated by a photon, wherein the output nodes of a plurality of the SPAD cells are connected to at least one common output line, whereby the culTents delivered to the output nodes of the activated SPAD cells are aggregated in the common output line to provide an output current, wherein the magnitude of the output current represents the activation rate of the SPAD cells.

hi the present invention, the activation rate of the SPAD cells is represented by the magnitude of the output current. The output current therefore represents in analogue form the intensity of light falling on the photodetector. The advantage of this arrangement over previous digital SPAD-based photodetectors is that it avoids the need for one or more digital counters that count individual activation events in each of the activated SPAD cells.

Instead, the rate of activation and hence the intensity of the light can be determined simply by adding together the output currents of the individual SPAD cells, which can be done by connecting each of the output lines to a common output line. This greatly simplifies the design of the photodetector array and allows a greater number and/or larger photodiodes to be provided within an available sampling area.

The output nodes of the SPAD cells are preferaNy connected to a single common output line. However, they may alternatively be connected to a plurality of common output lines.

which are preferably interconnected.

Advantageously, the SPAD circuit is connected to the readout circuit through a buffer device. The buffer device may consist for example of a simple inverter (or a pair of series-linked inverters) having an output that switches between high and low values when the voltage at the output node of the SPAD cell drops below the threshold voltage of the inverter. The inverter thus provides a voltage pulse at its output each time the SPAD cell is activated, which controls the output current of the readout circuit.

Advantageously, the readout circuit includes a constant current device and a switch device that is configured to control the delivery of current from the constant current device to the output node in response to activation of the SPAD circuit. Advantageously, the constant current source comprises a current limited transistor having a gate node configured to receive a control voltage for controlling the current delivered by the transistor. This allows a user of the photodetector to control the output current of the readout circuit to provide a readout signal (for example, a readout voltage) that is above the noise level of the readout circuit. This ensures that each avalanche event is counted and photon counting is maintained. The constant current source may for example comprise a PMOS transistor.

The switch device may also comprise a transistor, for example a PMOS transistor.

Advantageously, the readout circuit includes a differential output mechanism comprising first and second switch devices that are configured to steer current from the constant current device alternately to one or both of first and second output nodes in response to activation of the SPAD circuit. Activation of the SPAD cell can then be represented by the difference in the currents in the first and second output nodes. This arrangement reduces current fluctuations in the power supply rails. For example, current may be steered to the second output node only when the SPAD circuit is inactive and to both the first and second output nodes when the SPAD circuit is activated. In a preferred arrangement. the output node of the SPAD cell is connected to the gate node of the first switch device and a bias voltage is supphed to the gate node of the second switch device. The bias voltage may be adjusted to minimise current fluctuations in the power supply rails. The first and second switch devices may comprise transistor switches, for example PMOS transistors.

Alternatively, the readout circuit may include a differential output mechanism comprising first and second switch devices that are configured to steer current from the constant current device alternately to first and second output nodes in response to activation of the SPAD circuit. For example, current may be steered to the second output node only when the SPAD circuit is inactive and to the first output node only when the SPAD circuit is activated. Activation of the SPAD cell can then be represented by the difference in the currents in the first and second output nodes. This arrangement further reduces current fluctuations in the power supply rails. Advantageously, the readout circuit includes a switch driver device that is configured to control switching of the first and switch devices.

The first and second switch devices may comprise transistor switches, for example PMOS transistors.

Advantageously, the first output nodes of a plurality of the SPAD cells are connected to a first common output line, and the second output nodes of a plurality of the SPAD cells are connected to a second conirnon output line, wherein the differential current in the two output lines represents the activation rate of the SPAD cells. The activation rate of SPAD cells in the array can then be represented by the difference in the currents in the first and second output lines.

Advantageously, the SPAD circuit includes an APD and a quench and reset device that is configured to quench and reset the APD after it has been activated. The quench and reset device may for example consist of a current Umited transistor, for example a PMOS transistor. The gate node of the transistor may be connected to receive a gate voltage, which may be adjusted to control the speed of recovery of the APD during the reset phase, after the APD has been activated.

Alternatively, the quench and reset device may include a hold switch, a reset switch and a timing device that is configured to activate the hold switch after the SPAD cell has been activated so as to quench the APD, and then to activate the reset switch so as to reset the APD. The timing device ensures that the avalanche process is completely quenched before the APD is reset. This arrangement enables the quenching and resetting operations to be entirely independent of each other, allowing shorter reset times to be achieved. The hold and reset switches may comprise transistor switches, for example PMOS transistors.

Alternatively, the quench and reset device may include a reset switch and a timing device that is configured to sense activation of the SPAD cell, and to activate the reset switch so as to reset the APD only after a predetermined delay. The quench and reset device may for example include a delayed inverter in series with a conventional inverter, connected between the output node of the APD and the gate node of a reset transistor switch, for example a PMOS transistor. This arrangement is simpler than the arrangement that uses a timing circuit and separate hold and reset switches, but achieves a similar result.

According to one preferred embodiment, the present invention solves the problems with the previous systems by employing a method that has been used with high speed digital to analogue converters (DACs). In a particular embodiment a current steeling DAC with equally-weighed unit elements, is formed from an array of' cells' which each contain a current source and a pair of differential switches that steer the current from the current source to one of two output connections. The currents from the cells are summed by sharing these outputs between cells and the resulting currents can be converted to voltages using either resistors or TIAs. Due to the fast switching capability of the CMOS transistors.

these DACs have high operation speeds and the use of two switches and outputs minimises signa' integrity problems.

In an embodiment, the photodetector comprises an array of SPADs, wherein the basic building block of the array comprises a SPAD cell that contains an APD, a quenching circuit and a current steering cell. The APD is connected in series with the quenching circuit, whose function is to quench the self-sustained avalanche process to create a SPAD.

The output of the SPAD is connected to differential switches in the current steering circuit, which steer the culTent to one of two outputs for a predetermined time when an avalanche event occurs. All the equivalent outputs from each building block are connected in parallel which keeps the ayout simple and easy to scale. The output of the array is a differential current which is proportional to the number of SPADs in which events have recently occurred. The individual culTent sources can be designed andlor biased to adjust the current flowing through individual current sources. This effectively means that unlike the APD the gain of the system is controlled by the system designer and/or user. This flexibility can be used to ensure that the signal generated by a single photon is larger than the noise generated in the rest of the system. This ensures that each individual event is detected, and the photon counting behaviour of the detector is maintained. Due to the design of the current read-out mechanism, such a detector is compatible with the conventional read-out mechanism of PD and APDs. Due to the simple layout of summing currents, the array can be scaled up to large number of SPAD cells. In general, this mechanism reduces complexity by minimising the size of the cell, thereby adding scalability while maintaining high speed operation.

Certain embodiments of the invention will now be described by way of example with reference to the accompanying drawings, wherein: Fig 1 is a circuit diagram of a basic SPAD cell, comprising a first embodiment of the invention; Fig 2 is a circuit diagram of a SPAD cell with a differential output, comprising a second embodiment of the invention; Fig 3 is a circuit diagram of a SPAD cell with a high performance current steering read-out, comprising a third embodiment of the invention; Fig 4 is a timing diagram that illustrates the role of switch driver in signalling in the circuit of Fig 3; Fig 5 is a circuit diagram of a SPAD cell with an automatic diode reset and current steering readout, comprising a fourth embodiment of the invention; Fig 6 is a circuit diagram of a minimal timing and control circuit for a SPAD cell.

comprising a fifth embodiment of the invention; Fig 7 is a more detailed circuit diagram of a delayed inverter circuit comprising part of the timing and control circuit of Fig 6; Fig 8 is a circuit diagram of an array of basic SPAD circuits of the type shown in Fig I with a shared current output; Fig 9 is a schematic block diagram of a SPAD cell; Fig 10 is a schematic diagram of the physical layout of a SPAD cell showing the relative size of the different parts of the cell; Fig 11 is an oscilloscope trace showing the differential voltage at the output resistors of a SPAD cell; Fig i2 is an oscilloscope trace showing the accumulated traces of voltage output; and Fig 13 is an oscilloscope trace showing the output of a SPAD cell when illuminated with a pulsed light source, wherein the top oscilloscope trace is the eye diagram' and the bottom trace is the clock signal required to create the eye diagram'.

Option #1: The SPAD cell shown in Fig. I consists of two major parts: a SPAD circuit 2 and a readout circuit 4. The SPAD circuit 2 includes an avalanche photodiode (APD) 6 and a diode biasing circuit, which ensures that the avalanche photodiode (or "diode") 6 is appropriately biased, quenched, and reset. The readout circuit 4 enables a non-destructive readout of the diode's response. In the SPAD cell shown in Fig. I the cathode of the diode 6 is connected through a culTent limited quench and reset transistor MQR 8 to a positive diode biasing voltage supply node P05 10, and the anode of the diode 6 is connected to a negative diode biasing voltage supply node NEG 12. The gate of the quench and reset transistor MQR 8 is connected to a gate node 14. k use, the quench and reset transistor MQR 8 limits the amount of charge that can flow through the diode 6 during an avalanche event.

The readout circuit 4 comprises a buffer 16 that has an input connected to the cathode of the diode 6. The output of the buffer 16 is connected to the gate of a transistor switch M5 18 to control the flow of current from a current source transistor M5 20 to an output node 26. The current source transistor Mcs 20 is located between the transistor switch 18 and a voltage source YDU 24, the gate of the current source transistor M5 20 being connected to agatenode22.

When it is in its idle mode the photodiode 6 is biased over its breakdown voltage and the diode's capacitance is charged to the bias voltage. Then, when an avalanche event occurs.

the internal avalanche current discharges the diode's capacitance and the voltage across the SPAD drops to its breakdown voltage. Hence, the avalanche current is quenched. As soon as the avalanche current is quenched, the diode's capacitance is recharged to its initial voltage by the quench and reset transistor MQR 8. The current limiting quench and reset transistor 8 has a role of both quenching and resetting the diode 6. Its gate voltage determines the speed of recovery during reset phase.

The diode 6 is biased such that its breakdown voltage is between ground level and the threshold voltage of the buffer 16 connected to the diode's cathode. The voltage swing during the quench and reset phase is then made large enough to trigger the voltage buffer 16, which is connected the diode's cathode. When the diode 6 is quenched. the voltage at the cathode of the diode 6 drops below the threshold voltage of the buffer 16. If for example the buffer 16 consists of two inverters connected in senes, then this will lead to a digital low signal at the buffer output. As a result, transistor switch M conducts a current that is limited by the gate bias voltage of M5.

A circuit somewhat similar to that shown in Figure 1 has been used in imaging and biosensing applications. In the circuits designed for these applications the current output node 26 was connected to a capacitor, which integrated the current over a specific period of time. A reset transistor was added to recharge the capacitor. In the imaging implementation a pixel-level capacitor was used, and in the biosensing application a global capacitor was used. The number of avalanche events was proportional to the amount of charge stored in the capacitor or capacitors associated with the SPADs. One problem with this mechanism is that the capacitors must be reset periodically and so for some applications, including communications, it is then necessary to synchronise the SPAD array with another process.

To avoid the need for synchronisation, the output node 26 may be connected to a resistor 27 that converts the output current into an output voltage, which can be measured to provide a readout signal. Alternatively, the output node 26 could be connected to a transimpedance amplifier. The amount of current can be controlled by the voltage applied to the gate node 22 of the current source transistor 20. The gate voltage of the transistor 20 that provides the current source is chosen so that the transistor 20 operates in its saturation region: hence, the generated current is independent of the output voltage.

This bias voltage is also selected such that the converted output voltage is above the noise level of the read-out system. This ensures that each avalanche event is detectable, and the photon counting operation is maintained. When designing a circuit to be incorporated into -Il-an array of SPADs it is also important to ensure that the gate bias voltage used to bias the transistor is large enough so that variations between the output currents from different cells are negligible for the target application.

Option #2: Although the circuit in Option #i is suitable for applications such as imaging and sensing, it is not optimal for high speed performance. In particular, as each curent source transistor M5 20 is connected to the output 26 the amount of current flowing into the circuit fluctuates. This constant switching action causes a signal integrity problem on the power supply rails. In order to provide a constant culTent load on the power supply rails, a differential output mechanism may be used. In the circuit shown in Fig. 2 a second transistor switch Ms2 18' is provided in paralël with the first transistor switch Ms1 18 to sink to a second current output node 26' part or all of the cunent provided by the current source transistor M5 20. lii other respects, the circuit shown in Fig. 2 is similar to the first circuit shown in Fig. 1, as described above.

When an avalanche event occurs, transistor switch M51 conducts, and the current of the current supply transistor M5 is shared between the first and second transistor switches M51 and M52. Between avalanche events the current of the current supply transistor M5 flows exclusively through the second transistor switch M52. The current thus flows continuously through either one or both of the output nodes 26, 26'. By selecting an appropriate bias voltage for the gate of the second transistor switch M52, current fluctuations on the power supply rails are minimised.

Option #3: In high speed applications, the impedance of the switches and the asymmetry of the switching signals cause signal integrity problems. Differential current steering switches are widely used in high speed digital-to-analogue converters. These switches are made of a matched pair of transistors, hence providing similar switching transient characteristics. A complementary differential signal drives these switches providing a complementary switching operation, and current steering mechanism. The complementary current steering action minimises the glitch which occurs during high speed switching operations. A switch driver unit provides the symmetrical complementary switching signals required for the switches. In addition, it provides constant switch impedance by adjusting the amplitude of the switching signals that drive the switching transistors. As a result, high impedance nodes during the switching action are avoided.

Fig. 3 is a schematic diagram of a SPAD cell with a current steering readout mechanism. In other respects, the circuit shown in Fig. 3 is similar to the second circuit shown in Fig. 2, as described above.

The output of the buffer 16 is connected to a switch driver unit 30, which creates a differential pair of signals to drive the cunent steering switches M51 and M52. When an avalanche event occurs, the current is steered from the negative output node 26' to the positive output node 26. The differential current output is usually terminated by a pair of passive resistors (not shown), which convert the current into a voltage. The generated differential voltage provides a better signal integrity and noise immunity in any following circuits.

Fig. 4 shows the signalling operation of the switch driver unit 30. The input voltage to the switch driver unit 30 is a single ended output from the buffer. In order to avoid a high impedance node, the amplitude of the signal which drives the switching transistor is limited to a lower voltage. This ensures that the transistor is never fully turned off As a result, the output current swings between a minimum and a maximum current, which is determined by the switch driver unit 30.

During idle mode, when the cathode of the diode 6 is above the threshold level of the voltage buffer 16, less current flows through the first transistor switch Msi than through the second transistor switch M52. Hence, most of the current flowing through current supply transistor Ms flows through the negative output 26'. When an avabnche event occurs, the voltage on the diode's cathode drops below the threshold voltage of the buffer 16. This voltage drop changes the state of the switch driver unit 30 causing more current to flow through the first transistor switch Ms1 than through the second transistor switch Ms2.

As a result, the culTent is steered from the negative output 26' to the positive output 26.

During the recovery, once the diode's voltage passes the threshold voltage of the buffer 16, the state of the switch driver unit 30 changes and the current is steered baclc from the positive output 26 to the negative output 26'.

Option #4: In order to improve the performance of the SPAD cell, an automatic diode reset circuit may be implemented instead of the basic quenching and reset mechanism. In the basic method as shown in Fig. I the quench and reset transistor MQR provides means of both quenching and resetting the photo-diode 6. This means that the quenching and resetting processes are dependent on each other. If shorter reset times are required, the current of the quenching and reset transistor MQR should be increased. As a consequence, due to the higher current, the diode 6 may never quench. The use of an automatic diode reset circuit ensures that both quenching and resetting operations are independent of each other, allowing short reset times to be achieved.

Fig. 5 shows a SPAD cell with automatic diode reset and current steering readout. In other respects, the circuit shown in Fig. 5 is similar to the third circuit shown in Fig. 3, as descnbed above. The automatic reset circuit 32 includes two major components: hold and reset switches MR 34, M11 36 and a timing control circuit 38. The switches 34. 36 are connected to the cathode of the diode 6. The diode 6 is biased such that its breakdown voltage is between ground level and the threshold voltage of the buffer 16 connected to the diode's cathode.

In the idle mode the diode capacitance is charged by the bias voltage, and both the switches 34, 36 are non-conductive. Similar to the basic quenching mechanism, once an avalanche event occurs, the voltage across the diode 6 drops to its breakdown voltage, leading to quenching of the avalanche process. This voltage drop triggers the timing control circuit 38, which starts a timer (not shown) within the timing control circuit 38 for a specified period. This timer sends a signal back to the h&d switch MH 34, turning the hold switch M11 to conductive mode, and maintaining the bias voltage of the diode 6 at the ground level during this period, which ensures that diode's bias voltage is below its breakdown voltage to quench the avalanche process. This duration is referred to as deadtime as the diode 6 is inactive.

Once the deadtime has elapsed, the hold transistor MN becomes non-conducting, and a second sub-nanosecond timer (not shown) within the timing control circuit 38 sends a signal back to the reset transistor MR to charge the diode 6 to its initial bias voltage. Once the sub-nanosecond pulse has elapsed, the reset transistor MR becomes non-conducting and the SPAD cell is ready for detection of the next avalanche event.

Similar to Option #3, during the idle mode the current flows through the negative output 26'. When an avalanche event occurs the current is steered from the negative output 26' to the positive output 26. Once the deadtime has elapsed the current is steered back from the positive output 26 to the negative output 26'. During the deadtime the current flows through the positive output 26 as the voltage of the diode node is close to ground levd dunng the deadtime.

Figure 6 shows a minimal timing and control circuit for operating the avalanche diode 6 in the SPAD mode. This circuit includes the avalanche diode 6. a pMOS transistor MR 42 for resetting the circuit, a delayed digital inverter 44, a conventional digital inverter 46 and an output node 48, which is connected to the readout circuit (not shown). The delayed inverter 44 is similar to a conventional digital inverter except that its output has a delay relative to its input.

In idle mode, the capacitance of the diode 6 is fully charged, and the voltage at the output node 48, which is connected to the readout circuit, is VDD. The output of delayed inverter 44 is Low, and the gate voltage of the reset transistor MR is High, hence the reset transistor is not conducting.

Once an avalanche event occurs, the diode 6 is rapidly discharged to its breakdown voltage by the avalanche current. The negative supply voltage at terminal NEC is set to ensure that the breakdown voltage is sufficiently below the threshold voltage of the delayed inverter 44. As a result, the output of the delayed inverter 44 changes state from Low to High.

However this change occurs after a specified delay, which is in the range of nanoseconds.

The second inverter 46 has a negligible delay, hence, the gate voltage of the reset transistor MR changes from High to Low. As a result, the reset transistor MR becomes conducting and the capacitance of the diode 6 is recharged by the current provided by MR. Therefore the avalanche diode 6 is reset, and it is ready for detection of the next avalanche event.

Figure 7 shows an implementation of the delayed inverter circuit 44, which is based on current starved inverters. A current starved inverter charges the capacitance at its output node by a relatively lower current than a conventional inverter. As a result, the state of the output changes more slowly than in a conventional inverter. The first stage II of the delayed inverter circuit 44 shown in Figure 7 is a current starved inverter which has a slow rise and a fast fall at its output node. When the input falls from High to Low, transistor M2 is conducting and transistor M3 is not conducting. The capacitance C at the output node of inverter 11 is charged by transistors Ml and M2. The rate of charge is controlled by the gate voltage yR of the current limited transistor Ml. The inverter 12 sharpens the output pulse of inverter 11. The inverter 13, which is also a current starved inverter and comprises transistors M4, MS and M6, operates similarly to inverter Ii, however it has a fast rise and a stow fall. The rate of the fall in inverter 13 is controlled by the gate voltage of the current limited transistor M6. The inverters 14 and IS sharpen the output pulse. As a result, inverter Il creates a delay during a fall at the input of the delayed inverter circuit, and inverter 13 creates a delay during a rise at the input of the circuit.

Figure 8 illustrates an array of basic SPAD cells, wherein each SPAD cell 50, 50' etc. is of the type shown in Fig. 1 as described above. The gate of each quench and reset transistor MQR is connected to a quench and reset control line 52 to receive a quench and reset control signal VQR and the gate of each current supply transistor Mcs is connected to a current supply control line 52 to receive a current supply control signal Vçs. The output node 26 of each transistor switch M5 is connected via a common output line 56 to a common output node 58. The individual output currents of the SPAD cells 50, 50' etc. are therefore summed at the common output node 58. The total output curretu comprising the sum of the individual output culTent from each of the SPAD cells can be converted to a voltage by connecting the output node 58 to a resistor 27. This voltage can be measured to provide an analogue output signal or it can be converted to a digital signal using an analogue to digital converter (not shown). Alternatively, the total output current can be measured by connecting the output node 58 to a transimpedance amplifier TIA (not shown).

It should be understood that the alternative SPAD cells shown in Figs. 2, 3 and 5 to 7 may each be assembled into an array similar to that depicted in Fig. 8 but with the modifications depicted in Figs. 2, 3 and 5 to 7. In each case, operation of the individual SPAD cells will be substantially as described above, and the array as a whole will operate substantially as described in relation to Fig. 8 but with any necessary modifications required according to the type of SPAD cell used.

A SPAD array based on automatic diode reset and current steering readout has been designed and implemented in a commercial CMOS process. Fig. 9 is a schematic block diagram of a SPAD cell that has been implemented for use in such an array. The SPAD cell 60 contains three major blocks: the avalanche photodiode (APD) 6, a diode biasing circuit 62 and the readout circuit 64. The diode biasing circuit 62 is based on automatic diode reset mechanism shown in Fig. 5 and described above, which includes a hold and reset unit 66 and a timing and control unit 68. The bias voltage and the deadtime of the SPAD cell 60 can be controlled by off-chip externai bias voliages 70, 72. The readout circuit 64 of the SPAD cell 60 is based on the differential current steering output circuit shown in Fig. 5 and descnbed above, and includes first and second current switch transistors 18. i8', current source transistor 20, switch driver unit 30 and positive and negative output nodes 26, 26'. The gate voltage of the current source transistor 20 is controlled by an external bias voltage 74. This effectivdy determines the output gain of the SPAD array. These bias voltages 70, 72, 74 are all shared among the cells within the array.

Fig. 10 shows the implemented layout of a SPAD cell circuit 76. The photodiode 6 in this circuit 76 has a circular shape to maintain a uniform electrical field and avoid high electrical fields in sharp corners. The fabricated diode has a 30 jim diameter including its surrounding guard nngs 78. The diameter of the diode's active area 80, in which the photons are absorbed, is 10 tm. The automatic reset circuit 82 and the differential converter 84 are located close to the photo diode 6. The culTent steering switches and current source are located within the circuit area. As this implementation is a functional prototype, the circuit and layout sizes could be further optimised. In the photodiode 6, the ratio of the guard ring 78 to active area 80 could be improved by sharing some of the doping layers. The automatic reset circuit 82 and analogue read-out switches 84 could be redesigned to be more area efficient.

The fabricated prototype array has been tested for its basic functionality. the deadtime has been increased to the maximum possible which is in a range of milliseconds. This ensures that most of the cells within the array are sourcing current to the positive' output. The bias voltage of the current source transistor M5 ensures that it is operating in saturation region.

The current outputs are terminated with a 300 ohm resistor (not shown). The diode 6 is biased IV over its breakdown voltage. Fig. ii shows both differential outputs. As the deadtime is very long in comparison the avalanche event rate. aimost all the 64 cells within the array are sourcing current to the positive' output. However, occasionally some of the cells recover and the number of cells sourcing current drops below 64. As shown in Fig. II, this causes quantised fluctuations of the output voltage.

Fig. 12 shows accumulated oscilloscope traces for both differential outputs. This figure shows that the output voltage is quantised into equal steps which are of the same size in the both complementary outputs.

Fig. 13 shows the output when the illuminating light is modulated by a 20 Mbps pseudo-random on-off keying signal. The resulting eye diagram' clearly shows that the signal to noise ratio of this output signal is large enough for it to be demodulated.

Claims (11)

1. CLAIMS1. A photo-detector comprising an array of SPAD cells, wherein each SPAD cell includes a SPAD circuit and a readout circuit that has an output node and is configured to deliver an electrical current to the output node when the SPAD circuit is activated by a photon. wherein the output nodes of a plurality of the SPAD cells are connected to at least one common output line, whereby the currents delivered to the output nodes of the activated SPAD cells are aggregated to provide an output current wherein the magnitude of the output current represents the activation rate of the SPAD cells.
2. 2. A photo-detector according to claim 1, wherein the SPAD circuit is connected to the readout circuit through a buffer device.
3. 3. A photo-detector according to claim 1 or 2, wherein the readout circuit includes a constant current device and a switch device that is configured to control the delivery of current from the constant current device to the output node in response to activation of the SPAD circuit.
4. 4. A photo-detector according to claim 3, wherein the constant cunent source comprises a current limited transistor having a gate node configured to receive a control voltage for controlling the current delivered by the transistor.
5. 5. A photo-detector according to claim 3 or claim 4. wherein the readout circuit hicludes a differential output mechanism comprising first and second switch devices that are configured to steer current from the constant culTent device alternately to one or both of first and second output nodes in response to activation of the SPAD circuit.
6. 6. A photo-detector according to claim 3 or claim 4. wherein the readout circuit indudes a differential output mechanism comprising first and second switch devices that are configured to steer current from the constant current device alternately to first and second output nodes in response to activation of the SPAD circuit.
7. 7. A photo-detector according to claim 6, wherein the readout circuit includes a switch driver device that is configured to control switching of the switch devices.
8. 8. A photo-detector according to any one of claims 5 to 7, wherein the first output nodes of a plurality of the SPAD cells are connected to a first common output line, and the second output nodes of a plurality of the SPAD cells are connected to a second common output line, and wherein the differential current in the two output lines represents the activation rate of the SPAD cells.
9. 9. A photo-detector according to any one of the preceding claims, wherein the SPAD circuit includes an APD and a quench and reset device that is configured to quench and reset the APD after it has been activated.
10. 1 0. A photo-detector according to claim 9, wherein the quench and reset device includes a hold switch, a reset switch and a timing device that is configured to activate the hold switch after the SPAD cell has been activated so as to quench the APD, and then to activate the reset switch so as to reset the APD.
11. 11. A photo-detector according to claim 9, wherein the quench and reset device includes a reset switch and a timing device that is configured to sense activation of the SPAD cell, and to activate the reset switch so as to reset the APD only after a predetermined delay.