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GB2422488A - An advanced technique for forming transistors having raised drain and source regions with different height - Google Patents

An advanced technique for forming transistors having raised drain and source regions with different height Download PDF

Info

Publication number
GB2422488A
GB2422488A GB0607742A GB0607742A GB2422488A GB 2422488 A GB2422488 A GB 2422488A GB 0607742 A GB0607742 A GB 0607742A GB 0607742 A GB0607742 A GB 0607742A GB 2422488 A GB2422488 A GB 2422488A
Authority
GB
United Kingdom
Prior art keywords
regions
different height
source regions
epitaxial growth
raised drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0607742A
Other versions
GB2422488B (en
GB0607742D0 (en
Inventor
Ralf Van Bentum
Scott Luning
Thorsten Kammler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10351008A external-priority patent/DE10351008B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0607742D0 publication Critical patent/GB0607742D0/en
Publication of GB2422488A publication Critical patent/GB2422488A/en
Application granted granted Critical
Publication of GB2422488B publication Critical patent/GB2422488B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H01L21/823418—
    • H01L21/823814—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Abstract

The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Description

GB 2422488 A continuation (72) Inventor(s): Ralt Van Bentum Scott Luning
Thorsten Kammier (74) Agent and/or Address for Service: Brookes Batchellor LLP 102-1 08 Clerkenwell Road, LONDON, EC1M 55A, United Kingdom
GB0607742A 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height Expired - Fee Related GB2422488B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10351008A DE10351008B4 (en) 2003-10-31 2003-10-31 A method of fabricating transistors having elevated drain and source regions of different height and a semiconductor device
US10/862,518 US7176110B2 (en) 2003-10-31 2004-06-07 Technique for forming transistors having raised drain and source regions with different heights
PCT/US2004/031038 WO2005045924A1 (en) 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height

Publications (3)

Publication Number Publication Date
GB0607742D0 GB0607742D0 (en) 2006-05-31
GB2422488A true GB2422488A (en) 2006-07-26
GB2422488B GB2422488B (en) 2008-02-13

Family

ID=34575412

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0607742A Expired - Fee Related GB2422488B (en) 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height

Country Status (4)

Country Link
JP (1) JP2007528123A (en)
KR (1) KR101130331B1 (en)
GB (1) GB2422488B (en)
WO (1) WO2005045924A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
DE102005030583B4 (en) * 2005-06-30 2010-09-30 Advanced Micro Devices, Inc., Sunnyvale Method for producing contact insulation layers and silicide regions having different properties of a semiconductor device and semiconductor device
KR20230164472A (en) 2022-05-25 2023-12-04 삼성전자주식회사 Integrated circuit device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
US20020005553A1 (en) * 2000-07-06 2002-01-17 Fumio Ootsuka Semiconductor integrated circuit device and a method of manufacturing the same
US20020008261A1 (en) * 2000-03-06 2002-01-24 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
US20020106855A1 (en) * 2001-02-06 2002-08-08 Hidenori Sato Method of manufacturing semiconductor device
US20020158292A1 (en) * 2000-07-27 2002-10-31 Mitsubishi Denki Kabushiki Kaisha Method of making field effect transistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US616582A (en) * 1898-12-27 Victor odqtjist and john c
US690636A (en) * 1900-12-19 1902-01-07 Joseph Coldwell Warp stop-motion for looms.
JP2964925B2 (en) * 1994-10-12 1999-10-18 日本電気株式会社 Method of manufacturing complementary MIS type FET
JP2000124327A (en) * 1998-10-14 2000-04-28 Toshiba Corp Semiconductor device and manufacturing method thereof
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
US20020008261A1 (en) * 2000-03-06 2002-01-24 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
US20020005553A1 (en) * 2000-07-06 2002-01-17 Fumio Ootsuka Semiconductor integrated circuit device and a method of manufacturing the same
US20020158292A1 (en) * 2000-07-27 2002-10-31 Mitsubishi Denki Kabushiki Kaisha Method of making field effect transistor
US20020106855A1 (en) * 2001-02-06 2002-08-08 Hidenori Sato Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
GB2422488B (en) 2008-02-13
KR101130331B1 (en) 2012-03-27
GB0607742D0 (en) 2006-05-31
JP2007528123A (en) 2007-10-04
KR20060108641A (en) 2006-10-18
WO2005045924A1 (en) 2005-05-19

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20091210 AND 20091216

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20110917