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GB2398903A - Improving integrated circuit performance and reliability using a patterned bump layout on a power grid - Google Patents

Improving integrated circuit performance and reliability using a patterned bump layout on a power grid Download PDF

Info

Publication number
GB2398903A
GB2398903A GB0410834A GB0410834A GB2398903A GB 2398903 A GB2398903 A GB 2398903A GB 0410834 A GB0410834 A GB 0410834A GB 0410834 A GB0410834 A GB 0410834A GB 2398903 A GB2398903 A GB 2398903A
Authority
GB
United Kingdom
Prior art keywords
bump
integrated circuit
reliability
power grid
circuit performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0410834A
Other versions
GB0410834D0 (en
Inventor
Sudhakar Bobba
Tyler J Thorp
Dean Liu
Pradeep R Trivedi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/997,452 external-priority patent/US6577002B1/en
Priority claimed from US09/997,844 external-priority patent/US6617699B2/en
Priority claimed from US09/997,437 external-priority patent/US6473883B1/en
Priority claimed from US09/997,523 external-priority patent/US6541873B1/en
Priority claimed from US09/997,438 external-priority patent/US6762505B2/en
Priority claimed from US09/997,471 external-priority patent/US6495926B1/en
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of GB0410834D0 publication Critical patent/GB0410834D0/en
Publication of GB2398903A publication Critical patent/GB2398903A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H10W72/00—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H10W20/427—
    • H10W20/43—
    • H10W72/012—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H10W72/20—
    • H10W72/248—
    • H10W72/251—

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A method for improving integrated circuit by using a patterned bump layout on a metal layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

Description

GB 2398903 A continuation (72) Inventor(s): Sudhakar Bobba Tyler J Thorp
Dean Liu Pradeep R Trivedi (74) Agent and/or Address for Service: W P Thompson & Co Drury Lane, LONDON, WC2B 5SQ, United Kingdom
GB0410834A 2001-11-29 2004-05-14 Improving integrated circuit performance and reliability using a patterned bump layout on a power grid Withdrawn GB2398903A (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US09/997,452 US6577002B1 (en) 2001-11-29 2001-11-29 180 degree bump placement layout for an integrated circuit power grid
US09/997,844 US6617699B2 (en) 2001-11-29 2001-11-29 120 degree bump placement layout for an integrated circuit power grid
US09/997,437 US6473883B1 (en) 2001-11-29 2001-11-29 Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid
US09/997,523 US6541873B1 (en) 2001-11-29 2001-11-29 90 degree bump placement layout for an integrated circuit power grid
US09/997,438 US6762505B2 (en) 2001-11-29 2001-11-29 150 degree bump placement layout for an integrated circuit power grid
US09/997,471 US6495926B1 (en) 2001-11-29 2001-11-29 60 degree bump placement layout for an integrated circuit power grid
PCT/US2002/037643 WO2003048981A2 (en) 2001-11-29 2002-11-25 Improving integrated circuit performance and reliability using a patterned bump layout on a power grid

Publications (2)

Publication Number Publication Date
GB0410834D0 GB0410834D0 (en) 2004-06-16
GB2398903A true GB2398903A (en) 2004-09-01

Family

ID=27560358

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0410834A Withdrawn GB2398903A (en) 2001-11-29 2004-05-14 Improving integrated circuit performance and reliability using a patterned bump layout on a power grid

Country Status (4)

Country Link
JP (1) JP2005512315A (en)
AU (1) AU2002352885A1 (en)
GB (1) GB2398903A (en)
WO (1) WO2003048981A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6961247B2 (en) * 2002-06-27 2005-11-01 Sun Microsystems, Inc. Power grid and bump pattern with reduced inductance and resistance
US7335536B2 (en) * 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801966A (en) * 1995-07-24 1998-09-01 Cognex Corporation Machine vision methods and articles of manufacture for determination of convex hull and convex hull angle
WO1999041784A1 (en) * 1998-02-12 1999-08-19 Rose Research, L.L.C. Method and apparatus for coupling circuit components
US20010010408A1 (en) * 1999-03-19 2001-08-02 Ming-Dou Ker Low-capacitance bonding pad for semiconductor device
US20010013663A1 (en) * 1997-12-12 2001-08-16 Gregory F. Taylor Integrated circuit device having c4 and wire bond connections
US6323559B1 (en) * 1998-06-23 2001-11-27 Lsi Logic Corporation Hexagonal arrangements of bump pads in flip-chip integrated circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801966A (en) * 1995-07-24 1998-09-01 Cognex Corporation Machine vision methods and articles of manufacture for determination of convex hull and convex hull angle
US20010013663A1 (en) * 1997-12-12 2001-08-16 Gregory F. Taylor Integrated circuit device having c4 and wire bond connections
WO1999041784A1 (en) * 1998-02-12 1999-08-19 Rose Research, L.L.C. Method and apparatus for coupling circuit components
US6323559B1 (en) * 1998-06-23 2001-11-27 Lsi Logic Corporation Hexagonal arrangements of bump pads in flip-chip integrated circuits
US20010010408A1 (en) * 1999-03-19 2001-08-02 Ming-Dou Ker Low-capacitance bonding pad for semiconductor device

Also Published As

Publication number Publication date
WO2003048981A3 (en) 2004-06-24
AU2002352885A1 (en) 2003-06-17
GB0410834D0 (en) 2004-06-16
JP2005512315A (en) 2005-04-28
WO2003048981A2 (en) 2003-06-12

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)