GB2388691B - Memory control chip control method and control circuit - Google Patents

Memory control chip control method and control circuit

Info

Publication number: GB2388691B
Authority: GB; United Kingdom
Prior art keywords: control; memory; chip; circuit; control circuit
Prior art date: 2002-03-27
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

GB0300026A

Other versions

GB0300026D0 (en

GB2388691A (en

Inventor

Nai-Shung Chang

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Via Technologies Inc

Original Assignee

Via Technologies Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2002-03-27

Filing date

2003-01-02

Publication date

2004-03-31

2003-01-02 Application filed by Via Technologies Inc filed Critical Via Technologies Inc

2003-02-05 Publication of GB0300026D0 publication Critical patent/GB0300026D0/en

2003-11-19 Publication of GB2388691A publication Critical patent/GB2388691A/en

2004-03-31 Application granted granted Critical

2004-03-31 Publication of GB2388691B publication Critical patent/GB2388691B/en

2023-01-02 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals

GB0300026A 2002-03-27 2003-01-02 Memory control chip control method and control circuit Expired - Lifetime GB2388691B (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US36866402P	2002-03-27	2002-03-27

Publications (3)

Publication Number	Publication Date
GB0300026D0 GB0300026D0 (en)	2003-02-05
GB2388691A GB2388691A (en)	2003-11-19
GB2388691B true GB2388691B (en)	2004-03-31

Family

ID=23452211

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
GB0300026A Expired - Lifetime GB2388691B (en)	2002-03-27	2003-01-02	Memory control chip control method and control circuit

Country Status (4)

Country	Link
CN (2)	CN1228783C (en)
DE (1)	DE10260996B4 (en)
GB (1)	GB2388691B (en)
TW (1)	TW559809B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7356434B2 (en) *	2005-05-12	2008-04-08	Taiwan Semiconductor Manufacturing Co., Ltd.	Method of specifying pin states for a memory chip
EP2140232A2 (en)	2007-04-26	2010-01-06	Heraeus Sensor Technology Gmbh	Sheet resistor in an exhaust pipe
US7778093B2 (en) *	2007-08-08	2010-08-17	Mediatek Inc.	Memory control circuit capable of dynamically adjusting deglitch windows, and related method
CN102193891B (en) *	2010-03-03	2013-11-27	纬创资通股份有限公司	Timing adjustment module, second-line transmission system and timing adjustment method
US9665505B2 (en) *	2014-11-14	2017-05-30	Cavium, Inc.	Managing buffered communication between sockets
US9779813B2 (en) *	2015-09-11	2017-10-03	Macronix International Co., Ltd.	Phase change memory array architecture achieving high write/read speed
CN106559630B (en) *	2015-09-30	2019-10-01	中强光电股份有限公司	Projection device and data access control module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5787047A (en) *	1993-09-17	1998-07-28	Cypress Semiconductor Corp.	Memory architecture for burst mode access
US6034878A (en) *	1996-12-16	2000-03-07	Hitachi, Ltd.	Source-clock-synchronized memory system and memory unit
US20020125927A1 (en) *	2001-03-09	2002-09-12	Joseph Hofstra	Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6446158B1 (en) *	1999-05-17	2002-09-03	Chris Karabatsos	Memory system using FET switches to select memory banks
KR20010036202A (en) *	1999-10-06	2001-05-07	박종섭	Memory module for protecting voltage noise

2002
- 2002-05-24 TW TW91111026A patent/TW559809B/en not_active IP Right Cessation
- 2002-06-13 CN CN 02123231 patent/CN1228783C/en not_active Expired - Lifetime
- 2002-06-13 CN CN02238705U patent/CN2585371Y/en not_active Expired - Fee Related
- 2002-12-24 DE DE2002160996 patent/DE10260996B4/en not_active Expired - Lifetime
2003
- 2003-01-02 GB GB0300026A patent/GB2388691B/en not_active Expired - Lifetime

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5787047A (en) *	1993-09-17	1998-07-28	Cypress Semiconductor Corp.	Memory architecture for burst mode access
US6034878A (en) *	1996-12-16	2000-03-07	Hitachi, Ltd.	Source-clock-synchronized memory system and memory unit
US20020125927A1 (en) *	2001-03-09	2002-09-12	Joseph Hofstra	Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KR2001036202A and WPI abstract accession number 2002-008441 [01] *

Also Published As

Publication number	Publication date
GB0300026D0 (en)	2003-02-05
GB2388691A (en)	2003-11-19
DE10260996B4 (en)	2008-08-21
CN1399277A (en)	2003-02-26
CN1228783C (en)	2005-11-23
DE10260996A1 (en)	2003-10-23
TW559809B (en)	2003-11-01
CN2585371Y (en)	2003-11-05

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Legal Events

Date	Code	Title	Description
2023-01-25	PE20	Patent expired after termination of 20 years	Expiry date: 20230101