CN1228783C - Memory control chip, control method and control circuit - Google Patents

Abstract

A memory control chip comprises a plurality of groups of data signal pins, each group of data signal pins can be correspondingly connected to one group of data signal pins of each memory module, and a plurality of time pulse generating pins are used for outputting corresponding time pulse signals to time pulse input pins of each memory module. That is, a plurality of memory modules, which are the same memory bank , originally referenced to the same time pulse may instead be referenced to different time pulses having a predetermined phase difference, that is, the memory modules in the same memory bank may be accessed with different time pulses. Therefore, the amount of data that is varied simultaneously is reduced, i.e., the simultaneous switching noise is reduced, so that fewer power/ground pins can be arranged to reduce the manufacturing cost.

Description

Memory control chip, control method and control circuit

technical field

The invention relates to a memory circuit, and in particular to a memory control chip, a control method and a control circuit.

Background technique

Today's general personal computer (referred to as PC) system is mainly composed of a motherboard, an interface card, and peripheral devices, etc., and the motherboard can be said to be the heart of the computer system. On the motherboard, in addition to the central processing unit (Central Processing Unit, referred to as CPU), memory control chip, and slots for installing interface cards, there are also multiple memory module slots (Memory Module) for installing memory modules. module slot), which can install different numbers of memory modules (Memory module) according to the needs of users.

Generally, the memories used in personal computers include synchronous dynamic random access memory (Synchronous dynamic random access memory, referred to as SDRAM), and double data rate dynamic random access memory (Double data rate dynamic random access memory, referred to as DDR DRAM). ). Among them, SDRAM refers to the rising edge or falling edge of the system clock pulse to perform data access operations, while DDR DRAM performs data access operations referring to the rising or falling edges of the system clock pulse, so as to double the The data transfer rate at the system clock pulse frequency.

The DDR DRAM memory module currently on the market uses a 184-pin memory module socket that conforms to the JEDEC standard. The data signal pins provided by it are 64-bit wide, which is exactly in line with the 64-bit wide bus of the memory control chip. Therefore, each memory module can be defined as a memory bank, and each memory control chip can access 64-bit wide data. In order to increase the addressing space of the memory and preserve the flexibility of memory expansion, there are usually memory module slots of different numbers in the motherboard, which are used to respectively insert memory modules, and different memory module slots can represent different memory groups ( Memorybank) memory module.

Please refer to FIG. 1 , which shows a conventional memory control circuit. The circuit includes: a memory control chip 110 , a clock buffer 140 , a first memory module 120 and a second memory module 130 . The memory modules of the first memory module 120 and the second memory module 130 belonging to two different storage groups are inserted into memory module slots (not shown) to achieve data access with the memory control chip 110 . In addition, since the data signal pin (DATA) of the memory control chip 110 is 64 bits wide, and the data signal pins SD1 and SD2 of the first memory module 120 and the second memory module 130 are also 64 bits wide, so the memory control The chip 110 can use the 64-bit wide data bus 115 to access data in each memory module respectively. As shown in the figure, the timing pulse generating pin (DCLKO) of the memory control chip 110 is connected to the timing pulse input terminal (CKI) of the timing pulse buffer 140 to enhance the driving capability of the timing pulse signal, and then the timing pulse buffer 140’s clock output terminal (CKO1) to output a clock signal to simultaneously drive the first memory module 120 and the second memory module 130 (the clock signal output by the clock buffer 140 can be used to drive up to 4 groups of memory modules) . Therefore, the timing pulse signal can be sent to the first memory module 120 and the second memory module 130 as a reference timing pulse signal during data access. The clock pulse feedback output terminal ( CKO2 ) of the clock pulse buffer 140 transmits the clock pulse signal back to the clock pulse feedback input terminal ( DCLKI ) of the memory control chip 110 . There is a phase-locked loop (not shown) in the memory control chip 110 for adjusting the phase of the clock pulse sent by the clock pulse signal output terminal (DCLKO). Since the data signal pin of the memory module on the memory module slot is 64 bits wide, when the time pulse generation pin (DCLKO) of the memory control chip 110 sends the time pulse signal, and cooperates with an address to access any memory module, which means that there may be 64-bit data changes on the data bus 115, and the data changes on the data bus 115 will cause a lot of noise on the data signal pin (DATA) of the memory control chip, such as switching the output ( Simultaneous Switch Output, referred to as SSO) noise. In order to overcome this problem, it is necessary to arrange many power/ground pins near the data signal pin (DATA) in the memory control chip 110, so as to increase the charging and discharging path when the data signal pin (DATA) changes to quickly eliminate noise, and make the noise control within the allowable range.

With the development of semiconductor technology, the computing power of the central processing unit has improved rapidly. Therefore, the bus width of the memory control chip in the personal computer must also be expanded in order to cooperate with the computing power of the central processing unit.

Please refer to FIG. 2 , which shows a conventional memory control circuit with a 128-bit width structure. Under this structure, the 128-bit data bus 155 is provided with 64-bit data signals by each of the two memory modules 162 and 164, and the motherboard of this structure needs at least an even number of memory modules to operate. As shown in the figure, the circuit includes: a memory control chip 150 , a clock buffer 180 , a third memory module 162 and a fourth memory module 164 . The above-mentioned third memory module 162 and fourth memory module 164 are defined as the same memory bank (Memory bank) 160 inserted into individual memory module slots (not shown). Since the bus data signal pin (DATA) of the memory control chip 150 is 128 bits wide, and the sum of the data signal pins SD1 and SD2 of the third memory module 162 and the fourth memory module 164 is 128 bits wide, so the memory control chip The 150 can use the 128-bit wide data bus 155 to simultaneously access the data of the memory modules 162 and 164 in the same memory bank (Memory bank) 160 . Under this structure, the timing pulse generation pin (DCLKO) of the memory control chip 150 is connected to the timing pulse input terminal (CKI) of the timing pulse buffer 180 to enhance the driving capability of the timing pulse signal, and then use the timing pulse buffer The clock pulse output terminal (CKO1) of the device 180 outputs a clock pulse signal to drive the third memory module 162 and the fourth memory module 164 simultaneously. Therefore, the timing pulse signal can be sent to the third memory module 162 and the fourth memory module 164 as a reference timing pulse signal during data access. The time pulse feedback output terminal (CKO2) of the time pulse buffer 180 sends the time pulse signal back to the time pulse feedback input terminal (DCLKI) of the memory control chip 150, for the memory control chip 110 to adjust the time pulse generation pin (DCLKO ) sent by the time pulse phase.

In terms of the new 128-bit wide DDR DRAM memory module, each access will cause at most 128-bit data changes on the data bus 155. It is conceivable that when the data signal changes, the memory control for processing 128-bit data signals The noise of the chip 110 at the data signal pin (DATA) must be much larger than the noise at the data signal pin of the memory control chip that processes 64-bit data signals. Therefore, to simultaneously access 128-bit data with the same time pulse signal, it is necessary to add a lot of power/ground pins, which are arranged near the data signal pin (DATA) to reduce its noise. However, in order to avoid greatly increasing the manufacturing cost, the memory control chip 110 is packaged in a 37.5mm*37.5mm package, and due to the limitation of the number of pins, it is impossible to arrange enough power/ground pins. However, if the number of power/ground pins is arranged Insufficient, it will be difficult to overcome the problem of noise.

Contents of the invention

In view of this, the present invention provides a memory control chip, a control method and a control circuit, which can overcome the problem of noise under the arrangement of fewer power/ground pins.

To achieve the above and other purposes, the present invention provides a memory control chip for accessing a plurality of memory modules in a storage group, including: multiple groups of data signal pins, each group of data signal pins can be connected correspondingly A set of data signal pins to each memory module. And, a plurality of timing pulse generation pins output corresponding timing pulse signals and input them to the timing pulse input pins of each memory module. Wherein, all the time pulse signals have the same frequency and have a predetermined phase difference with each other.

The present invention also provides a memory control method, which is used to control multiple memory modules in the same memory group, comprising the following steps: first, multiple groups of chip data signal pins are provided, and each group of chip data signal pins can be connected correspondingly A set of data signal pins to each memory module. Next, a plurality of time pulse signals are provided corresponding to the time pulse input pins of each memory module, so that each memory module can perform data access of the memory module according to the corresponding time pulse signal, wherein, all time The pulse signals have the same frequency and have a predetermined phase difference with each other. Then, according to the time pulse signal, data access of the group data signal pins corresponding to each memory module is performed sequentially by different groups of chip data signal pins.

In addition, the present invention also provides a memory control circuit, including: a plurality of memory modules, each memory module has a clock pulse input pin and a set of data signal pins, wherein these memory modules are the same memory group. And, a memory control chip has multiple sets of data signal pins, each set of data signal pins can be connected to a set of data signal pins of each memory module, and has multiple time pulse generation pins, output The corresponding clock signal is sent to the clock input pin of each memory module. Wherein, all the time pulse signals have the same frequency and have a predetermined phase difference with each other.

Because of the memory control chip, control method and control circuit provided by the present invention, the bus data that originally referred to the same time pulse has been changed to refer to different time pulses with a predetermined phase difference. Therefore, it has at least the following advantages:

1. Since the amount of data that changes simultaneously is reduced, the simultaneous switching noise (SSO) generated is also reduced.

2. The problem of noise can be overcome by arranging fewer power supply/ground pins, so the manufacturing cost can be greatly reduced.

Description of drawings

In order to make the above and other purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, as follows:

Fig. 1 shows a kind of existing memory control circuit;

FIG. 2 is a diagram illustrating a memory control circuit under a 128-bit width structure;

FIG. 3 is a diagram showing a memory control circuit according to a preferred embodiment of the present invention; and

FIG. 4 is a timing diagram showing time pulses according to a preferred embodiment of the present invention.

Explanation of symbols in the figure:

110, 150, 210 memory control chip

115, 155 data bus

120 first memory module

130 Second memory module

140, 180, 240 time pulse buffer

160, 220 storage groups

162 The third memory module

164 fourth memory module

212 The first data bus

214 Second data bus

222 fifth memory module

224 Sixth memory module

Detailed ways

Please refer to FIG. 3 , which shows a memory control circuit in a 128-bit width structure according to a preferred embodiment of the present invention. The circuit includes: a memory control chip 210 , a clock buffer 240 , a fifth memory module 222 and a sixth memory module 224 . The above-mentioned fifth memory module 222 and sixth memory module 224 are defined as the same memory bank (Memory bank) 220 inserted in individual memory module slots (not shown).

Since the bus data signal pins (DATA1 and DATA2) of the memory control chip 210 are 128-bit wide, and the sum of the data signal pins SD1 and SD2 of the fifth memory module 222 and the sixth memory module 224 is 128-bit wide, the memory The control chip 210 can use the 128-bit wide data bus to access the data of the memory modules 222 and 224 in the same memory bank 220 . Wherein, the first group of chip data signal pins ( DATA1 ) are connected to the first group of data pins ( SD1 ) of the fifth memory module 222 , and are accessed through the first data bus 212 with a width of 64 bits. The second group of chip data signal pins ( DATA2 ) are connected to the second group of data pins ( SD2 ) of the sixth memory module 224 and accessed through the second data bus 214 with a width of 64 bits.

It can be seen from the figure that the first timing pulse generating pin (DCLKOL) of the memory control chip 210 outputs a first timing pulse, and the second timing pulse generating pin (DCLKOH) outputs a second timing pulse. The two time pulses are respectively input to the first time pulse input terminal (CKI1) and the second time pulse input terminal (CKI2) of the time pulse buffer 240, in order to enhance the driving capability of the time pulse signal, and then the time pulse buffer 240 The first time pulse output terminal (CKO1) and the second time pulse output terminal (CKO2) of the first time pulse output terminal (CKO2) respectively output the first time pulse signal and the second time pulse signal to the time pulse input pin (CK1) of the fifth memory module 222 and The clock pulse input pin (CK2) of the sixth memory module 224. Therefore, the fifth memory module 222 and the sixth memory module 224 can respectively refer to the first time pulse and the second time pulse to achieve data access.

Moreover, the first timing pulse feedback output terminal (CKO11) and the second timing pulse feedback output terminal (CKO12) of the timing pulse buffer 240 respectively transmit the first timing pulse timing signal and the second timing pulse signal back to the memory control chip The first timing pulse feedback input terminal (DCLKIL) and the second timing pulse feedback input terminal (DCLKIH) of 210 are used for the memory control chip 210 to individually adjust the first timing pulse generation pin (DCLKOL) and the second timing pulse generation The time pulse sent by the pin (DCLKOH).

Since the number of power/ground pins is limited by the package size of 37.5mm*37.5mm for the memory control chip, here we use a predetermined phase difference between the first time pulse signal and the second time pulse signal of the same cycle time, It is sent out by the first time pulse generation pin (DCLKOL) and the second time pulse generation pin (DCLKOH) respectively (as shown in Figure 4, the first time pulse generation pin (DCLKOL) and the second time pulse generation pin (DCLKOH) ) There is a phase difference A) between the two time pulse signals sent out.

That is, the fifth memory module 222 and the sixth memory module 224 refer to the first time pulse signal and the second time pulse signal respectively, so the first data signal 212 and the second data signal 214 are received by the memory control chip 210 at different times. Access, because each access only has a change of 64 bits at most (the data change on the first data bus 212 or the second data bus 214), so just less power/ground pins can be used, and in A lot of noise caused by Simultaneous Switch Output (SSO) caused by 64-bit data changes is eliminated twice at two different times, without increasing the number of power/ground pins to eliminate 128-bit data changes.

Of course, the above-mentioned chip data signal pins and time pulse generation pins are not limited to two groups. As long as there are memory control chips with different bit widths, they can be adjusted to the appropriate time pulse generation pins at any time to generate multiple time pulse signals corresponding to the control chip data. The data signal can be accessed by the signal pin. In terms of the design of the predetermined phase difference (phase difference A), for DDR DRAM, the data access operation is performed with reference to the rising and falling edges of the time pulse, so the predetermined phase difference (phase difference A) needs to be controlled within Less than 1/2 cycle, such as 1/4 cycle time or 1/8 cycle time, among which 1/4 cycle time is the best, because the data change interval between the first data signal 212 and the second data signal 214 is the largest, so SSO Can be effectively controlled within a certain range.

In addition, when the number of memory modules is small, the first timing pulse generating pin (DCLKOL) can also be directly connected to the timing pulse input pin (CK1) of the fifth memory module 222 . And the second clock pulse generating pin (DCLKOH) is directly connected to the clock clock input pin (CK2) of the sixth memory module 224 . In this way, two time pulses with a predetermined phase difference can also be used to access two memory modules in the same bank.

According to this embodiment, the frequencies of the first time pulse and the second time pulse are, for example, 133 MHz or 166 MHz. When the frequency of the first time pulse and the second time pulse is 133MHz, the data transmission rate on the first data bus 212 and the second data bus 214 is 266MHz, and the predetermined phase difference is set as 1/8 cycle of the first time pulse The noise can be effectively controlled within a predetermined range. When the frequency of the first time pulse and the second time pulse is 166MHz, the data transmission rate on the first packet data signal pin (DATA1) and the second packet data signal pin (DATA2) is 333MHz, and the predetermined phase difference is set When it is set as 1/4 period of the first time pulse, the noise can be effectively controlled within a predetermined range.

Therefore, because of the memory control chip, control method and control circuit provided by the present invention, the bus data that originally referred to the same time pulse has been changed to refer to different time pulses with a predetermined phase difference. Therefore, it has at least the following advantages:

1. Since the amount of data that changes simultaneously is reduced, the simultaneous switching noise (SSO) generated is also reduced.

2. The problem of noise can be overcome by arranging fewer power supply/ground pins, so the manufacturing cost can be greatly reduced.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims in combination with the specification and drawings.

Claims (10)

1. A memory control chip for accessing a first and second memory module in a memory group, at least comprising: a first data signal pin connected to a first data signal pin of the first memory module; a second data signal pin connected to a second data signal pin of the second memory module; a first timing pulse generating pin for outputting a first timing pulse signal for inputting to a first timing pulse input pin of the first memory module; and a second timing pulse generating pin for outputting a second timing pulse signal for inputting to a second timing pulse input pin of the second memory module; Wherein, the first and second time pulse signals have the same frequency and there is a predetermined phase difference between them, and the memory control chip sequentially generates data from the first and second chips according to the first and second time pulse signals The signal pins perform data access to the first and second data signal pins corresponding to the first and second memory modules. 2. The memory control chip according to claim 1, wherein the memory control chip is coupled to a clock buffer, and the clock buffer is connected to the first and second clock generation pins and between the timing pulse input pins of the first and second memory modules to increase the driving capability of the timing pulse signals. 3. The memory control chip according to claim 2, wherein the time pulse buffer has a plurality of time pulse feedback output terminals correspondingly connected to a plurality of time pulse feedback input terminals of the memory control chip for adjusting The phases of the corresponding time pulse signals. 4. The memory control chip as claimed in claim 1, wherein the number of the memory modules is two. 5. The memory control chip as claimed in claim 1, wherein each group of data signal pins of the memory control chip has a width of 64 bits. 6. The memory control chip as claimed in claim 1, wherein the group of data signal pins of each memory module has a width of 64 bits. 7. A memory control method for controlling a first and a second memory module in the same memory group, comprising the following steps: providing a first chip data signal pin, the first chip data signal pin being connected to a first data signal pin of the first memory module; providing a second chip data signal pin, the second chip data signal pin being connected to a second data signal pin of the second memory module; providing and adjusting a first and a second time pulse signal so that the first and second time pulse signals have the same frequency and have a predetermined phase difference; providing the first and second clock signals to a first and second clock input pins of the first and second memory modules, respectively, so that the first and second memory modules can operate according to the first and second a time pulse signal for data access to the first and second memory modules; and According to the first and second timing pulse signals, the first and second chip data signal pins sequentially perform data access to the first and second data signal pins. 8. A memory control circuit comprising at least: A first memory module, the first memory module has a first time pulse input pin and a first data signal pin; A second memory module, the second memory module has a second time pulse input pin and a second data signal pin, wherein the first and second memory modules are in the same memory group; and A memory control chip, having a first and a second memory data signal pin, and the first and second data signal pin are correspondingly connected to the first and second memory data signal pins of the first and second memory modules bit, and has a first and a second memory timing pulse generating pin for outputting a first and a second timing pulse signal for inputting to the first and second memory timing of the first and second memory modules Pulse input pin; Wherein, the first and second time pulse signals have the same frequency and have a predetermined phase difference between them. 9. The memory control circuit according to claim 8, further comprising a clock buffer connected to the first and second memory clock generation pins and the clocks of the first and second memory modules Between the pulse input pins, it is used to increase the driving capability of the first and second time pulse signals. 10. The memory control circuit according to claim 9, wherein the time pulse buffer has a plurality of time pulse feedback output terminals correspondingly connected to a plurality of time pulse feedback input terminals of the memory control chip for adjusting corresponding to the phases of the first and second time pulse signals.

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