[go: up one dir, main page]

GB2376328A - Processor having replay architecture with fast and slow replay paths - Google Patents

Processor having replay architecture with fast and slow replay paths Download PDF

Info

Publication number
GB2376328A
GB2376328A GB0221325A GB0221325A GB2376328A GB 2376328 A GB2376328 A GB 2376328A GB 0221325 A GB0221325 A GB 0221325A GB 0221325 A GB0221325 A GB 0221325A GB 2376328 A GB2376328 A GB 2376328A
Authority
GB
United Kingdom
Prior art keywords
replay
fast
processor
paths
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0221325A
Other versions
GB2376328B (en
GB0221325D0 (en
Inventor
Michael D Upton
David J Sager
Darrell D Boggs
Glenn J Hinton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/503,853 external-priority patent/US6735688B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0221325D0 publication Critical patent/GB0221325D0/en
Publication of GB2376328A publication Critical patent/GB2376328A/en
Application granted granted Critical
Publication of GB2376328B publication Critical patent/GB2376328B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.

Description

(57) According to one aspect of the invention, a microprocessor is
provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.
GB0221325A 2000-02-14 2000-12-29 Processor having replay architecture with fast and slow replay paths Expired - Fee Related GB2376328B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/503,853 US6735688B1 (en) 1996-11-13 2000-02-14 Processor having replay architecture with fast and slow replay paths
PCT/US2000/035590 WO2001061480A1 (en) 2000-02-14 2000-12-29 Processor having replay architecture with fast and slow replay paths

Publications (3)

Publication Number Publication Date
GB0221325D0 GB0221325D0 (en) 2002-10-23
GB2376328A true GB2376328A (en) 2002-12-11
GB2376328B GB2376328B (en) 2004-04-21

Family

ID=24003786

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0221325A Expired - Fee Related GB2376328B (en) 2000-02-14 2000-12-29 Processor having replay architecture with fast and slow replay paths

Country Status (7)

Country Link
KR (1) KR100508320B1 (en)
CN (1) CN1208716C (en)
AU (1) AU2001224640A1 (en)
DE (1) DE10085438B4 (en)
GB (1) GB2376328B (en)
HK (1) HK1048872B (en)
WO (1) WO2001061480A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266673B2 (en) * 2003-05-02 2007-09-04 Advanced Micro Devices, Inc. Speculation pointers to identify data-speculative operations in microprocessor
US7165167B2 (en) * 2003-06-10 2007-01-16 Advanced Micro Devices, Inc. Load store unit with replay mechanism
CN100362536C (en) * 2004-09-10 2008-01-16 华中科技大学 An intelligent vehicle condition monitoring system based on mobile communication
US20110320781A1 (en) 2010-06-29 2011-12-29 Wei Liu Dynamic data synchronization in thread-level speculation
KR101254911B1 (en) * 2012-01-31 2013-04-18 서울대학교산학협력단 Method, system and computer-readable recording medium for performing data input and output via multiple path
CN103744800B (en) * 2013-12-30 2016-09-14 龙芯中科技术有限公司 Caching method and device towards replay mechanism
KR102668233B1 (en) 2018-09-04 2024-05-23 삼성전자주식회사 Electronic device for obtaining images by controlling frame rate for external object moving through point ofinterest and operating method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618042A (en) * 1968-11-01 1971-11-02 Hitachi Ltd Error detection and instruction reexecution device in a data-processing apparatus
WO1998021684A2 (en) * 1996-11-13 1998-05-22 Intel Corporation Processor having replay architecture
US6094717A (en) * 1998-07-31 2000-07-25 Intel Corp. Computer processor with a replay system having a plurality of checkers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618042A (en) * 1968-11-01 1971-11-02 Hitachi Ltd Error detection and instruction reexecution device in a data-processing apparatus
WO1998021684A2 (en) * 1996-11-13 1998-05-22 Intel Corporation Processor having replay architecture
US6094717A (en) * 1998-07-31 2000-07-25 Intel Corp. Computer processor with a replay system having a plurality of checkers

Also Published As

Publication number Publication date
GB2376328B (en) 2004-04-21
HK1048872B (en) 2004-10-21
KR20030007425A (en) 2003-01-23
DE10085438B4 (en) 2006-01-05
AU2001224640A1 (en) 2001-08-27
WO2001061480A1 (en) 2001-08-23
CN1208716C (en) 2005-06-29
DE10085438T1 (en) 2003-01-16
KR100508320B1 (en) 2005-08-17
GB0221325D0 (en) 2002-10-23
CN1452736A (en) 2003-10-29
HK1048872A1 (en) 2003-04-17

Similar Documents

Publication Publication Date Title
US7581090B2 (en) Interrupt control apparatus and method
HK1048539A1 (en) Processing architecture having sub-word shuffling and opcode modification
WO1998021684A3 (en) Processor having replay architecture
EP1386476A4 (en) TECHNIQUE FOR EFFECTIVELY COMMUNICATING MOVEMENT DIRECTIONS
WO2001055821A3 (en) Microprocessor resistant to power analysis
TW351791B (en) Processor having execution core sections operating at different clock rates
HK1050254A1 (en) Isolated instructions for isolated execution
GB2366879B (en) Tracing the execution path of a computer program
JP2000020305A5 (en)
EP0933698A3 (en) Probing computer memory latency
EP1300758A3 (en) Dynamically switching statically bound function calls to dynamically bound function calls without recomplication
IL140267A0 (en) Dual processor trusted computing environment
GB2376328A (en) Processor having replay architecture with fast and slow replay paths
WO2003023701A3 (en) Operating device
WO2003081454A8 (en) Method and device for data processing
MY126922A (en) Turbo decoder with circular redundancy code signature comparison
WO2001016697A3 (en) Local register instruction for micro engine used in multithreadedparallel processor architecture
TW334546B (en) Data processor
WO2002097604A3 (en) Floating point adder with embedded status information
WO2001075635A3 (en) Dsp execution unit for efficient alternate modes of operation
WO2002035754A3 (en) Generation of correctly ordered test code for testing software components
WO2001095101A3 (en) Synchronizing partially pipelined instructions in vliw processors
WO2002029554A3 (en) Register move operations
DE50112962D1 (en) COMPUTER KNOT ARCHITECTURE WITH DEDICATED MIDDLEWARE PROCESSOR
DE50213654D1 (en) LINE ERROR

Legal Events

Date Code Title Description
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1048872

Country of ref document: HK

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20161229