CN1208716C - Processor with replay architecture with fast and slow replay paths - Google Patents

Abstract

According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.

Description

Processor with replay architecture with fast and slow replay paths

Cross References to Related Applications

This application is a continuation-in-part of Application Serial No. 09/222,805, filed 12/30/98, which in turn is a successor-in-part of Application Serial No. 08/746,547, filed 11/23/96, which is now a U.S. Patent No. 5,966,544. This application and the applications identified above are assigned to Intel Corporation of Santa Clara, California.

Background of the invention

1. Field of invention

The present invention relates generally to the field of processors, and more particularly to a playback architecture with fast and slow playback paths for facilitating data prediction operations.

2. Background information

Figure 1 shows a block diagram of one embodiment of a processor 100 disclosed in US Patent No. 5,966,544. The processor 100 shown in FIG. 1 includes an I/O ring 111 operating at a first clock frequency (I/O clock), a delay-tolerant execution core 121 operating at a second clock frequency (e.g., a slow clock), Latency-intolerant execution sub-core 131 operating at three clock frequencies (eg, medium clock) and latency-critical execution sub-core 141 operating at a fourth clock frequency (eg, fast clock). Processor 100 shown in FIG. 1 also includes time multiply and/or divide units 110, 120, and 130, which may be configured to give processor 100 sub-cores different Sections provide proper timing. The previous application teaches what particular part is most appropriate here is that an execution core may consist of two or more parts (sub-cores) operating at different clock rates.

In operation, the I/O ring 111 communicates with other parts of the computer system (not shown) by performing various I/O operations at the I/O clock rate, such as memory reads and writes. For example, the processor 100 may perform an I/O operation on the I/O ring 111 at an I/O clock frequency to read data from an external storage device. Different execution sub-cores 121, 131 and 141 are capable of performing different functions or operations at their respective clock frequencies according to input instructions and/or input data. For example, delay-tolerant execution sub-core 121 may complete an execution operation on input data to produce a first result. Latency-intolerant sub-core 131 may complete execution operations on the first result to produce the second result. Likewise, latency-critical execution sub-core 141 may complete another execution operation on the second result to generate the third result. Different operations performed by different executive sub-cores include arithmetic operations, logical operations, and other operations, among others. Those skilled in the art should understand and understand that the order of performing these different operations does not necessarily follow the hierarchical order of multiple execution sub-cores. For example, input data can immediately go directly to the innermost sub-core, where results obtained can be passed from the innermost sub-core to any other sub-core or back to the I/O ring 111 for writing back. Additionally, the on-chip cache structure may be partitioned into two or more portions of processor 100 as disclosed and taught in prior applications. Likewise, certain operations and/or functions may be performed at one clock frequency based on one characteristic of the data stored in the on-chip cache memory while also being clocked at a different frequency based on another characteristic of the data stored in the on-chip cache memory Perform other operations and/or functions. For example, way predictor misses on on-chip cache memory may be performed at one clock frequency in one sub-core while TLB hit/miss detection and/or page detection are performed at a different frequency on another sub-core. Miss detection. Also, certain errors and conditions can be detected earlier in the execution process than others.

FIG. 2 depicts a block diagram of one embodiment of a processor 200 disclosed in the prior application, which includes a general replay structure to facilitate data prediction operations. In this embodiment, processor 200 includes scheduler 231 coupled to multiplexer 241 to provide instructions received from instruction cache (I-cache) 211 to execution core 251 for execution. Execution core 251 may perform data prediction among execution of different instructions received from multiplexer 241 . The processor 200 shown in FIG. 2 includes a checker unit 281 to send a copy of the executed instruction back to the execution core 251 for re-execution (replay) when a data detection error is determined. However, in this general replay structure, checker unit 281 is located after execution core 251 , TLB and tag logic 261 , and cache hit/miss logic 271 . Some instructions may have been known to be executed incorrectly (ie, because of data mispredictions) before this checker location allows detection. Specifically, in some cases certain errors and conditions can be detected earlier, even before TLB/TAG logic 261 and hit/miss logic 271 are executed, which indicate data prediction in these cases it is wrong. Unfortunately, because of the current positioning of checker unit 281 , corresponding instructions that were mis-executed due to erroneous data predictions are not sent back to execution core 251 for re-execution or replay until they reach checker 281 . Thus, there is an unnecessary delay between the time it is known that an instruction has been executed incorrectly due to erroneous data predictions, until the time the corresponding instruction is sent back for re-execution. Thus, system performance is not optimized to the extent that these incorrectly executed instructions are re-executed or replayed earlier in the process than they should be.

Summary of the invention

According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism, and a second replay mechanism. The execution core performs data prediction during execution of the first instruction. A first replay mechanism is used to replay a first instruction via a first replay path upon detection of a first type of error indicative of a data misprediction. The second replay mechanism is used to replay the first instruction through the second replay path upon detection of an instruction of the second type indicating a data misprediction.

Figure overview

The features and advantages of the present invention will be more fully understood with reference to the accompanying drawings, in which:

1 is a block diagram of one embodiment of a processor including multiple sub-cores operating at different frequencies;

Figure 2 shows a block diagram of one embodiment of a processor with a general replay architecture;

Figure 3 depicts a block diagram of one embodiment of a processor pipeline in which the teachings of the present invention are implemented;

Figure 4 shows a block diagram of an embodiment of a processor with first and second replay mechanisms;

Figure 5 shows a more detailed block diagram of an embodiment of a processor with first and second replay mechanisms;

Figure 6 shows a flow diagram of one embodiment of a method in accordance with the teachings of the present invention.

A detailed description

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.

In the following discussion, the teachings of the present invention are utilized to implement methods, devices, and systems for facilitating data prediction in executing instructions. To reduce execution time, the execution unit performs data prediction during execution of input instructions. If the data prediction is wrong, the input instruction is re-executed by the execution unit until the correct result is obtained. In one embodiment, a data prediction error is determined if errors of the first type and the second type are detected. Errors of the first type can be detected before errors of the second type. In one embodiment, the first checker is responsible for sending a first copy of the input instruction back to the execution unit for re-execution or replay if a first type of error is detected upon execution of the input instruction. The second checker is responsible for sending a second copy of the input instruction back to the execution unit for re-execution or replay if an error of the second type is detected upon execution of the input instruction. In one embodiment, the selector is used to provide subsequent input instructions, the first copy or the second copy of the incorrectly executed instruction, to the execution unit for execution according to a predetermined priority mechanism. The teachings of the present invention apply to any processor or machine that performs data prediction in executing instructions. However, the present invention is not limited to processors or machines that perform data prediction, and can be applied to any processor and machine where a multi-stage replay mechanism is required.

Figure 3 is a block diagram of one embodiment of a processor pipeline 300 in which the present invention may be implemented. For purposes of this description, the term "processor" refers to any machine capable of executing a sequence of instructions, including but not limited to general-purpose microprocessors, special-purpose microprocessors, graphics controllers, audio processors, video processors, multimedia controllers and microcontrollers. Processor pipeline 300 includes a plurality of processing stages and begins with fetch stage 310 . At this stage, instructions are fetched and provided to pipeline 300 . For example, macroinstructions may be fetched from cache memory integrated in or closely coupled to the processor or from external memory via the system bus. Instructions fetched in fetch stage 310 are then input to decode stage 320, where the instructions or macroinstructions are decoded into microinstructions or micro-operations (also referred to herein as UOPs or uops) for execution by the processor. At the allocation stage 330, the processor resources necessary to execute the microinstructions are allocated. The next stage in the pipeline is the rename stage 340, where references to external registers are converted to internal register references to eliminate false dependencies created by register reuse. At the dispatch/dispatch stage 350, each microinstruction or UOP is dispatched and dispatched to an execution unit. Microinstructions or UOPs are then executed at execution stage 360 . After execution, the microinstruction or UOP is exited at the exit level.

In one embodiment, the multiple stages described above can be organized into three stages. The first stage, which may be referred to as the in-order front end, includes fetch stage 310 , decode stage 320 , allocate stage 330 and rename stage 340 . In the in-order front-end stage, instructions pass through pipeline 300 in their original program order. The second stage, which may be referred to as an out-of-order execution stage, includes a scheduling/allocation stage 350 and an execution stage 360 . At this stage, an instruction is scheduled, dispatched, and executed whenever its data dependencies are resolved and appropriate execution units are available, regardless of its sequential position in the original program. The third stage, referred to as the orderly exit stage, includes the exit stage 370 in which instructions are retired in their original, sequential program order to preserve program integrity and semantics.

In a processor with a replay structure, certain non-routine behaviors can be taken based on the scheduling and execution of incoming instructions. For example, even if the source data for an input UOP is not yet ready or unknown, it can be dispatched to an execution unit for execution. If the execution of the input UOP determines that the data prediction is wrong, the corresponding UOP is sent back to the execution unit for re-execution (replay) until the correct result is obtained. Of course, it is desirable to limit the number of replays or re-executions, since each replayed UOP uses available resources and reduces overall system performance. Additionally, there is a net performance gain to be gained from such ventures. For example, if a majority of UOPs get correct execution with a reduced number of cycles, and only a few UOPs have to be replayed, what is the overall throughput relative to the least common denominator case of making all UOPs wait as long as the worst case could take will improve.

As taught in the prior application, an on-chip data cache (also known as level zero or L0 data cache) can be partitioned such that its data storage array resides in determined in a logic higher clock region. The TLB and flag logic can also reside in a slower clock region than the data storage array. The TLB and flag logic can also be in the same clock region as the hit/miss logic, but this is not required.

One situation where a net performance gain can be obtained is when the execution of UOPs relies on or uses data from the L0 data cache. Instead of making all UOPs wait until their source data is determined to be valid, speculatively allocate and execute some UOPs earlier in the process—even if they don't know it yet, but think it's likely to be executed—so that their source data Residing in the L0 data cache. In most cases, the L0 data cache will be hit and valid data will be used as source data. There are only a few cases where the data prediction is wrong and the UOP has to be replayed. Also, most UOPs are executed correctly in a reduced number of cycles, thus improving overall performance.

4 is a block diagram of one embodiment of a processor 400 with first (also referred to as fast or early) and second (also referred to as slow or late) replay paths to facilitate data prediction in executing instructions . As shown in FIG. 4, processor 400 includes a scheduler/distributor 411 coupled to an instruction cache (not shown) to schedule and distribute through a selector (or multiplexer) 421 received from the instruction cache The first instruction goes to execution core 431 for execution. In one embodiment, execution core 431 performs data speculation during execution of input instructions. As mentioned above, even though the source data of the input instruction may not be ready or unknown, it can be allocated. For example, execution of an incoming instruction may require source data that may or may not be in the L0 cache. However, as explained above, net performance can be improved by predicting that the source data required for the execution of an incoming instruction resides in the L0 data cache. The processor 400 also includes a first replay mechanism 441 to re-execute an input instruction upon detection of a first type of error indicating a data misprediction. In one embodiment, errors of the first type are detectable in the first stage. Processor 400 also includes a second replay mechanism 451 to re-execute an input instruction upon detection of a second type of error indicating a data misprediction. In one embodiment, errors of the second type are detectable in a second stage, which is longer than the first stage. Also, if an error of the first type has been detected, the invention allows re-execution of an incorrectly executed instruction much faster than if the instruction had to wait until an error of the second type was detected. As shown in FIG. 4, if it is determined that the execution of the input instruction was incorrectly executed because of a first type of error that has been detected indicating a data misprediction, the first replay mechanism (fast or early checker) 441 will pass the replay The processor 421 sends the corresponding instruction back to the execution core 431 for re-execution (playback). Likewise, the second replay mechanism (slow or late checker) 451 will pass the multiplexer 421 sends the corresponding instruction back to execution core 431 for re-execution (replay). The function and operation of the first and second playback mechanisms shown in FIG. 4 will be described in detail below.

FIG. 5 shows a more detailed block diagram of one embodiment of a processor 500 having the first and second playback paths described above with reference to FIG. 4 . As shown in FIG. 5, processor 500 includes a scheduler 511 that schedules and distributes instructions received from an instruction cache (not shown) through a multiplexer 521 to execution cores 531 for execution. The function and operation of the multiplexer 521 are described in detail below. In one embodiment, execution core 531 performs data prediction during execution of input instructions received from multiplexer 521 . The processor 500 also includes a first delay unit 541 to generate a first copy of the input instruction and hold the first copy of the input instruction in the first clock region for at least one clock cycle. Processor 500 also includes a first checker 545 coupled to first delay unit 541 and execution core 531 . In one embodiment, the first checker 545 may be configured to determine whether the data prediction is correct with respect to the first set of error types and pass the first data of the input instruction through the first buffer 547 when the data prediction is wrong with respect to the first set of error types. The copy is sent back to the execution core for re-execution. As shown in FIG. 5, the processor 500 also includes a second delay unit 551, which is coupled to the first delay unit and which in one embodiment can be configured to generate a second copy of the incoming instruction and clock in a second clock region Save it for at least one clock cycle. Processor 500 includes a second checker 555 coupled to second delay unit 551 and first checker 545 . In one embodiment, the second checker is configurable to determine whether the execution of the instruction was erroneous with respect to the second set of error types and to send the incoming instruction back through the second buffer 557 when the execution was erroneous with respect to the second set of error types to the execution core 531 for repeated execution. As shown in FIG. 5 , the multiplexer 521 is coupled to the scheduler 511 , the execution core 531 , the first delay unit 541 , the first checker 545 , the second checker 555 , the first buffer 547 and the second buffer 557 . In one embodiment, multiplexer 521 may be configured to receive an incoming instruction and a successor instruction from an instruction cache, receive a first copy of an incoming instruction from a first checker, and receive a second copy of an incoming instruction from a second checker. copy. In one embodiment, the multiplexer 521 may be further configured to selectively provide the subsequent instruction, the first copy of the incoming instruction, or the second copy of the incoming instruction to the execution core 531 for execution according to a predetermined priority scheme. In one embodiment, the second copy of the incoming instruction is given a first execution priority, the first copy of the incoming instruction is given a second execution priority, and the subsequent instruction is given a third execution priority. In one embodiment, the first priority is higher than the second priority, and the second priority is higher than the third priority. In one embodiment, the first set of error types is a subset of the second set of error types. In another embodiment, the first set of error types is the complement of the second set of error types. In one embodiment, the first set of error types includes errors indicating a level 0 cache way predictor miss, errors indicating a level 0 cache CAM extension mismatch, and errors indicating store-and-forward buffer data is unknown. In one embodiment, the second set of error types includes errors indicating a TLB miss, errors indicating a page miss, or any other error indicating that an instruction was executed incorrectly and the respective instruction needs to be re-executed, and so on. In one embodiment, the first delay unit 541 may be configured to provide the first copy of the incoming instruction to the first checker 545 after a predetermined number of clock cycles in the first clock region. In one embodiment, the predetermined number of clock cycles in the first clock region approximately corresponds to a time delay of an incoming instruction through the execution core.

In some cases another unit in processor 500 can generate its own instructions to perform its corresponding function. For example, a memory control unit or memory execution unit (not shown) in processor 500 may sometimes need to dispatch instructions for execution in its own pipeline, which pipeline includes complete store operations or UOPs to handle page splits and TLB reloads ,etc. These types of instructions are referred to as fabricated instructions because they are generated or fabricated by a unit in processor 500 and are not in the instruction stream from the instruction cache. In one embodiment, multiplexer 521 is also coupled to receive fabrication instructions and send them to execution core 531 for execution. Because the multiplexer 521 can receive instructions from different paths at the same time, a predetermined priority mechanism is needed to coordinate the execution priorities among the instructions sent to the multiplexer 521 from different paths. For example, the multiplexer may receive a subsequent instruction from the scheduler 511, a first copy of an incoming instruction to be replayed from the first checker 545, a copy of an incoming instruction to be replayed from the second checker 55, all in the same processing cycle or clock cycle. place another input instruction, and receive fabrication instructions from another unit (eg, a memory control or execution unit). In one embodiment, the multiplexer 521 gives low priority to instructions from the instruction cache, medium priority to replay instructions from the first checker, and high priority to replay instructions from the second checker. Priority, to give the manufacturing order the highest priority.

As indicated above, in one embodiment, the error conditions detected by the first checker 545 may be a subset of the error conditions detected by the second checker 555 . In this case, the second checker 555 needs to provide a robust check, since a UOP cannot be replayed by the second checker 555 once it arrives. In another embodiment, the error conditions handled by the first checker 545 may be the complement of the error conditions handled by the second checker 555 . In this case, the first checker 545 will need to provide robust checks on its set of error conditions, rather than the "highly confident but not guaranteed" checks described above, since later checkers will not recheck The result of the previous checker. Thus, subset mode is preferred.

As previously mentioned, the second checker 555 can provide additional and/or complementary checks on error conditions not handled by the first checker 545 . The decision as to which checker processor to use can be determined by a number of factors including, but not limited to, processor performance concerns, design complexity, die area, etc. In one embodiment, the second checker 555 is responsible for replaying instructions due to TLB misses and other various problems that may arise in the memory control unit (not shown) of the processor 500 . These various problems may include problems or errors that are difficult to detect for a short period of time, such as cache misses based on full physical address checks, incorrect forward stores based on full physical address checks, and so on.

In one embodiment, the first checker 545 and the second checker 555 cooperate to control the operation of the multiplexer 521 . As shown in Figure 5, the multiplexer 521 performs its corresponding function according to the selection signal received from the first checker 545, the second checker 555 and an optional another selection signal received from another unit, so Said another unit such as a memory control unit (not shown) that generates fabrication instructions that are not in the instruction stream from the instruction cache. If more than one instruction from multiple different paths is waiting to be executed, multiplexer 521 uses these different select signals to determine which instruction to send to execution core 531 for execution in a given processing cycle. In one embodiment, manufacturing instructions are given a first execution priority, instructions from the second checker 555 are given a second priority, the second priority being lower than the first priority, and instructions from the first checker 545 is given a third priority, which is lower than the second priority, and subsequent instructions from the instruction cache via the scheduler 511 are given a fourth priority, which is lower than the second priority.

In one embodiment, once a particular UOP has been sent out for fast playback by the first inspector 545, the same instance of that UOP will not be sent out for slow playback by the second inspector 555, because that would exist copy. To prevent this from happening, in one embodiment, each UOP may include special fields that are used by the first inspector 545 and the second inspector 555 to coordinate playback activity between the two inspectors. For example, in one embodiment, a UOP may include a field called NEEDS_FAST_REPLAY, which is set by the first checker 545 to indicate that the first checker 545 wants to send it out for fast playback. The corresponding UOP may also include another field called GOT_FAST_REPLAY. The GOT_FAST_REPLAY field, in one embodiment, is set by cooperation between the first checker 545 and the second checker 555 . For example, assume that the first checker wants to send the first instruction for fast playback because a first type of error has been detected. In this case, the first checker 545 will set the corresponding NEEDS_FAST_REPLAY field of the corresponding UOP to indicate that this particular UOP needs to be played back on the fast playback path. If in the same clock cycle the second checker 555 wants to send a second UOP for slow playback, the GOT_FAST_REPLAY field of the first instruction will be cleared and the multiplexer 521 will be controlled to select the slow playback UOP instead of the one looking for fast playback . Then, when the first UOP reaches the second checker 555, it will be sent out for playback on the slow playback path because its corresponding NEEDS_FAST_REPLAY field has been set.

FIG. 6 depicts a flowchart of one embodiment of a method 600 that uses fast and slow playback paths to facilitate data prediction operations. Method 600 begins at block 601 and proceeds to block 605 . At block 605, the execution core or unit performs data prediction in executing the input instruction. Method 600 then proceeds from block 605 to block 609 . At block 609, it is determined whether a first type of error has been detected. As explained above, in one embodiment, the first type of error occurs if the L0 data cache way predictor misses, in which case the data cannot be in the L0 data cache, the L0 data Cache CAM extension mismatch (i.e., route predictor hit but tag mismatch), or store-forward buffer data unknown (i.e., data is assumed to be forwarded from store-forward buffer, but store data does not class), etc. wait. At block 613, the input instruction is re-executed if an error of the first type has been detected. As mentioned above, when a first type of error is detected, the first checker unit (ie fast or early checker) will send a copy of the input instruction for replay or re-execution on the fast replay path. Method 600 proceeds to block 617 . At block 617, it is determined whether a second type of error has been detected. In such an embodiment, a second checker (ie, a slow or late checker) is responsible for determining whether a second type of error has occurred. At block 621, if an error of the second type has occurred, the input command is re-executed. As mentioned above, the second checker is responsible for sending a copy of the input command for replay on the slow replay path if an error of the second type has occurred.

The invention has been described in connection with the preferred embodiments. In view of the foregoing description it will be apparent to those skilled in the art that many arrangements, modifications, variations and uses are readily apparent.

Claims (20)

1. microprocessor comprises:

Carry out core, actual figure be it is predicted in carrying out first instruction;

First replay mechanism, with the mistake of the first kind that determines whether to detect the designation data prediction error, and if the mistake that has detected the first kind just the first authentic copy of article one instruction is beamed back and is carried out core and reset; And

Second replay mechanism determines whether to detect the mistake of second type, and if the mistake that has detected second type just the triplicate of article one instruction is beamed back and is carried out core and reset.

2. the microprocessor of claim 1, wherein the mistake of the first kind is detectable in first cycle, and the mistake of second type is detectable in second period, and second period is longer than first cycle.

3. the microprocessor of claim 1 also comprises:

First delay cell, this first authentic copy that produces article one instruction also keeps the first authentic copy at least one clock period in the first clock zone.

4. the microprocessor of claim 3 also comprises:

Second delay cell produces this triplicate of article one instruction, and keeps at least one clock period of triplicate in the second clock zone.

5. the microprocessor of claim 4 further comprises:

Instruction cache stores and provides article one instruction and a successor instruction to carrying out core.

6. the microprocessor of claim 5 further comprises:

Selector switch, coupling be used for from instruction cache receive successor instruction, from first replay mechanism receive article one instruction the first authentic copy, receive another instruction from second replay mechanism, selector switch according to predetermined precedence scheme offer carry out that core carries out be from instruction cache successor instruction, from the first authentic copy of article one instruction of first replay mechanism or from another instruction of second replay mechanism.

7. the microprocessor of claim 6, wherein selector switch comprises a multiplexer.

8. the microprocessor of claim 6, wherein another instruction is given first execution priority, article one, Zhi Ling the first authentic copy is given second execution priority, successor instruction is given the 3rd execution priority, second execution priority is lower than first execution priority, and the 3rd execution priority is lower than second execution priority.

9. the microprocessor of claim 1, wherein the mistake of the first kind is the subclass of the mistake of second type.

10. the microprocessor of claim 1, wherein the mistake of the first kind is the supplementary set of the mistake of second type.

11. the microprocessor of claim 1, wherein the mistake of the first kind is chosen from one group of mistake, and this group is wrong to be expanded unmatched mistake and indicated the mistake of storage intransit buffering district's data the unknown to form by the miss mistake of 0 grade of cache ways available line fallout predictor of indication, 0 grade of cache memory CAM of indication.

12. the microprocessor of claim 1, wherein the mistake of second type is chosen from one group of mistake, and this group is wrong to be made up of with the mistake from the incorrect forwarding of storing that indication is checked according to full physical address the miss mistake of indication TLB.

13. the microprocessor of claim 3, wherein first delay cell is the first authentic copy in order to provide article one to instruct after the predefine number of clock in the first clock zone, and predefined clock period quantity is roughly corresponding to the delay of article one instruction by the execution core in the first clock zone.

14. the microprocessor of claim 6 further comprises:

Be used for making not at device from the instruction of the instruction stream of instruction cache.

15. the microprocessor of claim 14, wherein selector switch is coupled to be used for receiving the instruction that produces and they are sent to the execution core and carries out.

16. the microprocessor of claim 15, wherein selector switch gives the instruction low priority from instruction cache, give the playback instructions medium priority from first detector, give the playback instructions high priority from second detector, the instruction that produces is with limit priority.

17. the microprocessor of claim 5 also comprises:

The scheduler that is coupled to instruction cache and carries out core, scheduling also distributes article one instruction that receives from instruction cache to be used to carry out core.

18. a method comprises:

Actual figure be it is predicted in the instruction of execution article one in carrying out core;

Detect the mistake of the first kind of designation data prediction error;

Response detects the mistake of the first kind, sends the first authentic copy of article one instruction by first playback path of carrying out the core execution;

Detect the mistake of second type of designation data prediction error; When detecting the first kind wrong, by carrying out the first authentic copy that core re-executes article one instruction;

Response detects the mistake of second type, sends the triplicate of article one instruction by second playback path of carrying out the core execution; And

When detecting second type wrong, re-execute the triplicate of article one instruction.

19. the method for claim 18, wherein the triplicate of article one instruction is assigned with execution priority, and the first authentic copy of article one instruction is assigned with execution priority.

20. the method for claim 19, wherein the execution priority of the triplicate of article one instruction is higher than the execution priority of the first authentic copy of article one instruction.

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