GB2374701B - Improved apparatus and method for multi-threaded signal procesing - Google Patents
Improved apparatus and method for multi-threaded signal procesingInfo
- Publication number
- GB2374701B GB2374701B GB0217126A GB0217126A GB2374701B GB 2374701 B GB2374701 B GB 2374701B GB 0217126 A GB0217126 A GB 0217126A GB 0217126 A GB0217126 A GB 0217126A GB 2374701 B GB2374701 B GB 2374701B
- Authority
- GB
- United Kingdom
- Prior art keywords
- profiled
- improved apparatus
- threaded
- temporal
- signal procesing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
- Logic Circuits (AREA)
- Mobile Radio Communication Systems (AREA)
- Advance Control (AREA)
Abstract
System and circuit design methodology and apparatus implements general functional definition (10) using multi-threaded representation thereof, which may be profiled for parallel processing using one or more corresponding kemel logic elements (18). Preferably, communication (26), networking, or media processing functionality or algorithm (12) is functionally analyzed and symbolically represented to identify one or more thread segments, which are each profiled (14) using temporal and/or non-temporal functions, according to one or more particular fixed, parameterizable, programmable, or reconfigurable logic kernel.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US49263400A | 2000-01-27 | 2000-01-27 | |
| PCT/US2001/002982 WO2001055917A1 (en) | 2000-01-27 | 2001-01-29 | Improved apparatus and method for multi-threaded signal processing |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0217126D0 GB0217126D0 (en) | 2002-09-04 |
| GB2374701A GB2374701A (en) | 2002-10-23 |
| GB2374701B true GB2374701B (en) | 2004-12-15 |
Family
ID=23956997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0217126A Expired - Fee Related GB2374701B (en) | 2000-01-27 | 2001-01-29 | Improved apparatus and method for multi-threaded signal procesing |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP2003521072A (en) |
| KR (1) | KR100784412B1 (en) |
| AU (1) | AU2001233119A1 (en) |
| DE (1) | DE10195202T1 (en) |
| GB (1) | GB2374701B (en) |
| WO (1) | WO2001055917A1 (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
| DE19651075A1 (en) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like |
| US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
| DE19861088A1 (en) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Repairing integrated circuits by replacing subassemblies with substitutes |
| US6986073B2 (en) | 2000-03-01 | 2006-01-10 | Realtek Semiconductor Corp. | System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a plurality of port sampling clock rates |
| US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
| AU2002220600A1 (en) | 2000-10-06 | 2002-04-15 | Pact Informationstechnologie Gmbh | Cell system with segmented intermediate cell structure |
| US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
| US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
| US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
| US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
| US7577822B2 (en) | 2001-12-14 | 2009-08-18 | Pact Xpp Technologies Ag | Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
| US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
| WO2004038599A1 (en) | 2002-09-06 | 2004-05-06 | Pact Xpp Technologies Ag | Reconfigurable sequencer structure |
| US7657893B2 (en) * | 2003-04-23 | 2010-02-02 | International Business Machines Corporation | Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor |
| CN101546255A (en) * | 2005-04-12 | 2009-09-30 | 松下电器产业株式会社 | processor |
| US7693257B2 (en) | 2006-06-29 | 2010-04-06 | Accuray Incorporated | Treatment delivery optimization |
| CN107193539B (en) * | 2016-03-14 | 2020-11-24 | 北京京东尚科信息技术有限公司 | Multithreaded concurrent processing method and multithreaded concurrent processing system |
| US11288072B2 (en) * | 2019-09-11 | 2022-03-29 | Ceremorphic, Inc. | Multi-threaded processor with thread granularity |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4821220A (en) * | 1986-07-25 | 1989-04-11 | Tektronix, Inc. | System for animating program operation and displaying time-based relationships |
| US5519867A (en) * | 1993-07-19 | 1996-05-21 | Taligent, Inc. | Object-oriented multitasking system |
| US5537226A (en) * | 1994-11-22 | 1996-07-16 | Xerox Corporation | Method for restoring images scanned in the presence of vibration |
| US5870588A (en) * | 1995-10-23 | 1999-02-09 | Interuniversitair Micro-Elektronica Centrum(Imec Vzw) | Design environment and a design method for hardware/software co-design |
| US5946487A (en) * | 1996-06-10 | 1999-08-31 | Lsi Logic Corporation | Object-oriented multi-media architecture |
| US6112020A (en) * | 1996-10-31 | 2000-08-29 | Altera Corporation | Apparatus and method for generating configuration and test files for programmable logic devices |
-
2001
- 2001-01-29 WO PCT/US2001/002982 patent/WO2001055917A1/en not_active Ceased
- 2001-01-29 GB GB0217126A patent/GB2374701B/en not_active Expired - Fee Related
- 2001-01-29 JP JP2001555391A patent/JP2003521072A/en active Pending
- 2001-01-29 AU AU2001233119A patent/AU2001233119A1/en not_active Abandoned
- 2001-01-29 KR KR1020027009711A patent/KR100784412B1/en not_active Expired - Fee Related
- 2001-01-29 DE DE10195202T patent/DE10195202T1/en not_active Ceased
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4821220A (en) * | 1986-07-25 | 1989-04-11 | Tektronix, Inc. | System for animating program operation and displaying time-based relationships |
| US5519867A (en) * | 1993-07-19 | 1996-05-21 | Taligent, Inc. | Object-oriented multitasking system |
| US5537226A (en) * | 1994-11-22 | 1996-07-16 | Xerox Corporation | Method for restoring images scanned in the presence of vibration |
| US5870588A (en) * | 1995-10-23 | 1999-02-09 | Interuniversitair Micro-Elektronica Centrum(Imec Vzw) | Design environment and a design method for hardware/software co-design |
| US5946487A (en) * | 1996-06-10 | 1999-08-31 | Lsi Logic Corporation | Object-oriented multi-media architecture |
| US6112020A (en) * | 1996-10-31 | 2000-08-29 | Altera Corporation | Apparatus and method for generating configuration and test files for programmable logic devices |
Non-Patent Citations (1)
| Title |
|---|
| "Multithreading with Distributed Functional Units" - Bernard Gunther - IEEE Transactions on Computer, Pages 399-411, Vol 46, No 4 April 1997. * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100784412B1 (en) | 2007-12-11 |
| DE10195202T1 (en) | 2003-04-30 |
| GB2374701A (en) | 2002-10-23 |
| WO2001055917A1 (en) | 2001-08-02 |
| AU2001233119A1 (en) | 2001-08-07 |
| JP2003521072A (en) | 2003-07-08 |
| GB0217126D0 (en) | 2002-09-04 |
| KR20030004327A (en) | 2003-01-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20170129 |