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GB2367652B - Scheduling control within a system having mixed hardware and software based instruction execution - Google Patents

Scheduling control within a system having mixed hardware and software based instruction execution

Info

Publication number
GB2367652B
GB2367652B GB0024399A GB0024399A GB2367652B GB 2367652 B GB2367652 B GB 2367652B GB 0024399 A GB0024399 A GB 0024399A GB 0024399 A GB0024399 A GB 0024399A GB 2367652 B GB2367652 B GB 2367652B
Authority
GB
United Kingdom
Prior art keywords
instruction execution
software based
scheduling control
based instruction
mixed hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB0024399A
Other versions
GB0024399D0 (en
GB2367652A (en
Inventor
Edward Colles Nevill
Andrew Christopher Rose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to GB0024399A priority Critical patent/GB2367652B/en
Priority to GB0028249A priority patent/GB2367658B/en
Publication of GB0024399D0 publication Critical patent/GB0024399D0/en
Priority to US09/731,060 priority patent/US20020069402A1/en
Priority to US09/887,561 priority patent/US7134119B2/en
Priority to JP2001259954A priority patent/JP4938187B2/en
Publication of GB2367652A publication Critical patent/GB2367652A/en
Application granted granted Critical
Publication of GB2367652B publication Critical patent/GB2367652B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Devices For Executing Special Programs (AREA)
GB0024399A 2000-10-05 2000-10-05 Scheduling control within a system having mixed hardware and software based instruction execution Expired - Lifetime GB2367652B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GB0024399A GB2367652B (en) 2000-10-05 2000-10-05 Scheduling control within a system having mixed hardware and software based instruction execution
GB0028249A GB2367658B (en) 2000-10-05 2000-11-20 Intercalling between native and non-native instruction sets
US09/731,060 US20020069402A1 (en) 2000-10-05 2000-12-07 Scheduling control within a system having mixed hardware and software based instruction execution
US09/887,561 US7134119B2 (en) 2000-10-05 2001-06-25 Intercalling between native and non-native instruction sets
JP2001259954A JP4938187B2 (en) 2000-10-05 2001-08-29 Cross-call between native and non-native instruction sets

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0024399A GB2367652B (en) 2000-10-05 2000-10-05 Scheduling control within a system having mixed hardware and software based instruction execution

Publications (3)

Publication Number Publication Date
GB0024399D0 GB0024399D0 (en) 2000-11-22
GB2367652A GB2367652A (en) 2002-04-10
GB2367652B true GB2367652B (en) 2004-08-11

Family

ID=9900735

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0024399A Expired - Lifetime GB2367652B (en) 2000-10-05 2000-10-05 Scheduling control within a system having mixed hardware and software based instruction execution

Country Status (1)

Country Link
GB (1) GB2367652B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7536682B2 (en) 2003-04-22 2009-05-19 International Business Machines Corporation Method and apparatus for performing interpreter optimizations during program code conversion
US7543284B2 (en) 2003-04-22 2009-06-02 Transitive Limited Partial dead code elimination optimizations for program code conversion
GB2400937B (en) * 2003-04-22 2005-05-18 Transitive Ltd Method and apparatus for performing interpreter optimizations during program code conversion

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953741A (en) * 1996-11-27 1999-09-14 Vlsi Technology, Inc. Stack cache for stack-based processor and method thereof
WO1999061982A1 (en) * 1998-05-26 1999-12-02 Advanced Micro Devices, Inc. Coprocessor support allowing non-native code to run in a system
EP1102164A2 (en) * 1999-11-22 2001-05-23 Nec Corporation Microprocessor system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953741A (en) * 1996-11-27 1999-09-14 Vlsi Technology, Inc. Stack cache for stack-based processor and method thereof
WO1999061982A1 (en) * 1998-05-26 1999-12-02 Advanced Micro Devices, Inc. Coprocessor support allowing non-native code to run in a system
EP1102164A2 (en) * 1999-11-22 2001-05-23 Nec Corporation Microprocessor system

Also Published As

Publication number Publication date
GB0024399D0 (en) 2000-11-22
GB2367652A (en) 2002-04-10

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20201004