[go: up one dir, main page]

AU2001273211A1 - Instruction fetch and dispatch in multithreaded system - Google Patents

Instruction fetch and dispatch in multithreaded system

Info

Publication number
AU2001273211A1
AU2001273211A1 AU2001273211A AU7321101A AU2001273211A1 AU 2001273211 A1 AU2001273211 A1 AU 2001273211A1 AU 2001273211 A AU2001273211 A AU 2001273211A AU 7321101 A AU7321101 A AU 7321101A AU 2001273211 A1 AU2001273211 A1 AU 2001273211A1
Authority
AU
Australia
Prior art keywords
dispatch
instruction fetch
multithreaded system
multithreaded
fetch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001273211A
Inventor
Enric Musoll
Mario D Nemirovsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Clearwater Networks Inc
Original Assignee
Clearwater Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/616,385 external-priority patent/US7035997B1/en
Application filed by Clearwater Networks Inc filed Critical Clearwater Networks Inc
Publication of AU2001273211A1 publication Critical patent/AU2001273211A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • G06F9/383Operand prefetching
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3804Instruction prefetching for branches, e.g. hedging, branch folding
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3844Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
AU2001273211A 2000-07-14 2001-07-05 Instruction fetch and dispatch in multithreaded system Abandoned AU2001273211A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09616385 2000-07-14
US09/616,385 US7035997B1 (en) 1998-12-16 2000-07-14 Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
PCT/US2001/021372 WO2002006959A1 (en) 2000-07-14 2001-07-05 Instruction fetch and dispatch in multithreaded system

Publications (1)

Publication Number Publication Date
AU2001273211A1 true AU2001273211A1 (en) 2002-01-30

Family

ID=24469213

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001273211A Abandoned AU2001273211A1 (en) 2000-07-14 2001-07-05 Instruction fetch and dispatch in multithreaded system

Country Status (6)

Country Link
US (1) US7707391B2 (en)
EP (1) EP1311947B1 (en)
JP (1) JP2004518183A (en)
AU (1) AU2001273211A1 (en)
DE (1) DE60143896D1 (en)
WO (1) WO2002006959A1 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7257814B1 (en) * 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7020879B1 (en) * 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US6389449B1 (en) * 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7310722B2 (en) * 2003-12-18 2007-12-18 Nvidia Corporation Across-thread out of order instruction dispatch in a multithreaded graphics processor
GB0519597D0 (en) * 2005-09-26 2005-11-02 Imagination Tech Ltd Scalable multi-threaded media processing architecture
GB2457341B (en) * 2008-02-14 2010-07-21 Transitive Ltd Multiprocessor computing system with multi-mode memory consistency protection
US8443176B2 (en) * 2008-02-25 2013-05-14 International Business Machines Corporation Method, system, and computer program product for reducing cache memory pollution
US8640133B2 (en) * 2008-12-19 2014-01-28 International Business Machines Corporation Equal duration and equal fetch operations sub-context switch interval based fetch operation scheduling utilizing fetch error rate based logic for switching between plurality of sorting algorithms
US10007523B2 (en) * 2011-05-02 2018-06-26 International Business Machines Corporation Predicting cache misses using data access behavior and instruction address
JP5861354B2 (en) * 2011-09-22 2016-02-16 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
US9182991B2 (en) * 2012-02-06 2015-11-10 International Business Machines Corporation Multi-threaded processor instruction balancing through instruction uncertainty
JP2014038408A (en) * 2012-08-13 2014-02-27 International Business Maschines Corporation Stole reduction methods on pipeline of processor with simultaneous multi-threading capability, reduction device and reduction program
US9619230B2 (en) * 2013-06-28 2017-04-11 International Business Machines Corporation Predictive fetching and decoding for selected instructions
US9652418B2 (en) 2014-06-30 2017-05-16 Intel Corporation High throughput register file memory with pipeline of combinational logic
USRE50518E1 (en) 2016-03-24 2025-08-05 Samsung Electronics Co., Ltd. Method and device for controlling memory
US10482033B2 (en) 2016-03-24 2019-11-19 Samsung Electronics Co., Ltd Method and device for controlling memory
US12360771B2 (en) * 2021-04-27 2025-07-15 Red Hat, Inc. Rescheduling a load instruction based on past replays
US12288075B1 (en) * 2024-02-23 2025-04-29 International Business Machines Corporation Instruction execution scheduling using a hit/miss predictor

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4197579A (en) 1978-06-06 1980-04-08 Xebec Systems Incorporated Multi-processor for simultaneously executing a plurality of programs in a time-interlaced manner
JPS63254530A (en) 1987-04-10 1988-10-21 Nec Corp Information processor
US5321823A (en) 1988-07-20 1994-06-14 Digital Equipment Corporation Digital processor with bit mask for counting registers for fast register saves
JPH0748179B2 (en) 1988-10-12 1995-05-24 日本電気株式会社 Data processing device
US5142676A (en) 1988-12-28 1992-08-25 Gte Laboratories Incorporated Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory
JPH02190930A (en) 1988-12-29 1990-07-26 Internatl Business Mach Corp <Ibm> Software instruction executing apparatus
US5093777A (en) 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
GB2234613B (en) 1989-08-03 1993-07-07 Sun Microsystems Inc Method and apparatus for switching context of state elements in a microprocessor
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
JP2616182B2 (en) 1990-08-29 1997-06-04 三菱電機株式会社 Data processing device
JP2845646B2 (en) * 1990-09-05 1999-01-13 株式会社東芝 Parallel processing unit
JPH04335431A (en) 1991-05-13 1992-11-24 Nec Corp Information processor
US5309173A (en) 1991-06-28 1994-05-03 Texas Instruments Incorporated Frame buffer, systems and methods
JP2611065B2 (en) 1991-08-19 1997-05-21 三菱電機株式会社 Data transfer method
US5546593A (en) 1992-05-18 1996-08-13 Matsushita Electric Industrial Co., Ltd. Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream
JP2665111B2 (en) 1992-06-18 1997-10-22 日本電気株式会社 Vector processing equipment
WO1994027216A1 (en) 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
FR2705804B1 (en) 1993-05-27 1995-08-11 Sgs Thomson Microelectronics Multi-tasking processor architecture.
US5454117A (en) * 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
US5535365A (en) 1993-10-22 1996-07-09 Cray Research, Inc. Method and apparatus for locking shared memory locations in multiprocessing systems
US5572704A (en) 1993-12-15 1996-11-05 Silicon Graphics, Inc. System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes
US5604877A (en) 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for resolving return from subroutine instructions in a computer processor
US5745778A (en) 1994-01-26 1998-04-28 Data General Corporation Apparatus and method for improved CPU affinity in a multiprocessor system
US5509123A (en) 1994-03-22 1996-04-16 Cabletron Systems, Inc. Distributed autonomous object architectures for network layer routing
US5542088A (en) 1994-04-29 1996-07-30 Intergraph Corporation Method and apparatus for enabling control of task execution
US5758142A (en) 1994-05-31 1998-05-26 Digital Equipment Corporation Trainable apparatus for predicting instruction outcomes in pipelined processors
US5649144A (en) 1994-06-13 1997-07-15 Hewlett-Packard Co. Apparatus, systems and methods for improving data cache hit rates
JP2677202B2 (en) 1994-08-12 1997-11-17 日本電気株式会社 Microprocessor
US5812811A (en) 1995-02-03 1998-09-22 International Business Machines Corporation Executing speculative parallel instructions threads with forking and inter-thread communication
JP3494736B2 (en) * 1995-02-27 2004-02-09 株式会社ルネサステクノロジ Branch prediction system using branch destination buffer
US5748468A (en) 1995-05-04 1998-05-05 Microsoft Corporation Prioritized co-processor resource manager and method
US5784613A (en) 1995-09-12 1998-07-21 International Busines Machines Corporation Exception support mechanism for a threads-based operating system
JP2889845B2 (en) 1995-09-22 1999-05-10 松下電器産業株式会社 Information processing device
US5701432A (en) 1995-10-13 1997-12-23 Sun Microsystems, Inc. Multi-threaded processing system having a cache that is commonly accessible to each thread
US6115802A (en) 1995-10-13 2000-09-05 Sun Mircrosystems, Inc. Efficient hash table for use in multi-threaded environments
US5852726A (en) 1995-12-19 1998-12-22 Intel Corporation Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner
US5815733A (en) 1996-02-01 1998-09-29 Apple Computer, Inc. System for handling interrupts in a computer system using asic reset input line coupled to set of status circuits for presetting values in the status circuits
US5867725A (en) 1996-03-21 1999-02-02 International Business Machines Corporation Concurrent multitasking in a uniprocessor
US5826081A (en) 1996-05-06 1998-10-20 Sun Microsystems, Inc. Real time thread dispatcher for multiprocessor applications
JPH1011301A (en) 1996-06-25 1998-01-16 Masaharu Imai Multitask processing device and multitask processing control method
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5933627A (en) 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
JP3760035B2 (en) 1996-08-27 2006-03-29 松下電器産業株式会社 Multi-thread processor that processes multiple instruction streams independently and flexibly controls processing performance in units of instruction streams
CN1280714C (en) 1996-08-27 2006-10-18 松下电器产业株式会社 Multi-threaded processor that processes multiple instruction streams independently and softly controls the processing functions of each instruction stream
US5913054A (en) 1996-12-16 1999-06-15 International Business Machines Corporation Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle
US6029228A (en) * 1996-12-31 2000-02-22 Texas Instruments Incorporated Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions
JP3605978B2 (en) 1997-01-17 2004-12-22 松下電器産業株式会社 Microcomputer
US5835705A (en) 1997-03-11 1998-11-10 International Business Machines Corporation Method and system for performance per-thread monitoring in a multithreaded processor
US5946711A (en) 1997-05-30 1999-08-31 Oracle Corporation System for locking data in a shared cache
US5913049A (en) 1997-07-31 1999-06-15 Texas Instruments Incorporated Multi-stream complex instruction set microprocessor
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6076157A (en) * 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6260077B1 (en) 1997-10-24 2001-07-10 Sun Microsystems, Inc. Method, apparatus and program product for interfacing a multi-threaded, client-based API to a single-threaded, server-based API
US6061710A (en) * 1997-10-29 2000-05-09 International Business Machines Corporation Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
US5987492A (en) 1997-10-31 1999-11-16 Sun Microsystems, Inc. Method and apparatus for processor sharing
US6079003A (en) * 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
US6018759A (en) 1997-12-22 2000-01-25 International Business Machines Corporation Thread switch tuning tool for optimal performance in a computer processor
US6016542A (en) 1997-12-31 2000-01-18 Intel Corporation Detecting long latency pipeline stalls for thread switching
US6308261B1 (en) 1998-01-30 2001-10-23 Hewlett-Packard Company Computer system having an instruction for probing memory latency
US6430593B1 (en) 1998-03-10 2002-08-06 Motorola Inc. Method, device and article of manufacture for efficient task scheduling in a multi-tasking preemptive priority-based real-time operating system
US6356996B1 (en) 1998-03-24 2002-03-12 Novell, Inc. Cache fencing for interpretive environments
GB9809022D0 (en) 1998-04-29 1998-06-24 Int Computers Ltd Semaphore for a computer system
US6260138B1 (en) * 1998-07-17 2001-07-10 Sun Microsystems, Inc. Method and apparatus for branch instruction processing in a processor
US6119203A (en) 1998-08-03 2000-09-12 Motorola, Inc. Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system
US6567849B2 (en) 1998-08-17 2003-05-20 International Business Machines Corporation System and method for configuring and administering multiple instances of web servers
US6493749B2 (en) 1998-08-17 2002-12-10 International Business Machines Corporation System and method for an administration server
US6792524B1 (en) * 1998-08-20 2004-09-14 International Business Machines Corporation System and method cancelling a speculative branch
US6192384B1 (en) 1998-09-14 2001-02-20 The Board Of Trustees Of The Leland Stanford Junior University System and method for performing compound vector operations
SE9803632D0 (en) 1998-10-22 1998-10-22 Ericsson Telefon Ab L M A processor
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US6292888B1 (en) 1999-01-27 2001-09-18 Clearwater Networks, Inc. Register transfer unit for electronic processor
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US6477562B2 (en) 1998-12-16 2002-11-05 Clearwater Networks, Inc. Prioritized instruction scheduling for multi-streaming processors
US7237093B1 (en) 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
US6389449B1 (en) 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US7035997B1 (en) 1998-12-16 2006-04-25 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US6272624B1 (en) * 1999-04-02 2001-08-07 Compaq Computer Corporation Method and apparatus for predicting multiple conditional branches
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6442675B1 (en) 1999-07-29 2002-08-27 International Business Machines Corporation Compressed string and multiple generation engine
US6487571B1 (en) 1999-10-07 2002-11-26 International Business Machines Corporation Method and system for generating actual random numbers within a multiprocessor system
US6502185B1 (en) * 2000-01-03 2002-12-31 Advanced Micro Devices, Inc. Pipeline elements which verify predecode information
JP4335431B2 (en) 2000-12-07 2009-09-30 株式会社小森コーポレーション Paper feeder
US6976155B2 (en) 2001-06-12 2005-12-13 Intel Corporation Method and apparatus for communicating between processing entities in a multi-processor

Also Published As

Publication number Publication date
EP1311947A4 (en) 2008-02-27
DE60143896D1 (en) 2011-03-03
EP1311947A1 (en) 2003-05-21
WO2002006959A1 (en) 2002-01-24
US7707391B2 (en) 2010-04-27
US20070143580A1 (en) 2007-06-21
JP2004518183A (en) 2004-06-17
EP1311947B1 (en) 2011-01-19

Similar Documents

Publication Publication Date Title
AU2001273211A1 (en) Instruction fetch and dispatch in multithreaded system
AU2002223824A1 (en) Instruction processor systems and methods
AU2001239931A1 (en) Load management dispatch system and methods
GB2365185A8 (en) Systems and methods for trading
AU2001286956A1 (en) Software development systems and methods
AU2001294922A1 (en) Automated bioculture and bioculture experiments system
SG101932A1 (en) Three dimensional animation system and method
GB0022444D0 (en) Positioning system and method
AU2002243531A1 (en) Mram architecture and system
AU2001259525A1 (en) Location based messaging method and system
AU2001227797A1 (en) Method and system for interacting with a display
AU2001253403A1 (en) Computer-based interpretation and location system
AU2001249353A1 (en) Price charting system and technique
AU2001272788A1 (en) Parallel z-buffer architecture and transparency
AU2002212605A1 (en) Trading system and method
SG100690A1 (en) Coating and developing system
AU2002213227A1 (en) Generalizer system and method
AU2002211257A1 (en) Fetch and dispatch decoupling mechanism for multistreaming processors
AU2852901A (en) Interleaving method and system
AU2001296604A1 (en) Simd system and method
GB0124973D0 (en) Text processing and display methods and systems
AU6368401A (en) Method and system for call holding with call back
GB9907687D0 (en) Assays methods and means
AU1132902A (en) Reverse auction method and system
GB0019500D0 (en) System and method