GB2354881A

GB2354881A - Plural integrated circuit packaging structure

Info

Publication number: GB2354881A
Application number: GB0015843A
Authority: GB
Inventors: Ming-Tung Shen
Original assignee: CTS COMP TECHNOLOGY SYSTEM COR; CTS Computer Tech System Corp
Current assignee: CTS COMP TECHNOLOGY SYSTEM COR; CTS Computer Tech System Corp
Priority date: 1999-06-28
Filing date: 2000-06-28
Publication date: 2001-04-04
Anticipated expiration: 2020-06-28
Also published as: GB9915076D0; GB2354881B; GB0015843D0

Abstract

An plural integrated memory circuit structure which can accommodate two or four memory chips 2c and 2e in an aperture formed in an upper circuit board 3a mounted upon a lower circuit board 4a, with connecting wires 6a protected by encapsulation 5a and 5b. The packaging structure has circuitry which forms independent data buses for each memory chip while implementing the address buses and control buses in parallel. Two memory chips may be mounted adjacent and four may be mounted adjacent and stacked (as depicted). Stacked memory chips may be mounted back to back by an adhesive tape.

Description

2354881 integrated Circuit Packaging Structure

BACKGROUND OF TM INVENTTON 1. Field Of The Invention

The invention relates to an integrated circuit packaging structure and, in particular, to a packaging structure that can double the capacity of the memory without increasing the size of the package and the number of pins.

2. Description Of The Prior Art

Memory plays a very important role in the computer mechanism. Accompanying the increasing speed of the central process unit (CPU), the memory has been prosperously developed so that, in recent years, it has overwhelmed the Moore rule, which states that the capacity will increase by a factor of four every two or three years. The capacity has rapidly evolved from 16MB, 64MB, 128MB to 256MB and is still evolving toward higher capacity.

The memory is also modularized in accord with the need of the computer industry. A usual 64M[B SDRAM module known in the prior art is composed by eight memory integrated circuits (IC), and every memory IC with 54 pins has only one memory chip. Therefore, it is indeed a waste that there is only placed on little chip in such a big package.

In observation of the disadvantages in the memory packaging structure according to the prior art that awaits for improvement, the inventor then made efforts in modifying and refining and finally succeeded in the invention of this integrated circuit packaging structure after many years of research and hard-working.

SUMMARY OF THE INVENTION

The present invention provides an integrated circuit packaging structure, which has independent implementation for the data buses among chips and parallel implementation for the address buses and control buses, and then encapsulates them into one package so as to double the capacity of the memory.

Furthermore, the instant invention provides an integrated circuit packaging structure, by which the efficiency of a memory IC can be effectively promoted and the inner space of the package can be more effectively utilized.

Yet, the invention provides an integrated circuit packaging structure, via which the capacity of the memory can be rapidly doubled and modularized, and can speed up the development of the memory industry.

The integrated circuit packaging structure with the above mentioned merits imbeds two or four memory chips into the concave structure formed by the upper and lower circuit boards, has independent data buses for each memory chip while makes address buses and control buses work in parallel, and finally encapsulates them within a single package in the expectation of enlarging the memory capacity without increasing the size of the package and the number of pins.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings disclose an illustrative embodiment of the present invention which serves to exemplify the various advantages and objects hereof, and are as follows:

Fig. I(A) is an embodiment of packaging two memory chips into a package according to the present invention; Fig. I (B) is an A-A cross-sectional view of Fig. I (A); Fig. 2 is a circuit of packaging two memory chips into a package according to the present invention; 2 Fig. 3(A) is an embodiment of packaging four memory chips into a package according to the present invention; Fig. 3(B) is an A-A cross-sectional view of Fig. 3(A); Fig. 4 is a circuit of packaging four memory chips into a package according to the present invention.

Main Symbols 1 package 1 a package 2a memory chip 2b memory chip 2c memory chip 2d memory chip 2e memory chip 2f memory chip 21 welding pad 21 a welding pad 21b welding pad 3 upper circuit board 3 a upper circuit board 31 groove 3 1 a groove 32 welding pad 4 lower circuit board 4a lower circuit board 41 aperture 41 a aperture 42 welding pad 42a welding pad 5 colloidal protection layer 5a. colloidal protection layer 5b colloidal protection layer 6 connecting wire 6a connecting wire 7 punching 7a punching 8 double-sided tape DETAILED DESCRIPTION OF THE PREFERRED EMBODEWENT

Please refer to Fig. I(A), which is an embodiment of packaging two memory chips into a package according to the present invention. According to the diagram, two memory chips 2a, 2b are encapsulated within a package 1, and, by placing the memory chips 2a, 2b in parallel, the memory capacity doubles without enlarging the volume of the package 1.

Please refer to Fig. I(B), which is an A-A cross-sectional view of Fig. I(A). This diagram shows the embodiment structure of the instant invention, wherein the memory chip 2a is embedded in the groove 31 formed by the upper circuit board 3 and the lower circuit board 4.

3 The welding pad 21 ofi the memory chip 2a and the welding pad 42 on the lower circuit board 4 can be connected by the bonding technique. Applying a colloidal protection layer (such as epoxy) may protect the inner connecting wire6 and memory chip 2a. Punching 7 processes between the upper and lower circuit boards 3, 4 can make help connecting the circuits on the upper and lower circuit boards 3, 4, which is convenient for the S. M.T. process. The invention can effectively double the memory capacity via this structure.

Please refer to Fig. 2, which is a circuit of packaging two memory chips into a package according to the present invention. The diagram shows that the memory chip 2a and memory chip 2b are encapsulated within the package 1, wherein the data bus (DQO-DQ7) on the package I is composed by the data bus (DQO-DQ3) on the memory chip 2a and the data bus (DQO-DQ3) on the memory chip 2b independently; while the address bus (AO-Al 1, BAO, BAI) and control bus (CS, WE, EA-S, RAS, CLK CKE, DQM) on the package I are implemented by combining the address bus (AO-Al 1, BAO, BAI) and control bus (CS, WE, CAS, RAS, CLK, CKE, DQM) in parallel. Applying this circuit to the packaging structure described in Fig. I(B) can make a memory IC with doubled memory capacity.

Please refer to Fig. 3(A), which is an embodiment of packaging four memory chips into a package according to the present invention. The most difference between this diagram and Fig. I(A) is to encapsulate four memory chips 2a, 2b, 2c, and 2d into a package Ia, and, by putting the memory chips 2a, 2b, 2c, and 2d in parallel and in stack, the memory capacity can be increased by a factor of four without enlarging the volume of the package Ia.

Please refer to Fig. 3(B), which is an A-A cross-sectional view of Fig. 3(A). According to the diagram, the backs of the upper and lower memory chips 2e, 2c are glued together by the double-sided tape 8, and are, stacked as double layers, embedded into the groove 3 Ia formed by the upper circuit board 3a and the lower circuit board 4a. The welding pad 21a on the upper memory chip 2e and the welding pad 32 on the upper circuit board 3a are connected via the bonding technique, while the welding pad 21b on the lower memory chip 2c may be exposed in the aperture 4 1 a on the lower circuit board 4a, and the welding pad 2 1 b on the lower memory chip 2c and the welding pad 42a on the lower circuit board 4a may be connected via the bonding technique too. Applying colloidal protection layers 5a, 5b (such as epoxy) on both ends of the bonded elements can protect the inner connecting wire 6a and the memory chips 2e, 2c. Punching 7a processes between the upper and lower circuit boards 4a, 4b help connecting the circuits on the upper and lower circuit boards 4a, 4b, which in turn is convenient for the S.M.T. process. This invention can effectively increase the memory capacity by a factor of four with the help of this structure.

Please refer to Fig. 4, which is a circuit of packaging four memory chips into a package according to the present invention. The diagram demonstrates that the memory chips 2c, 2d, 2e, and 2f are encapsulated into a package Ia with 54 pins, wherein the data bus (DQO-DQ15) on the package I a are composed by the data bus (DQ)-DQ3) on each of the memory chips 2a, 2b, 2c, and 2d independently, while the address bus (AO-AI 1, BAO, BAI) and control bus (CS, WE, CAS, RAS, CLK, CKE, LDQK UDQM) on the package Ia are implemented by putting the address bus (AO-Al 1, BAO, BAI) and control bus (CS, WE, Z_AS, -RAS, CLIC, CKE, DQM) on each of the memory chips 2a, 2b, 2c, and 2d in parallel. Applying this circuit feature to the packaging structure described in Fig. 30B) can produce a memory IC with four times of memory capacity.

The integrated circuit packaging structure provided by the instant invention, when compared with the prior art, has the following merits:

4 1. the integrated circuit packaging structure according to the invention can encapsulated two memory chips into a single package and thus enlarges the memory capacity by a factor of two or four without increasing the size of the package and the number of pins; 2. the integrated circuit packaging structure according to the invention can effectively promote the efficiency of a memory IC, and can make good use of the inner space of the package; and 3. the integrated circuit packaging structure according to the invention can effectively double and modularize the memory, which can stimulate rapid development in memory industry.

Many changes and modifications in the above described embodiment of the invention can, of course, be carried out without departing from the scope thereof Accordingly, to promote the progress in science and the useful arts, the invention is disclosed and is intended to be limited only by the scope of the appended claims.

Claims

1. An integrated circuit packaging structure comprising at least two dice (2a), each dice having an address bus and a control bus, the address bus of one of the dice being electrically connected to the address bus of another one of the dice, the control bus of one of the dice being electrically connected to the control bus of another one of the dice, wherein the integrated circuit packaging structure further comprises a printed circuit board unit (4) having a top surface and a bottom surface, the top surface being formed with a plurality of electrical traces and plurality of bonding pads (42, 42a), each bonding pad being electrically connected to a corresponding one of the electrical traces, and having an aperture (41,41 a) formed therethrough; and wherein each of the dice has an upper surface on which are formed a plurality of bonding pads (21, 21b), the upper surface of each dice being attached to the bottom surface of the printed circuit board unit such that the bonding pads of the dice are registered with the aperture; and wherein a plurality of conductive wires (6, 6a) interconnect the bonding pads of the dice and the bonding pads of the printed circuit board unit through the aperture.

2. An integrated circuit packaging structure as claimed in claim 1, comprising an encapsulation layer (3) formed on the bottom surface of the printed circuit board unit around the dice.

3. An integrated circuit packaging structure as claimed in claim 1, wherein the printed circuit board unit comprises superimposed upper and lower printed circuit boards (3a, 4a), the upper printed circuit board (4a) having a top surface which serves as the top surface of the printed circuit board unit, and a bottom surface, the lower printed circuit board (3a) having a top surface attached to the bottom surface of the upper printed circuit board, a bottom surface on which a plurality of bonding pads (32) are provided, and a hole formed therethrough, the lower printed circuit board further having an inner peripheral wall which confines the hole, the inner peripheral wall of the lower printed circuit and the bottom surface of the upper printed circuit board 6 cooperatively defining therebetween a die-receiving cavity in which the dice (2c) are received, the integrated circuit packaging structure further comprising:

at least two second dice (2e), each of which is received in the diereceiving cavity and having a bottom surface attached to a bottom surface of a corresponding one of the first dice (2c), each of the second dice further having a top surface on which a plurality of bonding pads (2 1 a) are mounted; and a plurality of second conductive wires (6a) interconnecting the bonding pads of the second dice and the bonding pads of the lower printed circuit board.

4. An integrated circuit packaging structure, which has the feature of increasing the memory capacity by embedding a memory chip into a concave structure formed by an upper circuit board and a lower circuit board, by implementing the data buses among each memory chip independently while putting the address buses and the control buses in parallel, and by encapsulating the elements into a single package.

5. An integrated circuit packaging structure as claimed in claim 4, wherein the concave structure can take the form of parallel grooves so that two memory chips can be allocated to double the memory capacity.

6. An integrated circuit packaging structure as claimed in claim 4, wherein four memory chips can be deployed into the concave structure in parallel and in stack to increase the memory capacity by a factor of four.

7. An integrated circuit packaging structure as claimed in claim 5, wherein the memory chips in stack are implemented by gluing the backs of the two memory chips together by a double-sided tape.

8. An integrated circuit packaging structure as substantially hereinbefore described with reference to the accompanying figures.