GB2200774A - Timing generators - Google Patents

Description

1 -1 !Z A ' "' 0 0 7 74+ 2.1_ 1 TIMING GENE1RATOR.

The invention relates-to generating timing signals.

Stable clocks such as crys'tal oscillators have been used to generate a sequence of timing signalsof variable signal-to-signal interval by programming digital counters to trigger the timing signals at predetermined counts of the clock. -Although tapped delpy lines having resolution (e.g., I nanosecond) higher than that (e.g., 16 ns) of the clock have been used to additionally delay signals relative to the-start of the sequence, timing signal interval resolution has in such systems been limited by the clock resolution, with the timing signal period equal to the cryst al oscillator period or an integer multiple thereof.

In St. Clair U.S. Patent No. 4,231,104, desired period values that were not even multiples of the crystal period were obtained by dividing the desired period into a number of crystal periods plus a remainder and a residue value which was added by a-delay line. The remainder was simply the remainder of dividing the desired period by the crystal period (e.g., 2 ns remainder for dividing a 50 ns desired period by a 16 ns clock period). The residue values accounted for the fact that subsequent output pulses were not beginning at a clock signal. (E.g., if the first 50 ns period output appears 2 ns after a clock signal, the next output will have this R ns residue in addition to the 2 ns remainder, and will appear 4 ns after a 1 2 1 clock signal, in order to be 50 ns after the preceding output.) A plurality of timing edge generators, employing further delay lines, were driven by these desired period output pulses plus delayed clock signals, obtained by passing clock signals through a delay line delayed by the residue value. The circuitry employing the timing edge generators thus had both the crystal clock signals and asychronous-delayed clock signals distributed through it.

In some other timing signal generators, desired periods that are other than integer multiples of a crystal oscillator period are provided by splitting the clock signals into plural pliases, and programmably selecting signals from a particular phase to trigger an output (e.g., a 4 ns clock split into four phases to obtain ns resolution).

In accordance with the present invention, there is provided apparatus for providing a plurality of synchronous timing signals having period values that are not even multiples of a clock period, the apparatus comprising: a clock adapted for operatively generating clock signals separated in time by a clock period; a plurality of local edge generators arranged operatively to receive said clock signals, each said local edge generator including local programmable counting means adapted to provide local. outputs upon receiving 1 3 1 predetermined clock signals; and local programmable delay means adapted operatively to provide a timing signal after a delay interval following each said local output, the resolution of said local delay means being greater than that of said clock.

In preferred embodiments of our apparatus, we have found that, by distributing crystal clock signals directly to local timing edge generators and selecting a desired clock signal and adding the residue and remainder delay (to come up with pulses having periods other than integer multiples of the clock period) in the edge generators near the final pulse used for edge generation, using local programmable counting and delay means, important advantages are obtainable. In specific embodiments, the timing system is synchronous (promoting simplicity of manufacture and reliable operation); transmission line inaccuracies do not contribute to timing inaccuracies; there is relatively reduced crosstalk (owing to the need to distribute only one crystal phase), and there are only a relatively small number of gates (which tend to distort signals) between the clock signal and the final timing signal, yielding improved accuracy.

C r; i 11 4 In preferred embodiments the local programmable counting means includes a local counter and a coincidence detector that receives the output of the local counter plus output of a first random icCess memory (RAM) including the most significant bits of the desired period value (i.e., the integer number of clock periods in a desired period); a local end-of-count (LEOC) output is provided at a predetermined count to a flip flop that is triggered upon the'next clock signal in order to select a desired clock signal, and that output is provided to the local programmable delay means that adds the residue and remainder values; the programmable delay means includes a delay line that is controlled with a residue and remainder value provided from an adder that obtains the remainder value (also referred to as the least significant bits) from a second RAM and adds to it the re'sidue of the prior output, both RAMs being addressed by the same address bus; there is a master counter that counts clock signals and provides master end-of-count (MEOC) pulses to reset the local counters; there also are master RAMs that include the most signific.ant bits and remainder values for the desired period and adders that are used to calculate the residue value and distribute it to the local edge generators; and the local edge generators include adders which are used to add deskew values (used to account for differences in transmission paths to and through various edge Q5 r.

1, generators) to the residue and remainder values, the summation being used to provide the delay period in t1ae programmable delay line. A preferred application for embodiments of apparatus in accordance with the invention is in automatic circuit testing equipment in which test patterns are provided to a large number of input nodes of a circuit under test at high speed.

The invention is hereinafter more particularly described by way of example only with reference to the accompanying drawings, in which:

Fig. 1 is a block diagram of a period oscillator circuit used to provide'master end-of-count pulses and residue values to a plurality of local edge generators in a preferred embodiment of apparatus in accordance with the present invention; and Fig. 2 is a block diagram of a local edge generator using clock signals and the master end-of-count pulses and residue values of the Fig. 1 circuit to generate a timing edge pulse.

Referring to the figures, in Fig. 1 is shown master period oscillator 10, which receives as inputs the clock signals (XTAL) from 6.4 nanosecond crystal oscillator 12 and 8-bit time set addresses (for stored desired period values) and provides outputs used by the plurality of local edge generators 16, one of which is shown in Fig. 2. The timing circuitry shown in the figures is used in an automatic circuit tester in which test 6 patterns are provided to a large number of input nodes of a circuit under test at high speed and the resulting outputs are detected and compared with expected output.

Referring to Fig. 1, period oscillator 10 includes presetable 10-bit master counter 18 and MSB period value random access memory (RAM) 20 (10bit by 256-bit), the outputs of both of which are provided for c6mparison at coincidence detector 22 (plural exclusive or gates, the outputs of which are combined by or gates), to provide an output to flip flop 24 when the count at counter 18 matches the period value at the output of RAM 20. MSB RAM 20 is addressed by addresses provided over 8-bit time set address bus 19 from address register 14. Flip flop 24 is clocked by XTAL signals and provides its output to crystal delay 26, which is also clocked by XTAL signals and can delay its output by 1 XTAL signal when it receives a carry out signal on its delay input 28 from 6-bit residue adder 30. Time set address bus 19 is also provided to LSB period value RAM 22 (6 bit by 256 bit) and provides its output +to Che B input of residue adder 30.. The 6-bit, S summation output, designated RES(n), of residue adder 30 is connected to the input of register 33, which provides its 6-bit output, designated AES(n-1), to local edge generators 16 and to the A input of residue adder 30. The S summation output of residue adder 30-is also provided to programmable delay line 34, which provides an output period pulse each time it receives a master end-of-count (MEOC) pulse from crystal delay 26, after delaying it a delay interval indicated by RES(n). Programmable delay line 34 is a 4 1 1 f 1; 7 digital interpolator that has 100 ps resolution and can provide delays up to 6.4 ns. The MEOC output of crystal delay 26 is also provided to reset master counter 18 and to clock address register address 14.

Referring to Fig. 2, local edge generator 16 includes presetable 10-bit local counter 36, which is reset by MEOC pulses, clocked by XTAL sigfials, and provides its 10-bit output to coincidence detector 38, which also receives as an input the output of MSB time value RAM 40 (10-bit by 256bit). The output of coincidence detector is provided to flip flop 42, which is clocked by XTAL signals and provides'its output to crystal delay 44, which is also clocked by XTAL signals. Crystal delay 44 includes two delay inputs 46, 48, each of which is capable of delaying the local endof-count (LEOC) output of crystal delay 44 to programmable delay line 50 by 1 XTAL signal. Delay input 46 is connected to receive a carry out signal from 6-bit residue adder 53, and delay input 48 is connected to receive a carry out signal from 6-bit delay adder 54. WB'Mme"value RAM 52, (6-bit by 256-bit) is also addressed by time set address bus 19 and provides its output, designated REM(TV(n)/XTAL), to the A input of residue adder 53. The B input of residue adder 53 receives the RES(n-1) output from master period oscillator 10, and the 6-bit S summation output of residue adder 53 is provided to the 'A input of delay adder 44. The B input of adder 54 receives a deskew value, DES, from deskew value generator 56 in order to deskeW the edge provided by edge generator 16 so that it is.synchronous with edges provided by edge generators for other 4 1 8 channels. Generator 56 is reset by MEOC and receives control signals, CNTRL, indicating a deskew value to be used. The 6-bit S summation output (designated DELAY(n)) of delay adder 54 is provided by programmable delay line 50, which is a digital interpolator having 100 ps resolution and provides an output pulse each time it receives a pulse from crystal delay 44, after delaying it a delay interval indicated by the value of DELAY(n).

Claims (1)

1. In operation, period oscillator 10 provides period pulses having

   programmed period values fo cycle n, PV(n), that are other than integer multiples of the crystal period, similar to the operation described in St. Clair U.S. Patent No. 4,231j104. However, the residue value is not used to delay crystal signals, to which are added further delays in the.edge generators, as in St.. Clair; instead the crystal signals, the residue value, and the digital master end-of-count signal are sent to all of the local edge generators 16, in which all delay is added to the crystal signal at once.

   Ref erring to Fig. 1, the integer values (designated INT(PV(n)/XTAL) in Fig. 1), of dividing PV(n) bS, the crystal period (XTAL) are loaded into MSB period value RAM 20, and the remainder values (in 100 ps increments)'of this division (designated REM(PV(n)/XTAL) in Fig. 1) are loaded into LSB period value RAM 32. PV(n) can range from 19.2 ns (a minimum of three crystal periods are needed to accommodate routing through the circuitry to perform calculations) to 6.5 microseconds 1 4 t 9 i 1 (210 crystal periods) and is one of.the 256 values stored in RAM's 20,-32. The period value, PV(n),Is.thus a summation of the integer values loaded in RAM 20 (in clock period units), and the remainder values loaded into RAM 32 (in 100 ps units). Master counter 18 counts XTAL signals and provides its output to coincidence detector 22, which provides a pulse to flip flop 24 when the count on counter 18 equals the integer values provided by MSB RAM 20.- This is pro vided to flip flop 24, which on the next XTAL signal provides a pulse to crystal delay 26, which on the next XTAL signal (unless delayed by a carry out at input delay 28) provides an MEOC pulse, which resets counter 18 and clocks time set address register 14 to provide the next time set address to RAMs 20, 32. The remainder value provided from LSB RAM 32 to residue adder 30 is added to the value at input A and provided as a sum, RES(n), to delay line 34 and register 33. Time delay line 34 provides a period pulse each time it receives an MEOC pulse, after delaying it by the RES(n) value. Register 33, upon receiving an XTAL signal, prov1tes 'its output, designated RES(n-1), to indicate that it is one MEOC cycle behind the input to register 33. The RES(n) value provided by residue adder 30 to programmable delay 34 and tx3 register 33 has the value of the last 6 bits given by the following equation: RES(n) - RES(n-1) + REM(Mn)/XTAL) where:

   PV(n) Programmed Period value for cycle n, XTAL Crystal Period Value, REM(x/y) - remainder of dividing x by y, and A RES(n) = Residue for the nth cycle (RES(O)=O).

   Thus, if it is the beginning cycle, RES(n) simply equals the remainder value that was provided by LSB RAM 32. In subsequent cycles, RES(n) equals the summation of this value plus the residue value from the preceding cycle, fed back from the output of reg.1ster 33. In this manner period pulses with values PV(n) that are other than integer values of the period of oscillator 12 are provide by counting an integer number of clock signals to obtain an MEOC pulse and delaying the MEOC pulse by the remainder value in the first cycle and delaying the MEOC by the sum of the remainder and residue values in subsequent cycles, to account for the fa. c that the prior period pulse was not synchronous with a clock signal. Because the oscillator has a 6.4 ns period, and programmable delay 34 adds delays in increments of 100 ps, when residue adder 30 has counted to 64, it will overflow and provide a carry out, and the MEOC will once again be synchronous with the crystal signal, so a one- crystal-signal delay is provided at crystal delay 26. The period pulse is used by a pattern genethor"(not shown) to send the next cycle's data to be formatted.

   Referring to Fig. 2, edge generator 16 receives MEOC pulses, XTAL signals, addresses on time set address bus 19, and the RES(n-1) residue values from period oscillator 10. The MEOC pulses reset Counter 36, which counts XTAL signals and provides its output to coincidence detector 38. The time value for edge generator 16 for cycle n, TV(n), is split up into some integer number of crystal periods (designated INT(TV(n)/XTAL)) plus a remainder value (designated REM(TV(n)/XTAL) in RAMs 40, 52, as 4 was the period value. When the value of the output of counter 36 matches the integer values in MSB time value RAM 40, a pulse is provided to flip flop 42, which provides a pulse to crystal delay 44 upon the next XTAL signal. The remainder value, REM(TV(n)/XTAL), is provided to the A input of 6-bit adder 53, which adds to this the residue value, RES(n-1), provided from oscillator 10. The 6-bit sfimmation of these values is then provided to delay adder 54,'which adds in any deskew value, DES, from deskew value generator 56. The summation of these values is then provided to programmable delay line 50. The delay value thus is determined by the last 6 bits of the number provided by the following equation:

   DELAY(n) = RES(n-1) + REM(TV(n)/XTAL) + DES d where: TV(n) = Programmed Time Value for cycle n, and DES - deskew for'local edge generator 16. As in period oscillator 10, crystal delay 44 provides its LEOC pulse to programmable delay 50, which idils eo it a delay interval, here DELAY(n). The two delay inputs 46, 48 are used when 6-bit adders 53, 54 overflow and &ovide carry outs. The output of programmable delay line 50 is a timing edge-pulse, which is used to generate an edge, used, e.g., with an edge from another local edge generator to provide a data pulse to a digital circuit being tested by automatic test equipment employing the timing signal generator. Thus the time value TV(n) may differ from the period values PV(n), depending upon, e.g., whether the time pulse is a beginning edge or an ending a 12 edge and the desired pulse width. The DES values provide deskew that varies depending upon the path to and through the generator, whether the edge is used for rising or falling edges and whether it is used in a driver or a detector.

   There are substantial advantages associated with providing pure crystal signals to local edge generators and adding all delays at once. 'The timing system is totally synchronous so that it is simple to manufacture and reliable in operation. only a pure crystal is fanned out to the system so that transmission line inaccuracies do not contribute to timing inaccuracies; residue and remainder delays are distributed and added in the digital domain. Because there is only one crystal phase, crosstalk is reduced. Deskewed values are easily added in the digital domain rather than the analog domain. There are an absolute minimum of gates between the pure crystal signal and the final timing-signals, yielding improved accuracy by avoiding having the ultimate timing signals based upon signals that have passed through a plurality of gates, e;A of which adds some distortion.

   Other arrangements are feasible; for example, the timing system has application in circuitry other than multiple-channel automatic circuit testers, in particular circuitry requiring precise timing edges that can be varied on a cycle-.by-cycle basis.

   9 -5 1 0 11 13 CLAIMS:

   ill Apparatus for providing a plurality of synch ronous timing signals having period values that are not even multiples of a clock period, the apparatus comprising: a clock adapted for operatively generating clock signals separated in time by a clock period; a plurality of local edge generators arranged operatively to receive said clock signals, each said local edge generator including local programmable counting means adapted to provide local outputs upon receiving predetermined clock signals; and local programmable delay means adapted operatively to provide a timing signal after a delay interval following each said local output, the resolution of said local delay means being greater than that of said clock.

   2. Apparatus according to Claim 1, wherein said local programmable counting means includes-a local counter adapted to count clock signals and a coincidence detector adapted to compare the output of the local counter with an integer number corresponding to a desired time value and to provide an output to a flip flop adapted to be triggered on the next clock signal.

   3. Apparatus according to Claim 2, wherein said local programmable counting means includes a first random access memory (RAM) loaded with integer numbers of clock periods in desired time values, and wherein the said integer number is operatively obtained from said first RAM.

   1 14 1 4. Apparatus according to Claim 3, wherein said local programmable delay means includes a delay line and a second RAM loaded with remainder values of dividing said desired time values by said clock period; and further comprising a common address bus connected to said first and second RAMs in all said_local generators., 5. Apparatus according to Claim 4, wherein said programmable delay means includes a first adder operatively adapted for adding residue values to said remainder values and for providing the sum to said delay line.

   6. Apparatus according to Claim 5, wherein said programmable delay means includes a second adder operatively adapted for adding a deskew value to the residue and remainder values and for providing the sum to the delay line.

   7. Apparatus according to Claim 6, wherein said deskew value is operatively provided by a deskew generator that can vary the deskew value on a cycle-by-cycle basis.

   8. Apparatus according to any preceding claim, wherein a master control circuit is provided which is adapted operatively to provide master end-ofcount pulses and residue values to the local edge generators.

   i j Apparatus according to Claim 8, wherein said master control circuit comprises a period oscillator including master programmable counting means adapted operatively to provide master end-of-count outputs upon receiving predetermined clock signals and master programmable delay means adapted operatively to provide a period output signal after a delay interval following each said master end-of-count output, the resolution of said master delay means being greater than that of said clock.

   10. For providing a plurality of synchronous timing signals having period values that are not even multiples of a clock period, apparatus substantially as herein before described with reference to and as shown in the accompanying drawings.

   r Published 1988 at The Patent Office, State House, 6671 High Holborn, London WCIR 4TP. Further copies may be obtaLlIeft IrOm The Patent Office. Sales Branch, St Mary Cray, Orpington, Kent BR5 3RD. Printed by Multiplex techniques ltd_ St me,17 Cray, Kent, Con, 1187.