GB2276033A

GB2276033A - Integrated circuit package

Info

Publication number: GB2276033A
Application number: GB9404559A
Authority: GB
Inventors: Peter Jones
Original assignee: British Aerospace PLC
Current assignee: BAE Systems PLC
Priority date: 1993-03-11
Filing date: 1994-03-09
Publication date: 1994-09-14
Anticipated expiration: 2014-03-09
Also published as: GB2276033B; GB9404559D0; GB9304956D0

Abstract

An integrated circuit package comprises a ceramic sub-package (1) a substrate (5) mounted on shoulders (4) therein, a lid (9) and connecting pins (10). The sub-package (1) and substrate carry a multiplicity of naked semi-conductor dies (2A, 2B, 2C, 6A, 6B, 6C) which are connected to one another and the subpackage (1) via wire bonds (3, 7, 8). If desired, further die-carrying substrates may be stacked within the sub-package (1) thus achieving a high packing density of semi-conductor dies in a single package. <IMAGE>

Description

INTEGRATED CIRCUITS This invention relates to integrated circuits and particularly to packaging for semi-conductor devices.

An integrated circuit package may be fabricated by arranging a multiplicity of bare semi-conductor dies on a series of flat substrates which are stacked one on top of the other. European Patent Application EP-A-478,426 (Figure 13) discloses a package incorporating stacked substrates, each substrate being populated, on one of it s faces by semiconductor dies. The stack is supported by a lower unpopulated substrate.

This known configuration has the disadvantages of poor mechanical rigidity and the need for tortuous electrical interconnections between dies.

This invention aims to provide an integrated circuit package which combines a high packing density of a standard die product with ease of reworking and reliability.

Accordingly, the invention consists of an integrated circuit package including a lower surface substrate which is provided with a shoulder on which is supported an upper substrate and in which each substrate supports at least one bare semi-conductor die.

In this way, the lowermost substrate forms a sub-package which can be provided with a lid and external connecting pins to produce an integrated circuit for connection to a printed circuit board while the shoulder provides mechanical support for the upper substrate.

In order to maximise packing density, bare dies and other electronic devices can be provided on both sides of the upper substrate.

Optionally, further sets of shoulders could be incorporated to support further substrates.

Each substrate may be constructed from either low temperature (ie. approximately 86Oc) or high temperature (ie.

approximately 1600'c) multilayer, co-fired material. Bare dies can be mounted on each substrate using epoxy adhesive or solder and the necessary electrical connections made by wire-bonding. Electrical interconnections between substrates are achieved by virtue of the multilayer structure and wire bonding from the package to each substrate.

To facilitate pressure balancing and the back-filling of an inert atmosphere, each subsequent substrate is preferably provided with small holes.

Some embodiments of the invention will now be described, by way of example only, with reference to the drawings of which: Fig. 1 is a cross-sectional view of an integrated circuit package in accordance with the invention; and Fig. 2 is a cross-sectional view of an alternative embodiment.

In Figure 1, a sub-package 1 which is roughly U-shaped in cross-section is formed from multi-layer, co-fired material.

This material is essentially ceramic incorporating metal conducting tracks, pads and vias. Methods of forming this type of material are well-known and will not be described herein. Naked, semi-conductor dies 2A, 2B and 2C are mounted on the floor of the subpackage (which forms a lower substrate 1A) using epoxy adhesive and are connected to conducting pads incorporated within the sub-package 1 by thin wires 3.

The sub-package 1 incorporates a shoulder 4 on which is located a flat ceramic (upper) substrate 5. Further support can be given to the substrate 5 by providing support walls (not shown) extending between the subpackage floor and the lower surface of the substrate 5. The substrate 5 is fixed in place with epoxy adhesive having first been populated with naked semi-conductor dies 6A, 6B, 6C. Wire bonds 7 and 8 form the electrical interconnections between the dies 6A, 6B, 6C and the substrate 5 and the substrate 5 and sub-package 1 respectively. Interconnections between the substrate 5 and the floor of the sub-package 1 is achieved by virtue of the multilayer structure of the sub-package.

The above assembly is provided with a lid 9 and external connecting pins 10.

The package of Fig. 1 can be connected to printed circuit boards by through-hole or surface mount interconnection techniques. It can be filled with an inert gas and hermetically sealed using conventional methods.

It will be appreciated that during assembly of the integrated circuit package of Fig 1, the lower substrate 1A and upper substrate 5 can be tested independently and reworked if necessary.

The materials and assembly techniques used to fabricate the package are well proven and capable of producing packages with very high reliability over a temperature range -55 to 125 c.

It will also be appreciated that a high packing density is attainable and consequently, the package is particularly suitable for use with dies which comprise memory modules. In general, the invention can be applied equally well to analogue or digital circuits and is adaptable for use with dies supplied by most manufacturers.

A second embodiment which has all of the above advantages yet achieves a greater packing density is shown in Fig 2.

In Fig 2 two packages 11 and 12 of the type described with reference to Fig 1 are fixed to one another in a "back to back" configuration. They share common external connecting pins 13 with external wired connections 14 provided between the upper package 11 and said pins 13.

Further embodiments can be configured by populating both sides of the upper substrate 5 (of Figs 1 and 2) with semi-conductor dies, and other electronic devices.

Claims

1. An integrated circuit package including a lower substrate which is provided with a shoulder on which is supported an upper substrate and in which each substrate supports at least one bare semi-conductor die..

2. An integrated circuit package as claimed in claim 1 in which the upper substrate is provided with small holes.

3. An integrated circuit package as claimed in any preceding claim in which each substrate is constructed from multi-layer, co-fired material.

4. An integrated circuit package as claimed in any preceding claim in which the upper subsequent substrate is provided with bare semi-conductor dies on both of its sides.

5. A integrated circuit package as described in any preceding claim including support walls extending between the lower and upper substrates.

6. An integrated circuit package as claimed in any preceding claim in which the bare semi-conductor dies are electrically connected to a substrate by means of wires.

7. An integrated circuit package as claimed in any preceding claim which is provided with a lid and external connecting pins.

8. An integrated circuit package as claimed in any preceding claim incorporating one or more further shoulders for supporting one or more further substrates.

9. An integrated circuit package incorporating two packages as claimed in any preceding claim which are fixed to one another in a back to back configuration, each of said two packages sharing common external connecting pins.

10. An integrated circuit package substantially as hereinbefore described with reference to the drawings.