GB2275569A - Making contact to semiconductor heterojunction devices - Google Patents
Making contact to semiconductor heterojunction devices Download PDFInfo
- Publication number
- GB2275569A GB2275569A GB9303664A GB9303664A GB2275569A GB 2275569 A GB2275569 A GB 2275569A GB 9303664 A GB9303664 A GB 9303664A GB 9303664 A GB9303664 A GB 9303664A GB 2275569 A GB2275569 A GB 2275569A
- Authority
- GB
- United Kingdom
- Prior art keywords
- interface
- ohmic contact
- buried layer
- layer
- ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H10P30/206—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
- H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/161—Source or drain regions of field-effect devices of FETs having Schottky gates
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- H10D64/0116—
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- H10P30/208—
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
In a method for forming a shallow ohmic contact (21, 23) to a buried layer 3 of a semiconductor heterojunction device 1, an interface 11 which presents an abrupt energy barrier is disrupted in the region of desired contact by implanting ions at an appropriate energy. This results in compositional intermixing of the interface. The ohmic contact is then completed by diffusing a high concentration of dopant. <IMAGE>
Description
SEMI CONDUCTOR DEVICE AND METHOD OF MAKING SAME
The present invention is concerned with a method of making an ohmic contact to a heterojunction-type semiconductor device and the device resulting from such method.
A typical heterojunction device is a high electron mobility transistor (HEMT). This uses a heterostructure such as GaAs/AlGaAs to create a so-called two dimensional electron gas (2DEG), in which the wavefunction perpendicular to the layers is quantised in energy and electrons are confined in the GaAs layer near the GaAs/AlGaAs hetero-interface but can move freely in a plane close and parallel to the interface.
By separating donor impurities from the electron conducting channel, ie., by doping the Al GaAs layer, the 2DEG may exhibit very high mobilities (of the order of 106 cm2/Vs). This is utilized in HEMTs, MODFETs (Modulation Doped Field Effect Transistors) and the like. The HEMT finds application in such areas as microwave amplifiers and high speed integrated circuits.
In ordinary field effect transistors, conductivity modulation aG is effected through the change of carrier density AN within a channel. This sets a speed limit of about 1 picosecond using high-velocity
7 electrons ( 2x107cm/s ) travelling over a channel distance of 0. 2 Fm.
Figure 1 of the accompanying drawings shows a typical
HEMT structure 1. This comprises an undoped GaAs active layer 3 above which, in order, are an undoped Al GaAs spacer layer 5 (e.g. 200A thickness), an n-doped
AlGaAs barrier layer 7 (e.g. with impurity concentration around 1018cm 400A thickness) and a cap layer 9 (e.g. 200A thickness).
Figure 2 shows the energy band diagram of the HEMT according to Figure 1. Electrons are transferred to the
AlGaAs/GaAs interface 11 from the doped barrier layer and form a channel 13 in the active layer, adjacent to the interface in which the 2DEG 15 is confined.
However, carriers are free to move perpendicular to the layers so that a current can flow between a source 17 and drain 19, spaced apart and contacting the 2DEG in the buried active layer (see Fig. 1).
A gate electrode 25 above the cap layer switches the current flowing between source and drain, by affecting the number of carriers. Electrons are able to occupy sub-bands in the potential well of the channel but if the carrier density is sufficiently small, only the ground-state is occupied. The Schottky barrier formed at the surface changes the carrier density.
Due to the high concentration of localised states at the
GaAs surface, the Fermi level under all conditions except UHV cleaving of the (110) facet is pinned near the centre of the bandgap. This results in the depletion of charge carriers near the surface in doped samples, with the depletion width depending on the inverse square root of the bulk material doping concentration. The high surface state density also results in an almost work-function independent Schottky barrier height between GaAs and all metals. Thus a metal contact made to n-doped GaAs will result in a non-ohmic contact (non-linear current versus voltage behaviour), even if the work-function of the metal is of the order of the electron affinity.
Conventionally, the two main techniques to form an ohmic contact with a GaAs layer are either to diffuse dopant in underneath the contact or to form another material phase between the contact and the GaAs which results in
Fermi level pinning near the conduction band. By diffusing a high concentration of dopant such as Ge into the surface region under the contact the depletion depth is reduced to such an extent that tunnelling through the barrier becomes the dominant transport mechanism. This gives ohmic behaviour over the current range of interest. There are many contact technologies that work using this effect such as GePd, GeAg and NiGeAu etc.
However, the formation of an ohmic contact to a HEMT structure is more complicated because of the buried abrupt junction (e.g. AlGaAs/GaAs) inherent in this structure. This barrier, especially at low temperatures is very effective in inhibiting current flow between the contact and the 2DEG even if the above condition is met.
Moreover, in order to achieve ohmic contact to the heterostructure using the conventional methods, one either has to use a higher than normal diffusion temperature or else a higher than usual concentration of diffused dopant, so that the buried interface is "blurred". This results in a deep contact which for some devices, prevents them from functioning as intended.
One such device is a so-called velocity modulation transistor (VMT). A VMT is a derivative of the conventional HEMT. Switching of the source-to-drain current is achieved not by changing the number of carriers but by affecting their mobilities. A VMT typically has a pair of barrier layers sandwiching the active layer, with a respective gate electrode on either side. The structure is grown on a conducting substrate.
These electrodes are normally referred to as the front gate (on top of the structure) and the back gate (on the substrate side).
Using the conventional method, with (say) GeAu contacts, results in a leaky back gate. This is because the structure above the conduction band is thin (i. e.
3000A or less) so that the contact easily penetrates it. This makes it important to prevent diffusion of the dopant beyond the inverted hetero-interface.
We have now found a method of forming a shallow ohmic contact which overcomes this problem. Thus, the present invention provides a method of forming a shallow ohmic contact to a buried layer of a heterojunction semiconductor device in which said buried layer is part of a heterostructure and forms an interface with an adjacent layer of the heterostructure such that the interface presents an abrupt energy barrier, the method comprising the steps of:
(i)implanting ions to cause compositional intermixing at the interface; and
(ii)diffusing a dopant material to provide an ohmic contact to said buried layer.
The present invention also provides a heteroj unction semiconductor device comprising a buried layer and an adjacent layer of a heterostructure defining an interface therebetween, said interface being blurred by compositional intermixing between the buried layer and the adjacent layer, layers from a surface of the device down to said buried layer being diffused with a dopant to provide an ohmic contact to the buried layer.
The present invention enables the compositional intermixing to be shallow, ie. confined near the surface so that there is no deep penetration of the contact which would result in the disadvantages referred to above.
The present invention is especially useful for forming ohmic contacts in HEMT or VMT structures. In terms of a
HEMT or VMT structure, a "shallow" ohmic contact means one extending down to but not substantially beyond the active layer of interest, ie, down to the 2DEG.
The energy of implantation necessary to produce compositional intermixing will depend on the atomic mass of the ions to be implanted and the depth of the interface. However, it is not absolutely necessary for the peak concentration of the implanted ions to coincide with the interface. Generally, one will want to use as high an energy as possible, e.g. at least 10KeV, preferably 200KeV or more, for example up to 1000KeV.
For many semiconductor devices which can benefit from this method, the abruptness of the interface (away from the ohmic contact region) is essential to normal operation and so relatively low annealing temperatures (eg. around 500 C) are preferred. This tends to favour p-type dopants as the ions used for the implantation if activation of the implanted dopant is required.
However, n-type dopants and non-dopants (ie, material which do not produce excess free carriers) may also be used to cause the required intermixing.
Typical ions for the implantation step include
Si,Ge,P,Be,As and Ga ions. However, for a GaAs/AlGas interface at a depth of around 800A, As is the preferred material and optionally should be implanted using an ion energy of around 200KeV.
Generally speaking, for ions of a given atomic mass to cause the required intermixing at an interface at a predetermined depth without disruption of other buried interfaces can be obtained from look-up tables to achieve the desired penetration depth and width.
Figures 3 and 4 of the accompanying drawings explain the importance of the implantation step. Figure 3 is an energy diagram showing the effect of merely carrying out a regular high dopant diffusion to a HEMT structure as shown in Fig. 1 to form the ohmic contacts 21,23.
Whilst the effect of the Schottky barrier arising at the metal contact is greatly mitigated, the GaAs/AlGaAs interface still present a high and sharp barrier to conduction.
As shown in Figure 4, the compositional mixing arising from ion implantation smooths out and greatly reduces the magnitude of the barrier at the interface.
The concentration of implanted ions will depend on the peak position with respect to the GaAs/AlGaAs interface and therefore, on mass and energy. Quantitatively, the optimum implanted ion concentration may for example be around 1 x 10 cm for a peak depth of 700 A, using an energy of around 200 KeV.
It is preferred that the spatial range of intermixture of species from the two layers at the interface should be in the order of tens of Angstroms.
After ion implantation has been used to cause intermixing at the interface, the ohmic contact can be completed using any conventional technology applicable to GaAs, and the like, for example NiInW,GePd,N:GeAs etc. although GeAg can also be used.
In general, the present invention is applicable not only to AlGaAs/GaAs systems but to any structure where there is a large band discontinuity, for example InGaAs/AlInAs or InGaAs/InP.
The present invention will now be explained in more detail by the following description of a preferred embodiment and with reference to the accompanying drawings in which:
Figure 1 shows a typical HEMT structure with conventional ohmic contacts;
Figure 2 is an energy diagram for the HEMT structure shown in Figure 1;
Figure 3 shows the effect on the energy diagram of a conventional diffusion process for making an ohmic contact to the 2DEG in the structure shown in Figure 1; and
Figure 4 shows the energy diagram resulting from practising the present invention on the structure shown in Figure 1; and
Figure 5 shows a structure for describing a method and device according to a specific embodiment of the present invention.
Figure 5 shows a device 21 comprising a HEMT structure 21 grown on an n GaAs substrate 25. The strcuture can be grown by molecular beam epitaxy or molecular chemical vapour deposition. The layers of the HEMT structure are grown as follows.
Above a 1000A AlGaAs layer 27, there is formed a 1000A undoped GaAs active layer 29. A 200A semi-insulating AlGaAs spacer layer 31 is then followed by a 400A AlGaAs barrier layer 33 which is n-doped with 1x1018 cm 3 Si. A 100A semi-insulating GaAs layer 35 completes the HEMT structure. The HEMT structure is covered by a 2000A Al metallised layer 37 deposited in situ in the vacuum chamber er ex situ and finally a 1000A Si3N4 insulating layer 39 is deposited on top. In a source or drain region of the device, a contact well 41 is etched.
To form a shallow ohmic contact, the wafers heated to 250'C and the ohmic contact region is implanted with As at an energy of about 200 KeV and a dose of lX1013cm 2. The peak width of the implanted As is about 150A.
The structure is annealed at 500'C. Metallic contacts in the well are then provided by Pd/Ge annealed at 400 C capped with Ni/Cr/Au.
In the light of this disclosure, modifications of the described embodiment as well as other embodiments, all within the scope of the appended claims will now become apparent to persons skilled in the art.
Claims (8)
1. A method of forming a shallow ohmic contact to a buried layer of a heterojunction semiconductor device in which said buried layer is part of a heterostructure and forms an interface with an adjacent layer of the heterostructure such that the interface presents an abrupt energy barrier, the method comprising the steps of:
(i)implanting ions to cause compositional intermixing at the interface; and
(ii)diffusing a dopant material to provide an ohmic contact to said buried layer.
2. A method according to claim 1, wherein the ions are implanted with an energy in the range from 10KeV to 1000KeV.
3. A method according to claim 1 or claim 2, wherein the implanted ions are selected from Si, Ge, P, Be, As and
Ga ions.
4. A method according to either preceding claim, wherein the ohmic contact is completed using
NiInW,GePd,GeAg or NiGeAu.
5. A heterojunction semiconductor device comprising a buried layer and an adjacent layer of a heterostructure defining an interface therebetween, said interface being blurred by compositional intermixing between the buried layer and the adjacent layer, layers from a surface of the device down to said buried layer being diffused with a dopant to provide an ohmic contact to the buried layer.
6. A device according to claim 5, wherein the heterostructure is a HEMT structure.
7. A method of forming a shallow ohmic contact to a buried layer of a heterojunction semiconductor device, the method being substantially as hereinbefore described with reference to Figures 1, 4 and 5 of the accompanying drawings.
8. A heterojunction semiconductor device substantially as hereinbefore defined with reference to Figures 1, 4 and 5 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9303664A GB2275569B (en) | 1993-02-24 | 1993-02-24 | Semiconductor device and method of making same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9303664A GB2275569B (en) | 1993-02-24 | 1993-02-24 | Semiconductor device and method of making same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9303664D0 GB9303664D0 (en) | 1993-04-14 |
| GB2275569A true GB2275569A (en) | 1994-08-31 |
| GB2275569B GB2275569B (en) | 1996-08-07 |
Family
ID=10730925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9303664A Expired - Fee Related GB2275569B (en) | 1993-02-24 | 1993-02-24 | Semiconductor device and method of making same |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2275569B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0741417A3 (en) * | 1995-05-04 | 1997-01-15 | Motorola Inc | Heterostructure field effect device having refractory chemical contact directly on the channel layer and manufacturing method |
| EP1630860A3 (en) * | 1998-09-29 | 2008-03-05 | Raytheon Company | Pseudomorphic high electron mobility transistors |
| WO2008039369A3 (en) * | 2006-09-25 | 2008-05-29 | Lucent Technologies Inc | Field-effect heterostructure transistors |
| FR2914500A1 (en) * | 2007-03-30 | 2008-10-03 | Picogiga Internat Soc Par Acti | IMPROVED OHMICALLY CONTACT ELECTRONIC DEVICE |
-
1993
- 1993-02-24 GB GB9303664A patent/GB2275569B/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0741417A3 (en) * | 1995-05-04 | 1997-01-15 | Motorola Inc | Heterostructure field effect device having refractory chemical contact directly on the channel layer and manufacturing method |
| EP1630860A3 (en) * | 1998-09-29 | 2008-03-05 | Raytheon Company | Pseudomorphic high electron mobility transistors |
| WO2008039369A3 (en) * | 2006-09-25 | 2008-05-29 | Lucent Technologies Inc | Field-effect heterostructure transistors |
| US7781801B2 (en) | 2006-09-25 | 2010-08-24 | Alcatel-Lucent Usa Inc. | Field-effect transistors whose gate electrodes are over semiconductor heterostructures and parts of source and drain electrodes |
| FR2914500A1 (en) * | 2007-03-30 | 2008-10-03 | Picogiga Internat Soc Par Acti | IMPROVED OHMICALLY CONTACT ELECTRONIC DEVICE |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2275569B (en) | 1996-08-07 |
| GB9303664D0 (en) | 1993-04-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20120224 |