GB2112972A - Logic circuits - Google Patents

Abstract

A logic circuit for extracting sample values of a particular type of data word transmitted over parallel signals lines is disclosed. The circuit comprises an oscillator 4 and a first synchronisation circuit 2,3,5 which enables all values of a particular type of data word transmitted on the signal lines to be recorded in a parallel register (6), together with a second synchronisation circuit 8,9,10 which, on receipt of an input signal 7, extracts recorded values from the parallel register (6) and stores them in a second parallel register (15) from which they may be transmitted to circuits for measurement or indication. The second synchronisation circuit is coupled to the first by a gate 12 to ensure that demands for samples occurring while the parallel register (6) is in a state of transition will be queued for action until the recorded value stabilises. <IMAGE>

Description

SPECIFICATION Improvements relating to logic circuits The invention relates to logic circuits and particularly but not exclusively to logic circuits employed in measuring the activity of computer systems for testing purposes.

According to one feature of the invention, a logic circuit designed to produce in response to an external signal an output value consisting of the latest value of a particular type of data to have been transmitted on a set of signal lines designed to carry several types of data by multiplexing includes, in combination, an oscillator circuit, a first bi-stable circuit connected to be switched to a first logic state at the beginning of the first oscillator period following receipt of a first input signal and to be switched to a second logic state at the end of the same oscillator period, a second bi-stable circuit connected to be switched to a first logic state at the beginning of the first oscillator period following receipt of a second input signal, a third bi-stable connected to adopt the logic state of the first bi-stable on receipt of a clock signal occurring in the middle of the oscillator period, a logic gate and a fourth bi-stable connected so that on receipt of a clock signal occurring in the middle of the oscillator period it is switched to a first logic state if the second bistable is in the second logic state or the first bi-stable is in the first logic state and is switched to a second logic state otherwise in which case the second bi-stable is switched to the second logic state at the start of the following oscillator period, a first register consisting of bistable elements connected to be loaded with the value on the signal lines when the third bi-stable changes from the second to the first logic state, and a second register connected to be loaded with the value contained in the first register when the fourth bi-stable changes from the first to the second logic state, the arrangement being such that the first data register is loaded from the signal lines and the second data register is loaded from the first data register in the middle of the first oscillator period beginning after the occurrence of the first input signal and after the occurrence of the second input signal, respectively, except that if both input signals occur during the same oscillator period then loading of the second data register is delayed until loading of the first is completed.

Preferably the outputs of the second data register are connected to a device capable of storing and processing sample value of the data being transmitted on the signal lines.

In the preferred embodiment of the invention, the logic circuit forms part of a measurement system which indicates, over a period of time, the total time during which a particular program instruction or group of instructions was being decoded and executed by the processing unit of a computer system being measured. The first input signal is derived from signals generated by the processing unit being measured to indicate to its own logic circuits that the value on the signal lines is the address in program memory of the instruction whose execution is about to begin, and the second input signal is generated by the measurement system at the moment a sample is required.After generating the second signal and waiting sufficient time for the sample value to be transferred to the second register, the measuremenl system reads the outputs of the second register to obtain the address of the last instruction to have been accessed by the processing unit being measured. The oscillator and the associated bi-stable circuits ensure that the second data register will not be loaded with an address value that is in a state of change in the first register. The probability of the measuring unit receiving a particular address value if it samples at regular intervals is proportional to the time during which the instruction at that address was the last instruction sought by the processing unit and therefore to the total time spent reading and executing that instruction. Tabulation of program addresses with an indication of the time (i.e.

processing resources) spent executing instructions at each address provides valuable information used to improve the speed and efficiency of computer hardware and software.

The preferred embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 shows a circuit diagram of a sampling circuit using bi-stable circuits, logic gates, an oscillator and data registers.

Figure 2 shows a waveform diagram illustrating the operation of the circuit of Figure 1.

Referring now to Figure 1, the first input signal supplied to logic circuit input 1 is derived from a signal or group of signals generated by the internal logic of the processor being measured, which have the effect of validating the data on the signal lines and indicating that the data is an instruction address. The nature of the signals providing this indication varies from one processor to another and the combining of the signals to produce the first input signal is performed by logic circuits (not shown).

The first bi-stable, which in the preferred embodiment comprises two D-type circuits 2 and 3 in Figure 1, generates on receipt of the first input signal an impulse on its noninverting output, shown at 13 in Figure 1 and c) in Figure 2, which lasts for one period of the oscillator starting at the first rising edge of the waveform produced by the oscillator 4 shown at b) in Figure 2. A third bi-stable 5, which in the preferred embodiment comprises a D-type circuit, adopts the logic state of the first bi-stable on receipt of a clock impule derived from the falling edge of the clock waveform so that the noninverting output of this third bi-stable is an impule lasting one clock period and synchronised with the inverted clock waveform.This output, shown as 14 in Figure 1 and d) in Figure 2, is used to load the first register ("input register") 6 with the content of the signal lines not later than 1.5 clock periods after each occurrence of input signal 1.

The second input signal 7 normally has a frequency much lower than that of the first input signal due to the fact that the measuring system cannot read data fast enough to read every value transmitted on the signal lines and captured in the input register 6. Usually the second input signal does not occur simultaneously with the first input signal and in this case the treatment of the second input signal by bi-stables consisting of D-type circuits 8, 9, and 10 in the preferred embodiment is similar to that of the first input signal, except that because of the inversion produced by logic gate 12 the inverting output of D-type circuit 10 is used to load the second register. The value in the input register will be transferred to the second register ("output register") 15 not more than 1.5 clock periods after the occurrence of input signal 7.

If, however, the input register is in a transient state at about the time the sampling impulse 7 occurs, due to the fact that both input signals occur during the same clock period, as shown at a) and e) of Figure 2, then the logic state of the output of the synchronised bi-stable formed by 8 and 9 will be prevented from reaching bi-stable 10 by the action of the inverting output of D-type circuit 3 on logic gate 1 2, until the end of the first oscillator period following the first input signal.

The sampling impulse 7 will thus be queued at the output of 9 until mid-way through the impulse which loads register 6, and will act on bi-stable 10 only on the occurrence of the same falling clock edge that terminates the clock impulse on 6.

Provided that the measuring system waits long enough after issuing the sampling impulse to allow a possible input impulse at 1 to be treated and a subsequent clock cycle to take place, the data read from the outputs of the output register 11 will always be the value that existed in the input register at the time the sampling impulse was received, or the value being loaded into the input register at that time.

A modification to the sampling arrangement may be implemented in which the clock impulse from 10 which loads the output register 1 1 triggers a monostable circuit which signals to the measuring system that a new value is present and stable in the output register.

A further modification would be to derive the sampling impulse from a clock independent of the measuring system and possibly derived from oscillator 4.

Claims (6)

1. A logic circuit designed to produce in response to an external signal an output value consisting of the latest value of a particular type of data to have been transmitted on a set of signal lines designed to carry several types of data by multiplexing includes, in combination, an oscillator circuit, a first bi-stable circuit connected to be switched to a first logic state at the beginning of the first oscillator period following receipt of a first input signal and to be switched to a second logic state at the end of the same oscillator period, a second bi-stable circuit connected to be switched to a first logic state at the beginning of the first oscillator period following receipt of a second input signal, a third bi-stable connected to adopt the logic state of the first bi-stable on receipt of a clock signal occurring in the middle of the oscillator period, a logic gate and a fourth bi-stable connected so that on receipt of a clock signal occurring in the middle of the oscillator period it is switched to a first logic state if the second bi-stable is in the second logic state or the first bi-stable is in the first logic state and is switched to a second logic state otherwise in which case the second bi-stable is switched to the second logic state at the start of the following oscillator period, a first register consisting of bi-stable elements connected to be loaded with the value on the signal lines when the third bi-stable changes from the second to the first logic state, and a second register connected to be loaded with the value contained in the first register when the fourth bi-stable changes from the first to the second logic state, the arrangement being such that the first data register is loaded from the signal lines and the second data register is lodaed from the first data register in the middle of the first oscillator period beginning after the occurrence of the first input signal and after the occurrence of the second input signal, respectively, except that if both input signals occur during the same oscillator period then loading of the second data register is delayed until loading of the first is completed.

2. A circuit as claimed in claim 1 which provides at intervals sample values equal to the most recent value of a particular type of data word transmitted on a set of parallel signal lines.

3. A circuit as claimed in any preceding claim in which the intervals at which sample values are acquired are signalled by a device external to the invention.

4. A circuit as claimed in any preceding claim which generates sample values at predetermined intervals without external stimulus.

5. A circuit as claimed in any preceding claim which indicates which program instruction is being executed by a computer at a particular time.

6. A circuit as claimed in any preceding claim which indicates over a period of time the time spent by a computer in executing the various instructions of a program.