JPS61201362A - Weight cycle introduction circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to a wait cycle insertion circuit, and more particularly, to a wait cycle insertion circuit that can easily change the number of waits even when the basic clock changes in a microcomputer system. .

[Prior art] In computer systems, the CPU sends addresses to select memory and input/output devices, and perform read/output operations.
When sending commands such as write, the required command width (number of waits) differs depending on the access time of these devices.

Conventionally, the command width (number of waits) sent from the CPU
There are three methods: (a) fixedly set, (b) selectively set, and (C) using the wait cycle insertion circuit disclosed in the prior application. In the case of (a) above, the command width (wait number) is fixedly set for all input/output devices and memory, so
A single weight number is set by the strap. However, when there are input/output devices or memories with different access times in the system, it is necessary to set them according to the slowest element, so when the CPU accesses the element with a faster access time, the CPU processing time This results in waste. In the case of (b), different values are set for each input/output device and memory, so if the basic clock of the CPU is constant, the system can be operated efficiently. However, if the basic clock changes to match the processing speed of the CPU, the number of waits must be changed. That is, the number of waits is fixed with respect to the basic clock of the CPU. Furthermore, in the case of (C) 1, the present invention proposed a "wait cycle insertion circuit" (Japanese Patent Application No. 59-211).
As shown in Figure 4, it includes circuits 2 and 3 that decode addresses of memory and input/output devices from the CPUI, and control signals and basic clocks from the CPUI. Then, the control signal is delayed with respect to the change in the basic clock,
A weight adjustment circuit 4 that changes the number of weights, and a weight selection that generates multiple types of weight signals based on the output of the weight adjustment circuit 4 and selects one of them by the output of the decoding circuits 2 and 3. This circuit is provided with circuits 5, 6, and 7. In this circuit, when the basic clock CLK of the CPUI changes, the control signal CNT from the CPU 1 is delayed and the weight adjustment circuit 4 outputs the control signal CNT.

The number of weights in the entire system is variable. but,
When the basic clock of CPU1 changes.

Since the selection has to be made using a jumper, the reliability of the wait cycle insertion circuit is somewhat lacking.

Purpose The purpose of the present invention is to improve such conventional problems and to
Efficiently select the number of U waits for accessing memory and each input/output device to improve system processing capacity, and easily change the optimal number of waits even if the basic clock of the CPU changes. The purpose of the present invention is to provide a wait cycle insertion method that allows the user to insert a wait cycle.

Configuration In order to achieve the above object, the wait cycle insertion circuit of the present invention provides a wait cycle insertion circuit that connects a CPU, a memory that stores programs and data of the CPU, and various input/output devices. means for decoding addresses of input/output devices;
Weight adjustment means for converting a read/write signal from the cPU to a memory or an input/output device into a signal delayed according to the pulse width by measuring the pulse width of a basic clock of the CPU, the weight adjustment means The present invention is characterized in that a plurality of types of weight signals are generated based on the output of the decoding means, and one of them is selected by the output of the decoding means.

Hereinafter, the configuration of the present invention will be explained in detail with reference to examples.

FIG. 4 is an overall block diagram of a wait cycle insertion circuit according to the present invention. As is clear from FIG. 4, the wait cycle insertion circuit of the present invention has almost the same configuration as the earlier application in the overall block diagram, but the internal configuration of the weight adjustment circuit 4 in FIG. 4 is different from that of the earlier application. It's different.

In Fig. 4, if the CPUI accesses the memory (or input/output device (hereinafter referred to as Ilo)),
The operation of the wait cycle insertion circuit will be explained in relation to the operation of the CPU 1. When CPTJI sends the address AD for the memory to the memory decoding circuit 2, the decoding circuit 2 outputs the code CDor for that address.
Select CDI and select weight! Output in '36.

On the other hand, the address AD for Ilo is sent to the decoding circuit 3 for I10, and the decoding circuit 3 selects the corresponding code CD, , CD, and outputs it to the weight selection circuit 6. These codes mean the number of waits, and the number of waits required for the currently accessed device (memory or ■/○) is output.

In the case of FIG. 4, four types of weight numbers can be selected. The decoding circuits 2 and 3 are constituted by FROM, etc., and the way 1 necessary for a predetermined address is predetermined.
- The number (0, 1, 2, 3) is written as 2 bits 1-.

Weight selection mouth! ! 36 receives a signal M/IO indicating whether it is a memory access or an I10 access at a terminal S;
If the signal is "H", the memory is selected.11 If the signal is LI+, Ilo is selected, and the code of either the memory decoding circuit 2 or the I10 decoding circuit 3 is output to the selection circuit 7.

Therefore, the code CD output from the weight selection circuit 6
,,co, is the required number of weights for the currently accessed element.

On the other hand, CPUI sends an address.

Control signal (memory read/write or I
10 read/write) Send the CNT to the weight adjustment circuit 4. In the weight adjustment circuit 4, the signal to the weight generation circuit 5 connected to the secondary stage can be delayed compared to the control signal CNT in consideration of the basic clock of the CPU 1. The wait generation circuit 5 is a CPU
The output signals of weights O to 3 are sent to the weight selection circuit 7 in synchronization with the basic clock CLK.

FIG. 5 is an output timing chart of the wait generation circuit of FIG. 4.

The weight generation circuit 5 generates a weight signal in response to the output signal of the weight adjustment circuit 4. For example, way (
-Generation circuit 5 is a shift register.

It is composed of flip-flops and the like. That is,
When the output of the weight adjustment circuit 4 (in this case, 3.5 clocks) is input to the basic clock CLK shown in FIG. 5, the weight signal OCWA is output as is.
ITO), wait signal 1 (WAIT) that outputs the wait number for the period from the next clock rise to the first clock rise after the end of input, that is, 3 clocks.
L), wait signal 2 (WAIT2) that outputs way 1 match for 2 clocks shorter by l clocks, and further l clocks.
A wait signal 3 (WAIT3) that outputs the number of waits corresponding to one short clock is simultaneously sent to the weight selection circuit 7 in parallel.

The weight selection circuit 7 selects a necessary weight signal using the codes CD, . C.P.
U1 controls the control signal C by this wait signal.
The series of cycles ends by making NT inactive.

FIG. 1 is a configuration diagram of a wait adjustment circuit in a wait cycle insertion circuit showing an embodiment of the present invention.

2 is an operation timing chart of FIG. 1.

In FIG. 1, to, tt and 12.13 are D flip-flops, 14 is a counter, 15 is a clock generator, 16 is a decoder, 17 is an inverter, and 18.19 is an A
ND circuit, 20 is a NOR circuit, 21 (TRI, TR2,
TR3) is a tri-state buffer. CPU
1, the control signal CNT, the reset signal RE
SET.

Clock signals CLK are respectively input, a CPU clock input is output to the CPU 1, and a NOR@ path output, that is, a delayed control signal is output to the wait generation circuit 5.

As the basic clock CLK from the CPUI becomes faster, it is necessary to increase the number of waits. In FIG. 1, the currently input basic clock CLK is monitored, and the control signal CNT is modified with respect to the basic clock CLK. The D flip-flops to and tt are circuits that generate counter start and stop signals for measuring the clock width as a method of monitoring the basic clock CLK, and the D flip-flop chips 12 and 13 are circuits that generate counter start and stop signals for measuring the clock width.

One circuit delays the control signal CNT by one clock, and the other circuit delays the control signal CNT by two clocks. Also, counter 1
4 is a circuit that counts and measures the signal width of the CPU basic clock, a clock generator 15 is a circuit that generates a sampling clock to be applied to the counter 14, and a decoder 16 selects and outputs to the corresponding tri-state buffer 21 according to the count value. This is a circuit that gives TRI of the tri-state buffer 21 is set with the control signal CNT sent from the CPU without delay, TR2 is set with the control signal CNT delayed by one clock through the flip-flop 12, and TR3 is set with the control signal CNT delayed by one clock. A control signal CNT delayed by two clocks is set through flip-flops 12 and 13.

Now, consider the case where the CPU basic clock is 8 MHz.

As shown in FIG. 2, at the rising edge of CPUCLK, both the Q output of the flip-flop IO and the Q output of the flip-flop 11 become II H77, the AND circuit 18 is opened, and a start signal is applied to the counter 14. counter 14
counts the sampling clock (32 MHz) during a half cycle of CPUCLK. For example, 8M
For CPUCLK of Hz, the count value is 2, which is 4M
At Hz, the count value is 4, and at 2 MHz, the count value is 6.

Figure 3 shows the CPUCLK and count values in Figure 1,
It is a relationship diagram of a decoder and a decoder.

Each count value is shown for CPUCLK,
Additionally, decoder outputs are shown for those count values. Decoder 16 decodes the count value and drives tristate buffer 21. In the case of FIG. 2, since the CPUCLK is 8 MHz, the decoder 16 activates the tri-state buffer TR3. As mentioned above, activating TR1 means that the control signal of CPU1 (
(memory or I10 read/write) is sent as is to the wait generation circuit 5 at the next stage, and there is no delay at all. Also, activating TR2 means C
This is to delay the PU control signal by one clock and send it to the wait generation circuit 5 in the first stage.
3 is activated means that the CPU control signal is delayed by two clocks and sent to the wait generation circuit 5 of the first stage.

Generally, as CPUCLK becomes faster, it becomes necessary to increase the number of weights in the entire system. For this purpose, the weight adjustment circuit 4 delays the CPU control signal and sends it to the first stage weight generation circuit 5. In this way, the weight adjustment circuit 4 of FIG. 1 can automatically select the tristate buffer 21 corresponding to the current basic clock of the CPU.

The weight generation circuit 5 generates a weight signal corresponding to the output signal of the weight adjustment circuit 4. Therefore, the wait generation circuit 5 is composed of a shift register, a flip-flop, and the like.

The weight selection circuit 7 selects a necessary weight signal based on the codes CDo and CD1 from the weight selection circuit 6, and sends it to the READY input of the CPUI. CPU1
This wait signal makes the control signal inactive and ends the series of cycles.

As described above, in one aspect of the present invention, when the basic clock of the CPU changes, the total number of waits is automatically adjusted, so a highly reliable wait cycle insertion circuit can be realized. Furthermore, since the wait cycle insertion circuit according to the present invention is not limited to the basic clock of the CPU,
It can be used as a highly versatile wait cycle insertion circuit.

Effects As explained above, according to the present invention, the number of CPU waits is efficiently selected for each of the memory and each ■/○, improving the processing capacity of the system, and changing the basic clock of the CPU. In such cases, the number of weights can be changed to the optimal number with high reliability without using jumpers or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a wait adjustment circuit of a wait cycle insertion circuit showing an embodiment of the present invention, FIG. 2 is an operation timing chart of FIG. 1, and FIG. 3 is a diagram showing the CPU clock and counter values of FIG. 1. The relationship diagram of the decoder, FIG. 4 is an overall block diagram of the wait cycle insertion circuit of the present invention, and FIG.
The figure is an output timing chart of the wait generation circuit of FIG. 4. 1: CPU, 2, 3: Decode circuit, 4: Weight adjustment circuit, 5: Weight generation circuit, 6.7: Weight selection circuit, 10, 11, 12.13: Flip-flop, 14
: Counter, 15: Clock generator, 16: Decoder,
17: Inverter, 18.19: AND circuit, 20: N
OR circuit, 21 Ni dry state buffer. Figure 2 Figure 3

Claims (1)

[Claims] (1) In a computer system that connects a CPU, a memory that stores programs and data of the CPU, and various input/output devices, means for decoding the address of the memory or input/output device accessed by the CPU;
By measuring the pulse width of the PU's basic clock,
A weight adjustment means that converts a read/write signal from the CPU to the memory or input/output device into a signal delayed according to the pulse width, and generates multiple types of weight signals based on the output of the weight adjustment means. and means for selecting one of them by the output of the decoding means.