GB2191355A

GB2191355A - TTL compatible CMOS logic input stage

Info

Publication number: GB2191355A
Application number: GB08712118A
Authority: GB
Inventors: Carlo Dallavalle
Original assignee: SGS Microelettronica SpA
Current assignee: STMicroelectronics SRL
Priority date: 1986-06-04
Filing date: 1987-05-22
Publication date: 1987-12-09
Also published as: GB8712118D0; GB2191355B; IT1204247B; FR2599912B1; FR2599912A1; IT8683624A0; DE3718769A1; JPS63153917A

Description

GB 2 191 355 A 1

SPECIFICATION with the output of TTL logic gates. In these

TrL Compatible CMOS Logic with Low Power instances, the CMOS circuitry is also known as HCT Dissipation in the Input Stage logic (from High speed CMOS, TTL compatible, i.e.

high speed CMOS logic compatible with TTL logic).

The present invention relates, in general, to the 70 In these situations, the gate, i.e. the input stage of so-called micrologic circuits, i.e. logic circuitry the HCT logic, must be capable of accepting, i.e.

realized by the integrated circuit technique, that is recognizing, the worst output levels supplied bythe by "concentrating" a large number of fundamental TTL logic, that is and complex logic functions (logic circuits) in a 1 (from TTL logic) equivalent to VOHTTLmin2.4 V single, monolithically integrated, semiconductor 75 0 (from TTL logic) equivalent to VOLTTL,,,,.,=0.4 V device according to high density integration with a sufficient noise immunity, and therefore:

techniques such as: LSI (Large Scale Integration) or VI-SI (Very Large Scale Integration). According to VINHIII,,=2.0 V and VINLI1m.=0.8 V.

such advanced techniques, a large number of even complex logic elements, such as binary decades, 80 In these conditions, the triggering voltage for shift-registers, etc., may be formed on single chip. which the input stage of the CMOS logic circuit must More in particular, the invention relates to the so- be designed will be:

called CMOS logics, i.e. fabricated by means of complementary MOS (Metal Oxide Semiconductor) 2.0+0.8 technologies, utilizing both p channel and n channel 85 _= 1.4 V surface field effect transistors. 2

Such a family of micrologics (CMOS) already represents a marked technological improvement in Normally, such an interface input stage is formed respect of MOS micrologics made with transistors by a pair of complementary, push-pull connected of a single polarity, because the CMOS circuits have 90 transistors between the supply node and ground, the great advantage of dissipating "power" only having their respective gates connected in common during transitions of internal, input andlor output and constituting the input node.

electrical signals. In otherwords, if continuous This permits to obtain a noise immunity signals (DC levels) are applied to a normally biased characteristic substantially symmetrical both for the CMOS circuit, the latter shows a current absorption 95 0 state and for the 1 state. Nevertheless a problem (defined as Icc= rest supply current or quiescent arises when (and this happens often) the entire supply current) equal only to the leakage current of circuitry is arrested, i.e. when in stand-by condition the inversely biased internal junctions of the circuit. at the 2.4 V level (1 state). In such a case, in fact, the For SSI (Short Scale Integration) or MSI (Medium input stage of the HCT logic circuit conducts current Scale Integration) CMOS circuits, i.e. with a total 100 which is limited only by the sizes of the transistors number of transistors which may reach about 500, forming the input stage.

the Ice current, under rest conditions i.e. static Because the HCT logic circuits must be condition of the signals applied to the inputs (with 0 particularly fast in order to compete (adapt) in terms or 1 levels satisfying the limits of the logic levels VIL of speed with the TTL logic circuits with which they and VJ, is of the order of: 105 interface, the sizes of the transistors of the input stage can not, for this very reason, be much 1,c=-10-6A=1 pA reduced. It follows that in order to maintain the necessary speed, the HCT type CMOS logic circuits In integrated CMOS circuits of the more modern may exhibit a current absorption under rest technologies (LSI or VI-SI), such a value may even 110 conditions (]cc) in the order of 1-2 milliampers, decrease by two orthree orders of magnitude at thus losing completely their most appreciated room temperature, so thatthe stand-by current, i.e. quality by designers of logic circuitry.

the quiescent current, becomes of just few Therefore, a well recognized technical problem is nanoamperes. As it may be easily appreciated, such that of having HCT type CMOS micrologics a characteristic makes the CMOS micrologics 115 exhibiting an undiminished speed performance extremely advantageous in respect of other families together with a current absorption under stand-by of micrologics and in particular of the family which, conditions substantially similar to that of a normal by virtue of its intrinsic characteristic of extremely type CMOS logic circuit, i.e. of the HC type.

high speed, has dominated the field of standard Several proposals have been made for logics (basic logic functions which constitute a 120 overcoming such a problem. According to one of "circuit binder" for aggregating, over complex such proposals, it is contemplated the formation of cards, integrated LSI andlor VI-SI micrologics), that a diode in series to the p channel transistor of the is the TTLfamily (from Transistor-Transistor Logic). input stage with the aim of reducing the quiescent Such TTL logic circuits have, in fact, the drawback of current Icc through the p channel transistor, which showing a quiescent current absorption which may 125 being the element subject to a greater overdriving vary from few hundreds microampers to few factor (with 2.4 V at the input) is obviously the milliampers. critical element to be controlled in order to limit the On the other hand, nowadays, many apparatuses quiescent current.

andlor logic devices made by the CMOS technique According to another of such proposals, it is are necessarily designed so asto be interfaceable 130 contemplated to invervene during the fabrication 2 GB 2 191 355 A 2 process, by utilizing an additional mass for ion of a second inverting stage following said input implantation in such a way as to increase the stage, which is schematically represented in the threshold voltage of the p channel transistor of the figure by the complementary transistors pairThP2 input stage in respect of the typical threshold and Th,2, push -pull connected. Obviously the logic voltage of the other integrated transistors of the 70 circuit will comprise a number of other stages (not circuit. Such an expedient permits to reduce the shown in the figure for simplicity's sake), following stand-by current Icc though depressing the speed the two stages shown. The way the circuit function characteristics of the logic circuit due to the rising of is such that, whenever the input voltage of the the threshold voltage of the p channel transistor of circuit blocks itself, for example at 2.4 V (1 TTL logic the input stage. 75 level), a certain current Icc flows through the input Both such known proposals, though allowing a stage for an extremely small period of time, which is certain decrease of the stand-by current, decisively equivalent to the delay with which the output of the reduce the speed of the circuit in respect of an input second inverting stage raises to 5V, that is few stage circuit of the standard inverter type. The nanoseconds. Once this infinitesimal period of time second one of the above mentioned known 80 is elapsed, the voltage at the input of the circuit will proposals requires, further, an additional mask and no longer be 2.4 V but it will have raised, decisively therefore a more complicated fabrication process. approaching the value of the supply voltage, by In a far more advantageous way, the circuit object virtue of the fact that the n channel MOS transistor of the present invention overcomes or avoids the Thn3, acting as a "pull- up", will have drawn the drawbacks and the limitations of the circuits of the 85 input voltage towards the value of the supply known proposals, mentioned above, and allows to voltage, that is to 5 V. As a consequence also the Icc ensure a substantially null stand-by current, i.e. current will have practically reduced itself to zero.

equivalent only to the leakage current of reversely Therefore, the HCT logic circuit of the invention biased junctions, typical of the modern CMOS behaves exactly as a normal CMOS logic circuit logic circuits and practically negligible even in the 90 under input stand-by conditions with the exception case of TTL compatible CMOS logic circuits or HCT of a "peak" of absorbed current Icc which has a circuits. duration of just few nanoseconds and which is Such advantages as well as others which will be therefore practically negligible in terms of evidentthrough the following description are containing the dissipated power under stand-by obtained, according to the present invention, by 95 conditions.

means of a CMOS logic circuit comprising a More preferably, according to an embodiment of complementary pair, push-pull connected, MOS the invention, the fourth terminal of such additional transistors, whose gates, connected in common, n channel MOS transistor Th,,3, which is constitute the input node of said logic circuit, which represented by the "p-well" substrate thereof, is is characterized, by comprising an additional n 100 short circuited to the source, as shown in the figure.

channel MOS transistor whose source is connected This allows the MOS transistorTh,,3 to exert more to said input node and whose drain is connected to a effectively its "pull-up" action upon the input supply node (Vcc) of the logic circuit and whose gate voltage of the input stage (interface stage) of the is connected to the output of a second inverting HCT circuit, i.e. bringing the input voltage as close stage following said input stage formed by said pair 105 as possible to the value of the supply voltage Vcc.

of complementary MOS transistors. The function of In fact, under such stand by conditions, the such an n channel transistor is to intervene, theoretical value to which the input voltage VIN may whenever stand-by conditions of the whole logic be pulled-up (assuming the impedance of the TTL circuitry are determined, so that a voltage of 2.4 V (1 circuit allows it) is given by: VCC---Wh,, which, under from TTL logics) is applied at the input of the HCT 110 the indicated conditions i.e. with a supply voltage of logic circuit in order to quickly raise the voltage at 5 V, equals about 4 V, being the voltage drop across the input of the HCT circuit to the voltage of the the transistor WhO equal to about 1 V.

supply node (Vcc), thus determining the effective On the contrary, if the "p-well" of the transistor nullification of the stand-by current (Icc). The Thn3 is connected to ground, the input voltage VIN additional n channel transistor, coupled to the input, 115 would be shifted towards the Vcc voltage by a lesser acts therefore as a "pull-up" pulling towards the amount in respect of its value of 2.4 V because of the supply voltage Vcc the input node by virtue of its so-called body effect. Therefore it is decisively much lower impedance in respect of the output advantageous to ensure the input voltage VIN raising impedance of the eventual TTL logic circuit with as much as possible towards the value of the supply which the HCT circuit is interfaced. 120 voltage Vcc, by the expedient of short circuiting the The circuit of the invention is shown in the substrate of the transistor Th,,3 (i.e. its "p-well") to diagram of the annexed drawing. The its source. in this way the transistor pair of the input complementary input pair is formed by the M0,5 stage of interface are positively cut-off under all transistors Th.1 and Thnt Pushpull connected stand-by conditions.

between the supply node of the circuit (Vcc), which 125 An n channel MOS transistor connected between is commonly at 5V, and ground. An additional n the input node of the HCT circuit and the supply channel transistor, ThA has its source connected to node so as shown in the figure, has essentially a the input node of the circuit and its drain connected much lower impedance than the output impedance to the supply node Vec. The gate of such an typical of a TTL circuit and, therefore, may additional transistor Th,,3 is connected to the output 130 effectively perform its "pull-up" function. The 3 GB 2 191 355 A 3

Claims

addition of such a transistor has proved itself in CLAIMS practice

substantially noninfluent upon the intrinsic 1. A TTL comparable, CMOS logic circuit speed characteristics of the input stages of the HCT 40 comprising an input inverting stage formed circuit. Through experiments, it has been found that essentially by two complementary, push-pull an n channel MOS transistor of relatively small size connected, MOS transistors, whose gates are and such, for example, to determine an impedance connected in common and constitute the input node comprised between 0.
2 and 1 megaohm, is perfectly of said logic circuit, characterized in that suitable to the objectives of the invention and it 45 an additional n channel MOS transistor has its does not load but very little the second inverter source connected to said input node, its drain stage of the logic circuit, having a practically connected to a supply node of the logic circuit and negligible capacitance. its gate connected to the output of a second Notwithstanding such an n channel MOS inverting stage following said input inverting stage.

transistor may have dimensions and structural 50 2. The CMOS logic circuit according to Claim 1, characteristics similar or comparable to those of the wherein said additional n channel MOS transistor is transistors forming the push-pull pairs of the input formed in a p-well region and such a p-well region is inverter stages, it is preferred, in the practice of the short circuited to the source of the same transistor.

present invention, to form such an additional n
3. The CMOS logic circuit according to Claim 1, channel MOS transistor with smaller dimensions 55 wherein all said MOS transistors have the same than the dimensions of the complementary MOS dimensional characteristics.

transistors of said input pairs in order to ensure its
4. The CMOS logic circuit according to Claim 1, noninfluence upon the speed characteristics of the wherein said n channel MOS transistor has smaller circuit. dimensions than the dimensions of said A further advantage of the circuit of the invention 60 complementary MOS transistors of the input pair.

is in the fact that the presence of the n channel MOS
5. An input stage for a CMOS logic circuit transistor Thn3 does not influence the leakage comprising a pair of complementary, push-pull characteristics of the inputs of the logic circuits to connected, MOS transistors whose gates are which such an additional transistor is applied, connected in common and constitute an input node because in measuring the leakage toward ground as 65 of said stage, and wherein an additional n channel well as in measuring the leakage toward the supply MOS transistor has its source connected to said voltage Vcc, such a transistor Th,,21 is cut-off. input node, its drain connected to a supply node of In respect of some of the known proposals, the the logic circuit and its gate connected to the output present invention has the advantage of not node of a second inverting stage following said requiring any modification of the fabrication 70 input stage.

process, such as for example the addition of
6. The input stage of Claim 5, wherein said n masking steps for purposely modifying the doping channel MOS transistor is formed in a p-well region levels of the p channel transistors of the input and such a p-well region is short circuited to the stages. source of the same transistor.
7. An input stage for a CMOS logic circuit substantially as described herein with reference to the accompanying drawing.

Printed for Her Majesty's Stationery Office by Courier Press, Leamington Spa, 12187. Demand No. 8991685.

Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.