GB2185851A - Method of fabricating an mos transistor - Google Patents
Method of fabricating an mos transistor Download PDFInfo
- Publication number
- GB2185851A GB2185851A GB08601830A GB8601830A GB2185851A GB 2185851 A GB2185851 A GB 2185851A GB 08601830 A GB08601830 A GB 08601830A GB 8601830 A GB8601830 A GB 8601830A GB 2185851 A GB2185851 A GB 2185851A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- amorphous
- insulating layer
- polycrystalline
- seed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 17
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 238000001953 recrystallisation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- MUJOIMFVNIBMKC-UHFFFAOYSA-N fludioxonil Chemical compound C=12OC(F)(F)OC2=CC=CC=1C1=CNC=C1C#N MUJOIMFVNIBMKC-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/40—Crystalline structures
Landscapes
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
A metal oxide silicon (MOS) transistor comprises a semiconductor substrate (2), an insulating layer (1) on the substrate, and a seed window (3) in the insulating layer (1), which seed window (3) communicates with the semiconductor substrate. The MOS transistor also comprises a re-crystallised amorphous or polycrystalline semiconductor layer (4) which overlies the insulating layer (1) at least in the region of the seed window and contacts the semiconductor substrate (2). A source is formed in the re-crystallised amorphous or polycrystalline semiconductor layer (4) upon the insulating layer (1) on one side of the seed window (3), and a drain is formed in the re-crystallised amorphous or polycrystalline semiconductor layer (4) upon the other side of the seed window (3), and a gate electrode comprising a dielectric layer (9) and a conducting or semiconducting layer (10) is formed between the source and the drain.
Description
SPECIFICATION
Methods for fabricating transistors and
MOS transistors fabricated by such methods
This invention relates to methods for fabricating transistors, and to metal oxide silicon (MOS) transistors fabricated by such methods.
A A conventional type of transistor structure comprises a positively doped bulk silicon structure which includes source and drain regions in the form of diffused N conductivity type regions spaced apart in a silicon substrate. A gate electrode is formed over. the silicon substrate between the source and drain regions. This structure has the disadvantage that undesirable capacitances exist between the source and drain regions and the substrate.
Another conventional type of transistor structure, in this case a silicon on saphire (SOS) transistor, comprises a silicon layer having spaced apart source and drain regions on an insulating layer of saphire. Such a transistor attempts to reduce undesirable capacitances by putting the insulating layer under the device but this isolates the active channel region resulting in the device taking up an undefined potential which can modify the transistor action. Although this can be avoided by including a substrate contact on the top surface of the device, such a contact necesitates that the device takes up more space.
A A further conventional type of transistor which is subject to the same disadvantages as the SOS transistor is a silicon on insulator (S0l) transistor. Such a device comprises an insulating layer formed on a silicon substrate.
A A further silicon layer which includes source and drain regions is formed on the insulating layer.
A conventional method of fabricating the silicon on insulator (SOI) transistor structures comprises forming an insulating layer on a silicon substrate and etching seed windows in the insulating layer. A layer of polysilicon is then formed over the insulating layer and over the seed window. The polysilicon is then recrystallised (solid phase epitaxy) by way of a recrystallisation process, such as the one described in H.W. Lam IEDM Technical Digest 1980 paper 22.1. Source and drain regions are then formed in the recrystallised polysilicon layer by, for example, an implant doping process and a gate is formed between the source and the drain. In this structure, the gate overlies the insulating layer.
Such methods have the disadvantage that the seed window serves no further purpose after the recrystallisation process and so forms wasted space in the integrated circuit.
Further, it is difficult to recrystallise the polysilicon over large areas, particularly in areas distant from the seed window, which imposes restrictions on circuit layout and design.
The present invention is directed to a method for fabricating transistors which alleviates the aforementioned disadvantages, and
MOS transistors fabricated by such methods, which transistors have relatively low capacitances associated therewith.
According to the present invention there is provided a metal oxide silicon (MOS) transistor comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a seed window in the insulating layer which seed window communicates with the semiconductor substrate, and a recrystallised amorphous or polycrystalline semiconductor layer overlying the insulating layer at least in the region of the seed window and contacting the semiconductor substrate, a source formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the insulating layer on one side of the seed window, a drain formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the other side of the seed window, and a gate between the source and the drain, the gate overlying the seed window.
The source and the drain may be diffused N type regions formed in the part of the recrystallised amorphous or polycrystalline layer which overlies the insulator.
According to the present invention there is also provided a method for fabricating a metal oxide silicon (MOS) transistor, the method comprising: forming an insulating layer having one or more seed windows on a semiconductor substrate; depositing an amorphous or polycrystalline semiconductor layer on the insulating layer and on the seed window(s); recrystallising the amorphous or polycrystalline semiconductor layer at least in the region of the seed window(s); isolating the recrystallised amorphous or polycrystalline semiconductor layer in the region of the seed window from the remaining amorphous or polycrystalline semiconductor layer; and forming a source on one side of the seed window over the insulating layer, a drain on another side of the seed window over the insulating layer, and a gate between the source and the drain, the gate being located over the seed window.
The step of forming the insulating layer having one or more seed windows may comprise forming the insulating layer on the semiconductor substrate and then etching holes, corresponding to the seed window(s), through the insulating layer.
Alternatively, recesses may be formed in the semiconductor substrate and the insulating layer may be formed in the recesses, the seed window(s) and the insulating layer thereby having a substantially flat surface. The isolation of the recrystallised amorphous or polycrystalline semiconductor layer in the seed window region(s) may be effected by etching away the non-recrystallised and/or recrystal lised amorphous or polycrystalline semiconductor layer in the field region or by converting the non-recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field region to an insulator.
The drain and the source may be formed doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping of the polycrystalline layer after deposition.
The step of recrystallising the amorphous or polycrystalline layer may be by solid phase epitaxy or by direct epitaxy. In direct epitaxy, the amorphous polycrystalline layer recrystallises in the region of the seed window as the layer is deposited over the insulating layer and the seed window.
Embodiments of the present invention are advantageous in that they enable the fabrication of a novel MOS transistor structure having relatively low capacitances associated therewith. In addition, they provide for the elimination of the need to waste space due to adandonment of seed window regions by incorporating the seed window regions into the
MOS transistor structures. This saving of space can lead to increased packing density.
The invention will now be further described, by way of example with reference to the accompanying drawings, in which:
Figures la to le show fabrication stages for a MOS transistor structure embodying the present invention; and
Figures 2a to 2e show fabrication stages of an alternative MOS transistor structure embodying the present invention.
In Fig. 1a an insulating layer, for example, silicon dioxide is formed on a single crystal semiconductor substrate 2 such as silicon. A hole is etched through the insulating layer 1 to form a seed window 3; although only one seed window 3 is shown, a plurality of seed windows may be formed. A layer of amorphous or polycrystalline semiconductor, such as polysilicon 4, is then deposited over the insulating layer 1 and in the seed window 3 as illustrated in Fig. 1 b.
At least some of the polysilicon 4 in the region of the seed window 3 spontaneously becomes recrystallised using the substrate as a seed (direct epitaxy, that is, gas phase epitaxial deposition). However, the polysilicon 4 may be subjected to, for example, furnace treatment to cause solid phase epitaxy which grows single crystal silicon regions in the polysilicon around the seed window 3 using the substrate as a seed. The single crystal silicon region so formed is illustrated in Fig. 1c by reference numeral 5. Alternatively, the recrystallisation may be induced by laser treatments, electron beam treatments or quartz halogen lamps.
The seed window 3 is to correspond to an active region of a gate of a metal oxide silicon (MOS) transistor to be formed in the seed window 3 region. The next stage in the method of fabrication of the MOS transistor is to etch away field regions 6 of the MOS transistor, the resulting structure being illustrated in Fig. 1d. Alternatively, the field region 6 may be formed by converting the polysilicon layer in these regions into an insulator by oxidation. Source and drain regions 7 and 8 are formed in the regions of the polysilicon layer which overlie the insulating layer 1, for example, by furnace doping or implant. In the arrangement illustrated in Fig. 1e, the source region 7 and the drain region 8 are formed on opposite sides of the seed window 3 and may be of N or P conductivity type.A gate electrode, comprising a dielectric layer 9 and a conducting or semiconducting layer 10 is formed over the seed window 3 as shown in
Fig. 1 e. The gate electrode may be formed before the source and drain regions 7 and 8 are formed.
An MOS transistor, formed in the above described way, such as the one illustrated in Fig.
1e, is advantageous in that the benefits of silicon on insulator (SOI) technology (i.e. low capacitances) may be achieved for MOS transistors while using a simple fabrication process.
The relatively low capacitance achievable in
MOS transistors using the above described fabrication method exist since the fabrication method enables the MOS transistor to be formed in islands of good quality silicon which are connected to the substrate in the gate region, but have their source and drain regions over the initially formed oxide layer. Additionally, the transistors fabricated in this way may have low field capacitance because the field oxide may be made up of the oxidised polysilicon plus the original oxide.
An alternative series of fabrication stages for an MOS transistor structure is shown in
Figs. 2a to 2e. In this case, the insulating layer 1 is formed in recesses which have been etched in the single crystal semiconductor substrate 2, which results in the seed window 3 and the insulating layer 1 having a substantially flat surface (Fig. 2a). The polysilicon 4 is then formed on the surface of the insulating layer 1 and the seed window 3 as shown in
Fig. 2b. Recrystallisation of the polysilicon 4 in the region of the seed window 3 then takes place in a similar way to that described with reference to Fig. 1c to form a single crystal silicon region 5.
Source and drain regions 7 and 8 are then formed in a similar manner to that described earlier and the structure is then isolated, in this case, by converting the field regions to oxide 11 (Fig. 2d). Source and drain electrodes S, D are connected to the respective source and drain regions 7, 8 and a gate electrode G is formed over the seed window 3 (Fig. 2e) in a similar manner to that described with reference to Fig. 1e.
The methods for fabricating transistors, and the MOS transistors described above are intended to be examples and it is envisaged that variations may be adopted without departing from the scope of the present invention. For example, the step of recrystallisation by solid phase epitaxy may be combined with the isolation step which involves oxidation of the field regions.
Claims (4)
1. A method for fabricating a metal oxide silicon (MOS) transistor, the method comprising: forming on insulating layer having one or more seed windows on a semiconductor substrate; depositing an amorphous or polycrystalline semiconductor layer on the insulating layer and on the one or more seed windows; recrystallising the amorphous or polycrystalline semiconductor layer at least in the region of the seed windows; isolating the recrystallised amorphous or polycrystalline semiconductor layer in the region of the seed window from the remaining amorphous or polycrystalline semiconductor layer; and forming a source on one side of the seed window over the insulating layer; a drain on another side of the seed window over the insulating layer, and a gate between the source and the drain, the gate being located over the seed window.
2. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in claim 1 wherein the step of forming the insulating layer having one or more seed windows comprises forming the insulating layer on the semiconductor substrate and then etching holes, corresponding to the seed windows through the insulating layer.
3. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in claim 1 wherein recesses are formed in the semiconductor substrate and the insulating layer, the seed windows and the insulating layer thereby having a substantially flat surface.
4. A method of. fabricating a metal oxide silicon (MOS) transistor as claimed in claim 1 wherein isolation of the recrystallised amorphous or polycrystalline semiconductor layer in the seed window regions is achieved by etching away the non-crystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field region or by converting the non-recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field regions to an insulator.
4. A method of fabricating a metal oxide silicon (MOS) transistor wherein isolation of the recrystallised amorphous or polycrystalline semiconductor layer in the seed window regions is achieved by etching away the noncrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field region or by converting the non-recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field regions to an insulator.
5. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in any preceding claim wherein the drain is formed by doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping of the polycrystalline layer after deposition.
6. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in any preceding claim wherein the the source is formed by doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping the polycrystalline layer after deposition.
7. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in any preceding claim wherein the step of recrystallising the amorphous or polycrystalline layer is by solid phase epitaxy or direct epitaxy.
8. A method of fabricating a metal oxide silicon (MOS) transistor substantially as hereinbefore described with reference to the accompanying drawings.
9. A metal oxide silicon (MOS) transistor comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a seed window in the insulating layer which seed window communicates with the semiconductor substrate, and a recrystallised amorphous or polycrystalline semiconductor layer overlying the insulating layer at least in the region of the seed window and contacting the semiconductor substrate, a source formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the insulating layer on one side of the seed window, a drain formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the other side of the seed window and a gate between the source and the drain, the gate overlying the seed window.
10. A metal oxide silicon (MOS) transistor as claimed in claim 9 wherein the source and the drain are diffused N-type regions formed in the part of the recrystallised amorphous or polycrystalline layer which overlies the insulator.
11. A metal oxide silicon (MOS) transistor substantially as hereinbefore described with reference to the accompanying drawings.
CLAIMS
Amendments to the claims have been filed, and have the following effect:
Claim 4 above has been textually amended.
New or textually amended claims have been filed as follows:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08601830A GB2185851A (en) | 1986-01-25 | 1986-01-25 | Method of fabricating an mos transistor |
| EP87900849A EP0258285A1 (en) | 1986-01-25 | 1987-01-19 | Methods for fabricating transistors and mos transistors fabricated by such methods |
| PCT/GB1987/000030 WO1987004563A1 (en) | 1986-01-25 | 1987-01-19 | Methods for fabricating transistors and mos transistors fabricated by such methods |
| JP62500890A JPS63502544A (en) | 1986-01-25 | 1987-01-19 | Transistor manufacturing method and MOS transistor manufactured by the same method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08601830A GB2185851A (en) | 1986-01-25 | 1986-01-25 | Method of fabricating an mos transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8601830D0 GB8601830D0 (en) | 1986-02-26 |
| GB2185851A true GB2185851A (en) | 1987-07-29 |
Family
ID=10591944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08601830A Withdrawn GB2185851A (en) | 1986-01-25 | 1986-01-25 | Method of fabricating an mos transistor |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0258285A1 (en) |
| JP (1) | JPS63502544A (en) |
| GB (1) | GB2185851A (en) |
| WO (1) | WO1987004563A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1274134A3 (en) * | 2001-07-04 | 2006-11-02 | Matsushita Electric Industrial Co., Ltd. | MOS transistor and its fabrication method |
| EP4297099A1 (en) * | 2022-06-24 | 2023-12-27 | NXP USA, Inc. | Transistor with current terminal regions and channel region in layer over dielectric |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4863877A (en) * | 1987-11-13 | 1989-09-05 | Kopin Corporation | Ion implantation and annealing of compound semiconductor layers |
| US5021119A (en) * | 1987-11-13 | 1991-06-04 | Kopin Corporation | Zone-melting recrystallization process |
| US5453153A (en) * | 1987-11-13 | 1995-09-26 | Kopin Corporation | Zone-melting recrystallization process |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3764413A (en) * | 1970-11-25 | 1973-10-09 | Nippon Electric Co | Method of producing insulated gate field effect transistors |
| GB1457800A (en) * | 1973-02-24 | 1976-12-08 | Hitachi Ltd Mis | Semiconductor devices |
| GB1604786A (en) * | 1977-06-03 | 1981-12-16 | Fujitsu Ltd | Semiconductor device and process for producing the same |
| US4476475A (en) * | 1982-11-19 | 1984-10-09 | Northern Telecom Limited | Stacked MOS transistor |
| US4514895A (en) * | 1983-04-20 | 1985-05-07 | Mitsubishi Denki Kabushiki Kaisha | Method of forming field-effect transistors using selectively beam-crystallized polysilicon channel regions |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4269631A (en) * | 1980-01-14 | 1981-05-26 | International Business Machines Corporation | Selective epitaxy method using laser annealing for making filamentary transistors |
| JPS5861622A (en) * | 1981-10-09 | 1983-04-12 | Hitachi Ltd | Manufacture of single crystal thin film |
| EP0077737A3 (en) * | 1981-10-19 | 1984-11-07 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Low capacitance field effect transistor |
-
1986
- 1986-01-25 GB GB08601830A patent/GB2185851A/en not_active Withdrawn
-
1987
- 1987-01-19 EP EP87900849A patent/EP0258285A1/en not_active Withdrawn
- 1987-01-19 WO PCT/GB1987/000030 patent/WO1987004563A1/en not_active Ceased
- 1987-01-19 JP JP62500890A patent/JPS63502544A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3764413A (en) * | 1970-11-25 | 1973-10-09 | Nippon Electric Co | Method of producing insulated gate field effect transistors |
| GB1457800A (en) * | 1973-02-24 | 1976-12-08 | Hitachi Ltd Mis | Semiconductor devices |
| GB1604786A (en) * | 1977-06-03 | 1981-12-16 | Fujitsu Ltd | Semiconductor device and process for producing the same |
| US4476475A (en) * | 1982-11-19 | 1984-10-09 | Northern Telecom Limited | Stacked MOS transistor |
| US4514895A (en) * | 1983-04-20 | 1985-05-07 | Mitsubishi Denki Kabushiki Kaisha | Method of forming field-effect transistors using selectively beam-crystallized polysilicon channel regions |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1274134A3 (en) * | 2001-07-04 | 2006-11-02 | Matsushita Electric Industrial Co., Ltd. | MOS transistor and its fabrication method |
| EP4297099A1 (en) * | 2022-06-24 | 2023-12-27 | NXP USA, Inc. | Transistor with current terminal regions and channel region in layer over dielectric |
| US20230420546A1 (en) * | 2022-06-24 | 2023-12-28 | Nxp Usa, Inc. | Transistor with current terminal regions and channel region in layer over dielectric |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63502544A (en) | 1988-09-22 |
| EP0258285A1 (en) | 1988-03-09 |
| WO1987004563A1 (en) | 1987-07-30 |
| GB8601830D0 (en) | 1986-02-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |