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GB1520078A - Integrated mis driver stage - Google Patents

Integrated mis driver stage

Info

Publication number
GB1520078A
GB1520078A GB19324/76A GB1932476A GB1520078A GB 1520078 A GB1520078 A GB 1520078A GB 19324/76 A GB19324/76 A GB 19324/76A GB 1932476 A GB1932476 A GB 1932476A GB 1520078 A GB1520078 A GB 1520078A
Authority
GB
United Kingdom
Prior art keywords
junction point
transistors
coupled
capacitor
feedback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB19324/76A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of GB1520078A publication Critical patent/GB1520078A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

1520078 Transistor switching circuits ITT INDUSTRIES Inc 11 May 1976 [16 May 1975] 19324/76 Heading H3T An integrated circuit comprises: three field effect transistors 1, 2, 3 connected in series between supply terminals; two further field effect transistors 5, 6 also in series; an input applied to the gates of transistor 1, 5; and a feedback path via capacitor Cl. In the embodiment of Fig. 5, the feedback capacitor C1 is coupled from the junction point 7 between the series connected transistors 5, 6 and the output from the circuit is taken from the junction point A between two further series connected transistors 5' 6' driven in push-pull by the input inverter stage I. The feedback is coupled to the junction point 8 between transistors 2, 3. The gates of the transistors 2, 3, 6 may be driven by circuits which include further capacitors C2, C3 or alternatively they may be strapped to their respective drain electrodes, Figs. 1, 4 (not shown). In other alternatives the feedback capacitor is coupled to the push-pull driven output stage and the intermediate stage is omitted, Figs. 1, 2, 3 (not shown). Where such an arrangement includes the capacitor C2, this may be coupled either to the junction point 9 as shown or to the junction point in the output stage, Fig. 3 (not shown).
GB19324/76A 1975-05-16 1976-05-11 Integrated mis driver stage Expired GB1520078A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752521949 DE2521949A1 (en) 1975-05-16 1975-05-16 MONOLITHICALLY INTEGRATED MIS-DRIVER STAGE

Publications (1)

Publication Number Publication Date
GB1520078A true GB1520078A (en) 1978-08-02

Family

ID=5946771

Family Applications (1)

Application Number Title Priority Date Filing Date
GB19324/76A Expired GB1520078A (en) 1975-05-16 1976-05-11 Integrated mis driver stage

Country Status (6)

Country Link
JP (1) JPS51140544A (en)
DE (1) DE2521949A1 (en)
FR (1) FR2311407A1 (en)
GB (1) GB1520078A (en)
IT (1) IT1060573B (en)
NL (1) NL7605092A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0045133A3 (en) * 1980-07-28 1982-02-10 Inmos Corporation Bootstrap driver circuits for an mos memory
GB2132434A (en) * 1982-12-21 1984-07-04 Western Electric Co Improvements in or relating to driver circuits
US4583203A (en) * 1983-01-14 1986-04-15 Standard Telephones & Cables Memory output circuit

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4071783A (en) * 1976-11-29 1978-01-31 International Business Machines Corporation Enhancement/depletion mode field effect transistor driver
US4093875A (en) * 1977-01-31 1978-06-06 International Business Machines Corporation Field effect transistor (FET) circuit utilizing substrate potential for turning off depletion mode devices
IT1185851B (en) * 1985-08-02 1987-11-18 Sgs Microelettronica Spa PILOTING CIRCUIT WITH BOCTSTRAP IN N-MOS TECHNOLOGY FOR CAPACITIVE LOADS

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1534428A (en) * 1966-12-14 1968-07-26 North American Aviation Inc Capacitive feedback semiconductor metal oxide excitation device
US3508084A (en) * 1967-10-06 1970-04-21 Texas Instruments Inc Enhancement-mode mos circuitry

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0045133A3 (en) * 1980-07-28 1982-02-10 Inmos Corporation Bootstrap driver circuits for an mos memory
GB2132434A (en) * 1982-12-21 1984-07-04 Western Electric Co Improvements in or relating to driver circuits
US4583203A (en) * 1983-01-14 1986-04-15 Standard Telephones & Cables Memory output circuit

Also Published As

Publication number Publication date
IT1060573B (en) 1982-08-20
JPS51140544A (en) 1976-12-03
NL7605092A (en) 1976-11-18
FR2311407A1 (en) 1976-12-10
DE2521949A1 (en) 1976-11-25

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee