GB1506764A - Delay lines - Google Patents

Abstract

1506764 Active delays DEFENCE SECRETARY OF STATE FOR 10 Sept 1976 [12 Sept 1975] 37666/75 Heading H3U A clocked delay line includes: a first input stage comprising at least one analogue storage cell 1 receiving signal samples at an input 2 and producing output samples, having a lower sampling rate, at a plurality of outputs 3; at least one further input stage comprising a plurality of analogue storage cells 11, 21, 31 corresponding in number to the number of outputs of the first input stage and each producing a plurality of outputs 13, 23, 33 at a lower sampling frequency; at least one precursory output stage comprising a plurality of analogue storage cells 14, 24, 34 each having a plurality of inputs 16, 26, 36 receiving signal samples from respective preceding stages and each having an output at which is produced a recombined sample series at a higher sampling rate; and a final output stage comprising at least one analogue store 4 having a plurality of inputs 6 receiving signal samples from respective outputs of the precursory output stages and having an output at which is produced a recombined sample series at a higher sampling rate. As shown, signal samples are fed serially into a first shift register 1 at a rate f, and are fed out in parallel at a rate f/3 to provide three serial input signals to respective second stage shift registers 11, 21, 31 which in turn produce nine parallel outputs at a rate f/9 to delays 17, 27, 37 each of which comprises a respective two stage delay for each of the nine signals. The delayed signals are then fed in parallel at a clock rate f/9 to registers 14, 24, 34 each of which produces a serial output at clock rate f/3. These outputs are then fed as parallel inputs of a final stage 4 having a serial output at the initial clock rate f. The arrangement is equivalent to a simple delay of thirty four stages, but comprises only ten transfer locations. The series may be extended to give increased delays, Fig. 5 (not shown). In a modification, Fig. 6 (not shown), instead of the three-location shift registers two-location registers are used, every third sample being passed on directly to the next stage without entering the register, by modifying the clock signal sequence. In a second embodiment, Fig. 8 (not shown), multipart delays, e.g. CCD or Bucket Brigade, are used. In the inputs stages these delays have a single input and two outputs so that each succeeding stage doubles the number of signal paths. Conversely each output stage delay has two inputs and a single output.