GB1326386A - Television standards conversion - Google Patents

Abstract

1326386 Television standards conversion BRITISH BROADCASTING CORP 15 July 1971 [7 Aug 1970 13 April 1971] 38270/70 and 9292/71 Heading H4F In a television line standards converter for television signals in pulse form, i.e. digital (PCM) signals or signals comprising a plurality of analogue samples, instead of using a plurality of storage elements, e.g. capacitors, equal in number to the number of picture elements in a scanning line as described in Specifications 928,730 and 966,318, a plurality of pulse storage units are used each including a plurality of pulse storage elements corresponding to a capacity of one line or a submultiple thereof, and each unit having only one input and one output, e.g., MOS shift registers or analogue pulse stores of the bucket-brigade type. In a first embodiment, Fig. 1, the input signal is routed by a switch 10 to a plurality of storage units 11 each having a capacity equal to one line (although their capacities may be a submultiple thereof). The digital signal is clocked into the storage units at the input word rate and then read out at the output word rate. Input switch 10 makes connection to the storage units 11 in regular time sequence but the movement of the two ganged output switches 12A and 12B is irregular, their outputs being connected to the inputs of an interpolator 13 which effects interpolation between two lines. By providing more than two output switches more than two lines may be interpolated. Storage units 11 may be read out non-destructively or the information may be recirculated (indicated by dotted line) or rewritten into the units after read out. Operation of this arrangement is as described in the above referred to Specifications and Specification 1,025,512, but the present Specification shows that where interpolation is effected between two input. lines the number of storage units required is equal to the next higher integer than: 1+2n+t 0 /t 1 if to < t 1 (e.g. 405 to 625) or 2+n(1+t 0 /t 1 ) if t 0 > t 1 (e.g. 625 to 405) where t 1 = the duration of an input line period to = the duration of an output line period, and each storage unit has a capacity of 1/n of a line, n being an integer. In a second embodiment for use when t 1 < t 0 , Fig. 4, two line interpolation 21 is effected before re-distribution, a one-line delay 20 being utilized, and the number of storage units 23 is shown to be equal to the next higher integer than n+ 2(t 1 /t 0 ) (i.e. three when each has a capacity of one line (n = 1) and the conversion is 625 to 405). When the input line period t 1 is longer than the output line period t 0 , two lines are simultaneously generated occasionally during each picture period and thus the arrangement of Fig. 6 is employed in which two ganged input switches 32A and 32B are connected to the output of the interpolator and their outputs are fed to a bank of storage units 33 from which they are read in regular sequence by means of an output switch 34. In this embodiment the number of storage units 33 is shown to be equal to the next higher integer than In a further embodiment, Fig. 8, interpolation and time redistribution are combined within a single line storage unit 44, there being several such units for continuous conversion (see Fig. 10). At the start or operation of Fig. 8 no information is held in unit 44 and the switches S1 S2 and S3 are positioned as shown. To formulate an output line from four input lines a, b, c and d each are multiplied by a weighting coefficient α, #, γ and 8 respectively and because of the closed loop 46 coupling the output of unit 44 to its input, the complete interpolated line stored therein comprises αa + #b + γc + #d. Switches S 1 , S 2 and S 3 are now changed to the open circuit positions and the interpolated line is held in the unit until required. When required, switches S 2 and S 3 are changed to the output position and the process of time redistribution is effected by means of an output standard clock. A complete 625 to 405 standards converter using five such line storage units is shown in Fig. 10, the operation of the switches 55 and 57 being controlled by control circuit 59 connected to a sync. converter 60. To check and monitor the correct operation of one of the store units between each interpolation and redistribution operation, a test signal is read into the store unit during read-out of the output line, and held in the store unit until the first line of the next interpolation is read into the store unit, at which time it is read out and checked for correct form. Similarly the input multiplier and adder may be checked. Reference is also made to field-store standards conversion and phase standards conversion.