GB1310751A - Digital arithmetic system for computation of square roots and squares - Google Patents

Abstract

1310751 Squarer or square rooter WESTINGHOUSE ELECTRIC CORP 9 March 1970 [9 April 1969] 11662/70 Headings G4A and G4H The invention relates to a digital arithmetic system for computing squares or square roots. Pulses at a frequency f are fed via gate 22 to a counter having flip-flop stages FFI-FFN. The pulses are also fed to a frequency divider which supplies pulses at frequency f/2 to a further N- stage counter X. Corresponding stages of the counters feed AND gates AI-AN which feed an OR gate 14. The OR gate feeds an N-stage counter Y. It can be shown that if counters X and Y commence at zero then the contents of Y are the square root of the contents of X. The contents of counter Y may be compared with the preset contents of a register (Fig. 3, not shown) and when agreement occurs the gate 22 is inhibited. The contents of X are then the square of the preset number. Counter Y may be coupled to a digital to analog converter feeding a differential amplifier also receiving a varying analog signal. When the differential amplifier inhibits the gate the digital value of the square of the analog signal is in the X counter. Alternatively the X counter may be coupled to the converter (Fig. 5, not shown) so that the square root of the analog signal is obtained in the Y counter.